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inv_imu_defs.h
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1 /*
2 * ________________________________________________________________________________________________________
3 * Copyright (c) 2017 InvenSense Inc. All rights reserved.
4 *
5 * This software, related documentation and any modifications thereto (collectively "Software") is subject
6 * to InvenSense and its licensors' intellectual property rights under U.S. and international copyright
7 * and other intellectual property rights laws.
8 *
9 * InvenSense and its licensors retain all intellectual property and proprietary rights in and to the Software
10 * and any use, reproduction, disclosure or distribution of the Software without an express license agreement
11 * from InvenSense is strictly prohibited.
12 *
13 * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE SOFTWARE IS
14 * PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
15 * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
16 * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL
17 * INVENSENSE BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY
18 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
19 * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THE SOFTWARE.
21 * ________________________________________________________________________________________________________
22 */
23
24 #ifndef _INV_IMU_DEFS_H_
25 #define _INV_IMU_DEFS_H_
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
35 #include <stdint.h>
36
37 /* List whoami values for all device variants*/
38 #define T1000_WHOAMI 0x30
39 #define ICM42607P_WHOAMI 0x60
40 #define ICM42670P_WHOAMI 0x67
41 #define ICM42670T_WHOAMI 0x64
42 #define ICM42670S_WHOAMI 0x69
43 #define ICM42680_WHOAMI 0x80
44 #define ICM42608P_WHOAMI 0x3F
45 #define ICM42671P_WHOAMI 0x52
46 #define ICM42671S_WHOAMI 0x54
47 #define ICM42370P_WHOAMI 0x0D
48
49 #define ICM_REV_A 0xA
50 #define ICM_REV_B 0XB
51
52 /* Define whoami value for the targeted product and make sure the target is valid */
53 #if defined(T1000)
54 #define ICM_WHOAMI T1000_WHOAMI
55 #define ICM_REV ICM_REV_A
56 #define ICM_IS_GYRO_SUPPORTED 1
57 #elif defined(ICM42607P)
58 #define ICM_WHOAMI ICM42607P_WHOAMI
59 #define ICM_REV ICM_REV_A
60 #define ICM_IS_GYRO_SUPPORTED 1
61 #elif defined(ICM42670P)
62 #define ICM_WHOAMI ICM42670P_WHOAMI
63 #define ICM_REV ICM_REV_A
64 #define ICM_IS_GYRO_SUPPORTED 1
65 #elif defined(ICM42670T)
66 #define ICM_WHOAMI ICM42670T_WHOAMI
67 #define ICM_REV ICM_REV_A
68 #define ICM_IS_GYRO_SUPPORTED 1
69 #elif defined(ICM42670S)
70 #define ICM_WHOAMI ICM42670S_WHOAMI
71 #define ICM_REV ICM_REV_A
72 #define ICM_IS_GYRO_SUPPORTED 1
73 #elif defined(ICM42680)
74 #define ICM_WHOAMI ICM42680_WHOAMI
75 #define ICM_REV ICM_REV_A
76 #define ICM_IS_GYRO_SUPPORTED 1
77 #elif defined(ICM42608P)
78 #define ICM_WHOAMI ICM42608P_WHOAMI
79 #define ICM_REV ICM_REV_B
80 #define ICM_IS_GYRO_SUPPORTED 1
81 #elif defined(ICM42671P)
82 #define ICM_WHOAMI ICM42671P_WHOAMI
83 #define ICM_REV ICM_REV_B
84 #define ICM_IS_GYRO_SUPPORTED 1
85 #elif defined(ICM42671S)
86 #define ICM_WHOAMI ICM42671S_WHOAMI
87 #define ICM_REV ICM_REV_B
88 #define ICM_IS_GYRO_SUPPORTED 1
89 #elif defined(ICM42370P)
90 #define ICM_WHOAMI ICM42370P_WHOAMI
91 #define ICM_REV ICM_REV_A
92 #define ICM_IS_GYRO_SUPPORTED 0
93 #else
94 #error "Please define which IMU variant is targeted."
95 #endif
96
97 #if ICM_REV == ICM_REV_A
98 #include "imu/inv_imu_regmap_rev_a.h"
99 #elif ICM_REV == ICM_REV_B
100 #include "imu/inv_imu_regmap_rev_b.h"
101 #endif
102
103 /* ----------------------------------------------------------------------------
104 * Device features
105 *
106 * Next macros define some of the device features such as FIFO, sensor data
107 * size or whoami value.
108 * ---------------------------------------------------------------------------- */
109
110 #define ACCEL_DATA_SIZE 6
111 #define GYRO_DATA_SIZE 6
112 #define TEMP_DATA_SIZE 2
113
114 #define FIFO_HEADER_SIZE 1
115 #define FIFO_ACCEL_DATA_SIZE ACCEL_DATA_SIZE
116 #define FIFO_GYRO_DATA_SIZE GYRO_DATA_SIZE
117 #define FIFO_TEMP_DATA_SIZE 1
118 #define FIFO_TS_FSYNC_SIZE 2
119 #define FIFO_TEMP_HIGH_RES_SIZE 1
120 #define FIFO_ACCEL_GYRO_HIGH_RES_SIZE 3
121
122 #define FIFO_16BYTES_PACKET_SIZE \
123 (FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + \
124 FIFO_TS_FSYNC_SIZE)
125 #define FIFO_20BYTES_PACKET_SIZE \
126 (FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + \
127 FIFO_TS_FSYNC_SIZE + FIFO_TEMP_HIGH_RES_SIZE + FIFO_ACCEL_GYRO_HIGH_RES_SIZE)
128
129 #define FIFO_HEADER_ODR_ACCEL 0x01
130 #define FIFO_HEADER_ODR_GYRO 0x02
131 #define FIFO_HEADER_FSYNC 0x04
132 #define FIFO_HEADER_TMST 0x08
133 #define FIFO_HEADER_HEADER_20 0x10
134 #define FIFO_HEADER_GYRO 0x20
135 #define FIFO_HEADER_ACC 0x40
136 #define FIFO_HEADER_MSG 0x80
137
138 #define INVALID_VALUE_FIFO ((int16_t)0x8000)
139 #define INVALID_VALUE_FIFO_1B ((int8_t)0x80)
140 #define OUT_OF_BOUND_TEMPERATURE_NEG_FIFO_1B ((int8_t)0x81)
141 #define OUT_OF_BOUND_TEMPERATURE_POS_FIFO_1B ((int8_t)0x7F)
142
144 typedef union {
145 unsigned char Byte;
146 struct {
147 #if ICM_IS_GYRO_SUPPORTED
148 unsigned char gyro_odr_different : 1;
149 #else
150 unsigned char reserved1 : 1;
151 #endif
152 unsigned char accel_odr_different : 1;
153 #if ICM_IS_GYRO_SUPPORTED
154 unsigned char fsync_bit : 1;
155 #else
156 unsigned char reserved2 : 1;
157 #endif
158 unsigned char timestamp_bit : 1;
159 unsigned char twentybits_bit : 1;
160 #if ICM_IS_GYRO_SUPPORTED
161 unsigned char gyro_bit : 1;
162 #else
163 unsigned char reserved3 : 1;
164 #endif
165 unsigned char accel_bit : 1;
166 unsigned char msg_bit : 1;
167 } bits;
168 } fifo_header_t;
169
170 /* ----------------------------------------------------------------------------
171 * Device registers description
172 *
173 * Next section defines some of the registers bitfield and declare corresponding
174 * accessors.
175 * Note that descriptors and accessors are not provided for all the registers
176 * but only for the most useful ones.
177 * For all details on registers and bitfields functionalities please refer to
178 * the device datasheet.
179 * ---------------------------------------------------------------------------- */
180
181 /* ---------------------------------------------------------------------------
182 * register bank 0
183 * ---------------------------------------------------------------------------- */
184
185 /*
186 * DEVICE_CONFIG
187 * Register Name : DEVICE_CONFIG
188 */
189
190 /* SPI_MODE */
191 typedef enum {
192 DEVICE_CONFIG_SPI_MODE_1_2 = (0x1 << DEVICE_CONFIG_SPI_MODE_POS),
193 DEVICE_CONFIG_SPI_MODE_0_3 = (0x0 << DEVICE_CONFIG_SPI_MODE_POS),
194 } DEVICE_CONFIG_SPI_MODE_t;
195
196 /* SPI_AP_4WIRE */
197 typedef enum {
198 DEVICE_CONFIG_SPI_4WIRE = (0x1 << DEVICE_CONFIG_SPI_AP_4WIRE_POS),
199 DEVICE_CONFIG_SPI_3WIRE = (0x0 << DEVICE_CONFIG_SPI_AP_4WIRE_POS),
200 } DEVICE_CONFIG_SPI_AP_4WIRE_t;
201
202 /*
203 * SIGNAL_PATH_RESET
204 * Register Name: SIGNAL_PATH_RESET
205 */
206
207 /* SOFT_RESET_DEVICE_CONFIG */
208 typedef enum {
209 SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_EN =
210 (0x01 << SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_POS),
211 SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_DIS =
212 (0x00 << SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_POS),
213 } SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_t;
214
215 /* FIFO_FLUSH */
216 typedef enum {
217 SIGNAL_PATH_RESET_FIFO_FLUSH_EN = (0x01 << SIGNAL_PATH_RESET_FIFO_FLUSH_POS),
218 SIGNAL_PATH_RESET_FIFO_FLUSH_DIS = (0x00 << SIGNAL_PATH_RESET_FIFO_FLUSH_POS),
219 } SIGNAL_PATH_RESET_FIFO_FLUSH_t;
220
221 /*
222 * INT_CONFIG
223 * Register Name: INT_CONFIG
224 */
225
226 /* INT2_MODE */
227 typedef enum {
228 INT_CONFIG_INT2_MODE_LATCHED = (0x01 << INT_CONFIG_INT2_MODE_POS),
229 INT_CONFIG_INT2_MODE_PULSED = (0x00 << INT_CONFIG_INT2_MODE_POS),
230 } INT_CONFIG_INT2_MODE_t;
231
232 /* INT2_DRIVE_CIRCUIT */
233 typedef enum {
234 INT_CONFIG_INT2_DRIVE_CIRCUIT_PP = (0x01 << INT_CONFIG_INT2_DRIVE_CIRCUIT_POS),
235 INT_CONFIG_INT2_DRIVE_CIRCUIT_OD = (0x00 << INT_CONFIG_INT2_DRIVE_CIRCUIT_POS),
236 } INT_CONFIG_INT2_DRIVE_CIRCUIT_t;
237
238 /* INT2_POLARITY */
239 typedef enum {
240 INT_CONFIG_INT2_POLARITY_HIGH = (0x01 << INT_CONFIG_INT2_POLARITY_POS),
241 INT_CONFIG_INT2_POLARITY_LOW = (0x00 << INT_CONFIG_INT2_POLARITY_POS),
242 } INT_CONFIG_INT2_POLARITY_t;
243
244 /* INT1_MODE */
245 typedef enum {
246 INT_CONFIG_INT1_MODE_LATCHED = (0x01 << INT_CONFIG_INT1_MODE_POS),
247 INT_CONFIG_INT1_MODE_PULSED = (0x00 << INT_CONFIG_INT1_MODE_POS),
248 } INT_CONFIG_INT1_MODE_t;
249
250 /* INT1_DRIVE_CIRCUIT */
251 typedef enum {
252 INT_CONFIG_INT1_DRIVE_CIRCUIT_PP = (0x01 << INT_CONFIG_INT1_DRIVE_CIRCUIT_POS),
253 INT_CONFIG_INT1_DRIVE_CIRCUIT_OD = (0x00 << INT_CONFIG_INT1_DRIVE_CIRCUIT_POS),
254 } INT_CONFIG_INT1_DRIVE_CIRCUIT_t;
255
256 /* INT1_POLARITY */
257 typedef enum {
258 INT_CONFIG_INT1_POLARITY_HIGH = 0x01,
259 INT_CONFIG_INT1_POLARITY_LOW = 0x00,
260 } INT_CONFIG_INT1_POLARITY_t;
261
262 /*
263 * PWR_MGMT0
264 * Register Name: PWR_MGMT0
265 */
266
267 /* ACCEL_LP_CLK_SEL */
268 typedef enum {
269 PWR_MGMT0_ACCEL_LP_CLK_WUOSC = (0x00 << PWR_MGMT0_ACCEL_LP_CLK_SEL_POS),
270 PWR_MGMT0_ACCEL_LP_CLK_RCOSC = (0x01 << PWR_MGMT0_ACCEL_LP_CLK_SEL_POS),
271 } PWR_MGMT0_ACCEL_LP_CLK_t;
272
273 /* IDLE */
274 typedef enum {
275 PWR_MGMT0_IDLE_DIS = (0x01 << PWR_MGMT0_IDLE_POS),
276 PWR_MGMT0_IDLE_EN = (0x00 << PWR_MGMT0_IDLE_POS),
277 } PWR_MGMT0_IDLE_t;
278
279 #if ICM_IS_GYRO_SUPPORTED
280 /* GYRO_MODE */
281 typedef enum {
282 PWR_MGMT0_GYRO_MODE_LN = (0x03 << PWR_MGMT0_GYRO_MODE_POS),
283 PWR_MGMT0_GYRO_MODE_LP = (0x02 << PWR_MGMT0_GYRO_MODE_POS),
284 PWR_MGMT0_GYRO_MODE_STANDBY = (0x01 << PWR_MGMT0_GYRO_MODE_POS),
285 PWR_MGMT0_GYRO_MODE_OFF = (0x00 << PWR_MGMT0_GYRO_MODE_POS),
286 } PWR_MGMT0_GYRO_MODE_t;
287 #endif
288
289 /* ACCEL_MODE */
290 typedef enum {
291 PWR_MGMT0_ACCEL_MODE_LN = 0x03,
292 PWR_MGMT0_ACCEL_MODE_LP = 0x02,
293 PWR_MGMT0_ACCEL_MODE_OFF = 0x00,
294 } PWR_MGMT0_ACCEL_MODE_t;
295
296 #if ICM_IS_GYRO_SUPPORTED
297 /*
298 * GYRO_CONFIG0
299 * Register Name: GYRO_CONFIG0
300 */
301
302 /* GYRO_FS_SEL*/
303 typedef enum {
304 GYRO_CONFIG0_FS_SEL_250dps = (3 << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS),
305 GYRO_CONFIG0_FS_SEL_500dps = (2 << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS),
306 GYRO_CONFIG0_FS_SEL_1000dps = (1 << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS),
307 GYRO_CONFIG0_FS_SEL_2000dps = (0 << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS),
308 } GYRO_CONFIG0_FS_SEL_t;
309
310 /* GYRO_ODR */
311 typedef enum {
312 GYRO_CONFIG0_ODR_1_5625_HZ = 0xF,
313 GYRO_CONFIG0_ODR_3_125_HZ = 0xE,
314 GYRO_CONFIG0_ODR_6_25_HZ = 0xD,
315 GYRO_CONFIG0_ODR_12_5_HZ = 0xC,
316 GYRO_CONFIG0_ODR_25_HZ = 0xB,
317 GYRO_CONFIG0_ODR_50_HZ = 0xA,
318 GYRO_CONFIG0_ODR_100_HZ = 0x9,
319 GYRO_CONFIG0_ODR_200_HZ = 0x8,
320 GYRO_CONFIG0_ODR_400_HZ = 0x7,
321 GYRO_CONFIG0_ODR_800_HZ = 0x6,
322 GYRO_CONFIG0_ODR_1600_HZ = 0x5,
323 } GYRO_CONFIG0_ODR_t;
324 #endif
325
326 /*
327 * ACCEL_CONFIG0
328 * Register Name: ACCEL_CONFIG0
329 */
330
331 /* ACCEL_FS_SEL */
332 typedef enum {
333 ACCEL_CONFIG0_FS_SEL_2g = (0x3 << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS),
334 ACCEL_CONFIG0_FS_SEL_4g = (0x2 << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS),
335 ACCEL_CONFIG0_FS_SEL_8g = (0x1 << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS),
336 ACCEL_CONFIG0_FS_SEL_16g = (0x0 << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS),
337 } ACCEL_CONFIG0_FS_SEL_t;
338
339 /* ACCEL_ODR */
340 typedef enum {
341 ACCEL_CONFIG0_ODR_1_5625_HZ = 0xF,
342 ACCEL_CONFIG0_ODR_3_125_HZ = 0xE,
343 ACCEL_CONFIG0_ODR_6_25_HZ = 0xD,
344 ACCEL_CONFIG0_ODR_12_5_HZ = 0xC,
345 ACCEL_CONFIG0_ODR_25_HZ = 0xB,
346 ACCEL_CONFIG0_ODR_50_HZ = 0xA,
347 ACCEL_CONFIG0_ODR_100_HZ = 0x9,
348 ACCEL_CONFIG0_ODR_200_HZ = 0x8,
349 ACCEL_CONFIG0_ODR_400_HZ = 0x7,
350 ACCEL_CONFIG0_ODR_800_HZ = 0x6,
351 ACCEL_CONFIG0_ODR_1600_HZ = 0x5,
352 } ACCEL_CONFIG0_ODR_t;
353
354 #if ICM_IS_GYRO_SUPPORTED
355 /*
356 * GYRO_CONFIG1
357 * Register Name: GYRO_CONFIG1
358 */
359
360 /* GYRO_UI_FILT_BW_IND */
361 typedef enum {
362 GYRO_CONFIG1_GYRO_FILT_BW_16 = (0x07 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS),
363 GYRO_CONFIG1_GYRO_FILT_BW_25 = (0x06 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS),
364 GYRO_CONFIG1_GYRO_FILT_BW_34 = (0x05 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS),
365 GYRO_CONFIG1_GYRO_FILT_BW_53 = (0x04 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS),
366 GYRO_CONFIG1_GYRO_FILT_BW_73 = (0x03 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS),
367 GYRO_CONFIG1_GYRO_FILT_BW_121 = (0x02 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS),
368 GYRO_CONFIG1_GYRO_FILT_BW_180 = (0x01 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS),
369 GYRO_CONFIG1_GYRO_FILT_BW_NO_FILTER = (0x00 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS),
370 } GYRO_CONFIG1_GYRO_FILT_BW_t;
371 #endif
372
373 /*
374 * ACCEL_CONFIG1
375 * Register Name: ACCEL_CONFIG1
376 */
377
378 /* ACCEL_UI_AVG_IND */
379 typedef enum {
380 ACCEL_CONFIG1_ACCEL_FILT_AVG_64 = (0x5 << ACCEL_CONFIG1_ACCEL_UI_AVG_POS),
381 ACCEL_CONFIG1_ACCEL_FILT_AVG_32 = (0x4 << ACCEL_CONFIG1_ACCEL_UI_AVG_POS),
382 ACCEL_CONFIG1_ACCEL_FILT_AVG_16 = (0x3 << ACCEL_CONFIG1_ACCEL_UI_AVG_POS),
383 ACCEL_CONFIG1_ACCEL_FILT_AVG_8 = (0x2 << ACCEL_CONFIG1_ACCEL_UI_AVG_POS),
384 ACCEL_CONFIG1_ACCEL_FILT_AVG_4 = (0x1 << ACCEL_CONFIG1_ACCEL_UI_AVG_POS),
385 ACCEL_CONFIG1_ACCEL_FILT_AVG_2 = (0x0 << ACCEL_CONFIG1_ACCEL_UI_AVG_POS),
386 } ACCEL_CONFIG1_ACCEL_FILT_AVG_t;
387
388 /* ACCEL_UI_FILT_BW_IND */
389 typedef enum {
390 ACCEL_CONFIG1_ACCEL_FILT_BW_16 = (0x7 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS),
391 ACCEL_CONFIG1_ACCEL_FILT_BW_25 = (0x6 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS),
392 ACCEL_CONFIG1_ACCEL_FILT_BW_34 = (0x5 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS),
393 ACCEL_CONFIG1_ACCEL_FILT_BW_53 = (0x4 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS),
394 ACCEL_CONFIG1_ACCEL_FILT_BW_73 = (0x3 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS),
395 ACCEL_CONFIG1_ACCEL_FILT_BW_121 = (0x2 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS),
396 ACCEL_CONFIG1_ACCEL_FILT_BW_180 = (0x1 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS),
397 ACCEL_CONFIG1_ACCEL_FILT_BW_NO_FILTER = (0x0 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS),
398 } ACCEL_CONFIG1_ACCEL_FILT_BW_t;
399
400 /*
401 * APEX_CONFIG0
402 * Register Name: APEX_CONFIG0
403 */
404
405 /* DMP_POWER_SAVE_EN */
406 typedef enum {
407 APEX_CONFIG0_DMP_POWER_SAVE_EN = (0x1 << APEX_CONFIG0_DMP_POWER_SAVE_EN_POS),
408 APEX_CONFIG0_DMP_POWER_SAVE_DIS = (0x0 << APEX_CONFIG0_DMP_POWER_SAVE_EN_POS),
409 } APEX_CONFIG0_DMP_POWER_SAVE_t;
410
411 /* DMP_INIT_EN */
412 typedef enum {
413 APEX_CONFIG0_DMP_INIT_EN = (0x01 << APEX_CONFIG0_DMP_INIT_EN_POS),
414 APEX_CONFIG0_DMP_INIT_DIS = (0x00 << APEX_CONFIG0_DMP_INIT_EN_POS),
415 } APEX_CONFIG0_DMP_INIT_t;
416
417 /* DMP_MEM_RESET */
418 typedef enum {
419 APEX_CONFIG0_DMP_MEM_RESET_APEX_ST_EN = (0x01 << APEX_CONFIG0_DMP_MEM_RESET_EN_POS),
420 APEX_CONFIG0_DMP_MEM_RESET_DIS = (0x00 << APEX_CONFIG0_DMP_MEM_RESET_EN_POS),
421 } APEX_CONFIG0_DMP_MEM_RESET_t;
422
423 /*
424 * APEX_CONFIG1
425 * Register Name: APEX_CONFIG1
426 */
427
428 /* SMD_ENABLE */
429 typedef enum {
430 APEX_CONFIG1_SMD_ENABLE_DIS = (0x00 << APEX_CONFIG1_SMD_ENABLE_POS),
431 APEX_CONFIG1_SMD_ENABLE_EN = (0x01 << APEX_CONFIG1_SMD_ENABLE_POS),
432 } APEX_CONFIG1_SMD_ENABLE_t;
433
434 /* FF_ENABLE */
435 typedef enum {
436 APEX_CONFIG1_FF_ENABLE_DIS = (0x00 << APEX_CONFIG1_FF_ENABLE_POS),
437 APEX_CONFIG1_FF_ENABLE_EN = (0x01 << APEX_CONFIG1_FF_ENABLE_POS),
438 } APEX_CONFIG1_FF_ENABLE_t;
439
440 /* TILT_ENABLE */
441 typedef enum {
442 APEX_CONFIG1_TILT_ENABLE_DIS = (0x0 << APEX_CONFIG1_TILT_ENABLE_POS),
443 APEX_CONFIG1_TILT_ENABLE_EN = (0x1 << APEX_CONFIG1_TILT_ENABLE_POS),
444 } APEX_CONFIG1_TILT_ENABLE_t;
445
446 /* PED_ENABLE */
447 typedef enum {
448 APEX_CONFIG1_PED_ENABLE_DIS = (0x0 << APEX_CONFIG1_PED_ENABLE_POS),
449 APEX_CONFIG1_PED_ENABLE_EN = (0x1 << APEX_CONFIG1_PED_ENABLE_POS),
450 } APEX_CONFIG1_PED_ENABLE_t;
451
452 /* DMP_ODR */
453 typedef enum {
454 APEX_CONFIG1_DMP_ODR_25Hz = (0x0 << APEX_CONFIG1_DMP_ODR_POS),
455 APEX_CONFIG1_DMP_ODR_50Hz = (0x2 << APEX_CONFIG1_DMP_ODR_POS),
456 APEX_CONFIG1_DMP_ODR_100Hz = (0x3 << APEX_CONFIG1_DMP_ODR_POS),
457 APEX_CONFIG1_DMP_ODR_400Hz = (0x1 << APEX_CONFIG1_DMP_ODR_POS),
458 } APEX_CONFIG1_DMP_ODR_t;
459
460 /*
461 * WOM_CONFIG
462 * Register Name: WOM_CONFIG
463 */
464
465 /* WOM_INT_DUR */
466 typedef enum {
467 WOM_CONFIG_WOM_INT_DUR_1_SMPL = (0x00 << WOM_CONFIG_WOM_INT_DUR_POS),
468 WOM_CONFIG_WOM_INT_DUR_2_SMPL = (0x01 << WOM_CONFIG_WOM_INT_DUR_POS),
469 WOM_CONFIG_WOM_INT_DUR_3_SMPL = (0x02 << WOM_CONFIG_WOM_INT_DUR_POS),
470 WOM_CONFIG_WOM_INT_DUR_4_SMPL = (0x03 << WOM_CONFIG_WOM_INT_DUR_POS),
471 } WOM_CONFIG_WOM_INT_DUR_t;
472
473 /* WOM_INT_MODE */
474 typedef enum {
475 WOM_CONFIG_WOM_INT_MODE_ANDED = (0x01 << WOM_CONFIG_WOM_INT_MODE_POS),
476 WOM_CONFIG_WOM_INT_MODE_ORED = (0x00 << WOM_CONFIG_WOM_INT_MODE_POS),
477 } WOM_CONFIG_WOM_INT_MODE_t;
478
479 /* WOM_MODE */
480 typedef enum {
481 WOM_CONFIG_WOM_MODE_CMP_PREV = (0x01 << WOM_CONFIG_WOM_MODE_POS),
482 WOM_CONFIG_WOM_MODE_CMP_INIT = (0x00 << WOM_CONFIG_WOM_MODE_POS),
483 } WOM_CONFIG_WOM_MODE_t;
484
485 /* WOM_ENABLE */
486 typedef enum {
487 WOM_CONFIG_WOM_EN_ENABLE = (0x01 << WOM_CONFIG_WOM_EN_POS),
488 WOM_CONFIG_WOM_EN_DISABLE = (0x00 << WOM_CONFIG_WOM_EN_POS),
489 } WOM_CONFIG_WOM_EN_t;
490
491 /*
492 * FIFO_CONFIG1
493 * Register Name: FIFO_CONFIG
494 */
495
496 /* FIFO_MODE */
497 typedef enum {
498 FIFO_CONFIG1_FIFO_MODE_SNAPSHOT = (0x01 << FIFO_CONFIG1_FIFO_MODE_POS),
499 FIFO_CONFIG1_FIFO_MODE_STREAM = (0x00 << FIFO_CONFIG1_FIFO_MODE_POS)
500 } FIFO_CONFIG1_FIFO_MODE_t;
501
502 /* FIFO_BYPASS */
503 typedef enum {
504 FIFO_CONFIG1_FIFO_BYPASS_ON = (0x01 << FIFO_CONFIG1_FIFO_BYPASS_POS),
505 FIFO_CONFIG1_FIFO_BYPASS_OFF = (0x00 << FIFO_CONFIG1_FIFO_BYPASS_POS),
506 } FIFO_CONFIG1_FIFO_BYPASS_t;
507
508 /*
509 * APEX_DATA0 and APEX_DATA1
510 * Register Name: APEX_DATA0 and APEX_DATA1
511 */
512
513 /* Pedometer output */
514 typedef struct APEX_DATA_STEP_ACTIVITY {
515 uint16_t step_cnt; /* Number of steps taken */
516 uint8_t step_cadence; /* Walk/run cadence in number of samples. Format is u6.2.*/
517 uint8_t activity_class; /* Detected activity unknown (0), walk (1) or run (2) */
518 } APEX_DATA_STEP_ACTIVITY_t;
519
520 /*
521 * APEX_DATA3
522 * Register Name: APEX_DATA3
523 */
524
525 /* DMP_IDLE */
526 typedef enum {
527 APEX_DATA3_DMP_IDLE_ON = (0x01 << APEX_DATA3_DMP_IDLE_POS),
528 APEX_DATA3_DMP_IDLE_OFF = (0x00 << APEX_DATA3_DMP_IDLE_POS),
529 } APEX_DATA3_DMP_IDLE_OFF_t;
530
531 /* ACTIVITY_CLASS */
532 typedef enum {
533 APEX_DATA3_ACTIVITY_CLASS_OTHER = 0x0,
534 APEX_DATA3_ACTIVITY_CLASS_WALK = 0x1,
535 APEX_DATA3_ACTIVITY_CLASS_RUN = 0x2,
536 } APEX_DATA3_ACTIVITY_CLASS_t;
537
538 /*
539 * INTF_CONFIG0
540 * Register Name: INTF_CONFIG0
541 */
542
543 /* FIFO_COUNT_REC */
544 typedef enum {
545 INTF_CONFIG0_FIFO_COUNT_REC_RECORD = (0x01 << INTF_CONFIG0_FIFO_COUNT_FORMAT_POS),
546 INTF_CONFIG0_FIFO_COUNT_REC_BYTE = (0x00 << INTF_CONFIG0_FIFO_COUNT_FORMAT_POS),
547 } INTF_CONFIG0_FIFO_COUNT_REC_t;
548
549 /* FIFO_COUNT_ENDIAN */
550 typedef enum {
551 INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN = (0x01 << INTF_CONFIG0_FIFO_COUNT_ENDIAN_POS),
552 INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN = (0x00 << INTF_CONFIG0_FIFO_COUNT_ENDIAN_POS),
553 } INTF_CONFIG0_FIFO_COUNT_ENDIAN_t;
554
555 /* DATA_ENDIAN */
556 typedef enum {
557 INTF_CONFIG0_DATA_BIG_ENDIAN = (0x01 << INTF_CONFIG0_SENSOR_DATA_ENDIAN_POS),
558 INTF_CONFIG0_DATA_LITTLE_ENDIAN = (0x00 << INTF_CONFIG0_SENSOR_DATA_ENDIAN_POS),
559 } INTF_CONFIG0_DATA_ENDIAN_t;
560
561 /* ---------------------------------------------------------------------------
562 * register bank MREG1
563 * ---------------------------------------------------------------------------- */
564
565 /*
566 * TMST_CONFIG1_MREG1
567 * Register Name: TMST_CONFIG1
568 */
569
570 /* TMST_RES */
571 typedef enum {
572 TMST_CONFIG1_RESOL_16us = (0x01 << TMST_CONFIG1_TMST_RES_POS),
573 TMST_CONFIG1_RESOL_1us = (0x00 << TMST_CONFIG1_TMST_RES_POS),
574 } TMST_CONFIG1_RESOL_t;
575
576 /* TMST_FSYNC */
577 typedef enum {
578 TMST_CONFIG1_TMST_FSYNC_EN = (0x01 << TMST_CONFIG1_TMST_FSYNC_EN_POS),
579 TMST_CONFIG1_TMST_FSYNC_DIS = (0x00 << TMST_CONFIG1_TMST_FSYNC_EN_POS),
580 } TMST_CONFIG1_TMST_FSYNC_EN_t;
581
582 /* TMST_EN */
583 typedef enum {
584 TMST_CONFIG1_TMST_EN = 0x01,
585 TMST_CONFIG1_TMST_DIS = 0x00,
586 } TMST_CONFIG1_TMST_EN_t;
587
588 /*
589 * FIFO_CONFIG5_MREG1
590 * Register Name: FIFO_CONFIG5
591 */
592 /* FIFO_WM_GT_TH */
593 typedef enum {
594 FIFO_CONFIG5_WM_GT_TH_EN = (0x1 << FIFO_CONFIG5_FIFO_WM_GT_TH_POS),
595 FIFO_CONFIG5_WM_GT_TH_DIS = (0x0 << FIFO_CONFIG5_FIFO_WM_GT_TH_POS),
596 } FIFO_CONFIG5_WM_GT_t;
597
598 /* FIFO_HIRES_EN */
599 typedef enum {
600 FIFO_CONFIG5_HIRES_EN = (0x1 << FIFO_CONFIG5_FIFO_HIRES_EN_POS),
601 FIFO_CONFIG5_HIRES_DIS = (0x0 << FIFO_CONFIG5_FIFO_HIRES_EN_POS),
602 } FIFO_CONFIG5_HIRES_t;
603
604 /* FIFO_TMST_FSYNC_EN */
605 typedef enum {
606 FIFO_CONFIG5_TMST_FSYNC_EN = (0x1 << FIFO_CONFIG5_FIFO_TMST_FSYNC_EN_POS),
607 FIFO_CONFIG5_TMST_FSYNC_DIS = (0x0 << FIFO_CONFIG5_FIFO_TMST_FSYNC_EN_POS),
608 } FIFO_CONFIG5_TMST_FSYNC_t;
609
610 #if ICM_IS_GYRO_SUPPORTED
611 /* FIFO_GYRO_EN */
612 typedef enum {
613 FIFO_CONFIG5_GYRO_EN = (0x1 << FIFO_CONFIG5_FIFO_GYRO_EN_POS),
614 FIFO_CONFIG5_GYRO_DIS = (0x0 << FIFO_CONFIG5_FIFO_GYRO_EN_POS),
615 } FIFO_CONFIG5_GYRO_t;
616 #endif
617
618 /* FIFO_ACCEL_EN*/
619 typedef enum {
620 FIFO_CONFIG5_ACCEL_EN = 0x01,
621 FIFO_CONFIG5_ACCEL_DIS = 0x00,
622 } FIFO_CONFIG5_ACCEL_t;
623
624 #if ICM_IS_GYRO_SUPPORTED
625 /*
626 * FSYNC_CONFIG_MREG1
627 * Register Name: FSYNC_CONFIG
628 */
629
630 /* FSYNC_UI_SEL */
631 typedef enum {
632 FSYNC_CONFIG_UI_SEL_NO = (0x0 << FSYNC_CONFIG_FSYNC_UI_SEL_POS),
633 FSYNC_CONFIG_UI_SEL_TEMP = (0x1 << FSYNC_CONFIG_FSYNC_UI_SEL_POS),
634 FSYNC_CONFIG_UI_SEL_GYRO_X = (0x2 << FSYNC_CONFIG_FSYNC_UI_SEL_POS),
635 FSYNC_CONFIG_UI_SEL_GYRO_Y = (0x3 << FSYNC_CONFIG_FSYNC_UI_SEL_POS),
636 FSYNC_CONFIG_UI_SEL_GYRO_Z = (0x4 << FSYNC_CONFIG_FSYNC_UI_SEL_POS),
637 FSYNC_CONFIG_UI_SEL_ACCEL_X = (0x5 << FSYNC_CONFIG_FSYNC_UI_SEL_POS),
638 FSYNC_CONFIG_UI_SEL_ACCEL_Y = (0x6 << FSYNC_CONFIG_FSYNC_UI_SEL_POS),
639 FSYNC_CONFIG_UI_SEL_ACCEL_Z = (0x7 << FSYNC_CONFIG_FSYNC_UI_SEL_POS),
640 } FSYNC_CONFIG_UI_SEL_t;
641 #endif
642
643 /*
644 * ST_CONFIG_MREG1
645 * Register Name: ST_CONFIG
646 */
647 typedef enum {
648 ST_CONFIG_16_SAMPLES = (0 << ST_CONFIG_ST_NUMBER_SAMPLE_POS),
649 ST_CONFIG_200_SAMPLES = (1 << ST_CONFIG_ST_NUMBER_SAMPLE_POS),
650 } ST_CONFIG_NUM_SAMPLES_t;
651
652 typedef enum {
653 ST_CONFIG_ACCEL_ST_LIM_50 = (7 << ST_CONFIG_ACCEL_ST_LIM_POS),
654 } ST_CONFIG_ACCEL_ST_LIM_t;
655
656 #if ICM_IS_GYRO_SUPPORTED
657 typedef enum {
658 ST_CONFIG_GYRO_ST_LIM_50 = (7 << ST_CONFIG_GYRO_ST_LIM_POS),
659 } ST_CONFIG_GYRO_ST_LIM_t;
660 #endif
661
662 /*
663 * SELFTEST_MREG1
664 * Register Name: SELFTEST
665 */
666
667 /* GYRO_ST_EN and ACCEL_ST_EN */
668 typedef enum {
669 SELFTEST_DIS = 0,
670 SELFTEST_ACCEL_EN = SELFTEST_ACCEL_ST_EN_MASK,
671 #if ICM_IS_GYRO_SUPPORTED
672 SELFTEST_GYRO_EN = SELFTEST_GYRO_ST_EN_MASK,
673 SELFTEST_EN = (SELFTEST_ACCEL_ST_EN_MASK | SELFTEST_GYRO_ST_EN_MASK)
674 #endif
675 } SELFTEST_ACCEL_GYRO_ST_EN_t;
676
677 /*
678 * OTP_CONFIG_MREG1
679 * Register Name: OTP_CONFIG
680 */
681
682 /* OTP_CONFIG */
683 typedef enum {
684 OTP_CONFIG_OTP_COPY_TRIM = (1 << OTP_CONFIG_OTP_COPY_MODE_POS),
685 OTP_CONFIG_OTP_COPY_ST_DATA = (3 << OTP_CONFIG_OTP_COPY_MODE_POS),
686 } OTP_CONFIG_COPY_MODE_t;
687
688 /*
689 * APEX_CONFIG2_MREG1
690 * Register Name: APEX_CONFIG2
691 */
692
693 /* LOW_ENERGY_AMP_TH_SEL */
694 typedef enum {
695 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_30_MG = (0 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
696 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_35_MG = (1 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
697 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_40_MG = (2 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
698 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_45_MG = (3 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
699 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_50_MG = (4 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
700 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_55_MG = (5 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
701 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_60_MG = (6 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
702 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_65_MG = (7 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
703 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_70_MG = (8 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
704 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_75_MG = (9 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
705 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_80_MG = (10 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
706 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_85_MG = (11 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
707 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_90_MG = (12 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
708 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_95_MG = (13 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
709 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_100_MG = (14 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
710 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_105_MG = (15 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS),
711 } APEX_CONFIG2_LOW_ENERGY_AMP_TH_t;
712
713 /* DMP_POWER_SAVE_TIME_SEL */
714 typedef enum {
715 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_0_S = 0x0,
716 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_4_S = 0x1,
717 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_8_S = 0x2,
718 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_12_S = 0x3,
719 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_16_S = 0x4,
720 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_20_S = 0x5,
721 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_24_S = 0x6,
722 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_28_S = 0x7,
723 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_32_S = 0x8,
724 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_36_S = 0x9,
725 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_40_S = 0xA,
726 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_44_S = 0xB,
727 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_48_S = 0xC,
728 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_52_S = 0xD,
729 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_56_S = 0xE,
730 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_60_S = 0xF,
731 } APEX_CONFIG2_DMP_POWER_SAVE_TIME_t;
732
733 /*
734 * APEX_CONFIG3_MREG1
735 * Register Name: APEX_CONFIG3
736 */
737
738 /* PEDO_AMP_TH_SEL */
739 typedef enum {
740 APEX_CONFIG3_PEDO_AMP_TH_30_MG = (0 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
741 APEX_CONFIG3_PEDO_AMP_TH_34_MG = (1 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
742 APEX_CONFIG3_PEDO_AMP_TH_38_MG = (2 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
743 APEX_CONFIG3_PEDO_AMP_TH_42_MG = (3 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
744 APEX_CONFIG3_PEDO_AMP_TH_46_MG = (4 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
745 APEX_CONFIG3_PEDO_AMP_TH_50_MG = (5 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
746 APEX_CONFIG3_PEDO_AMP_TH_54_MG = (6 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
747 APEX_CONFIG3_PEDO_AMP_TH_58_MG = (7 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
748 APEX_CONFIG3_PEDO_AMP_TH_62_MG = (8 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
749 APEX_CONFIG3_PEDO_AMP_TH_66_MG = (9 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
750 APEX_CONFIG3_PEDO_AMP_TH_70_MG = (10 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
751 APEX_CONFIG3_PEDO_AMP_TH_74_MG = (11 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
752 APEX_CONFIG3_PEDO_AMP_TH_78_MG = (12 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
753 APEX_CONFIG3_PEDO_AMP_TH_82_MG = (13 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
754 APEX_CONFIG3_PEDO_AMP_TH_86_MG = (14 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
755 APEX_CONFIG3_PEDO_AMP_TH_90_MG = (15 << APEX_CONFIG3_PED_AMP_TH_SEL_POS),
756 } APEX_CONFIG3_PEDO_AMP_TH_t;
757
758 /*
759 * APEX_CONFIG4_MREG1
760 * Register Name: APEX_CONFIG4
761 */
762
763 /* PEDO_SB_TIMER_TH_SEL */
764 typedef enum {
765 APEX_CONFIG4_PEDO_SB_TIMER_TH_50_SAMPLES = (0 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS),
766 APEX_CONFIG4_PEDO_SB_TIMER_TH_75_SAMPLES = (1 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS),
767 APEX_CONFIG4_PEDO_SB_TIMER_TH_100_SAMPLES = (2 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS),
768 APEX_CONFIG4_PEDO_SB_TIMER_TH_125_SAMPLES = (3 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS),
769 APEX_CONFIG4_PEDO_SB_TIMER_TH_150_SAMPLES = (4 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS),
770 APEX_CONFIG4_PEDO_SB_TIMER_TH_175_SAMPLES = (5 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS),
771 APEX_CONFIG4_PEDO_SB_TIMER_TH_200_SAMPLES = (6 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS),
772 APEX_CONFIG4_PEDO_SB_TIMER_TH_225_SAMPLES = (7 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS),
773 } APEX_CONFIG4_PEDO_SB_TIMER_TH_t;
774
775 /* PEDO_HI_ENRGY_TH_SEL */
776 typedef enum {
777 APEX_CONFIG4_PEDO_HI_ENRGY_TH_88_MG = (0 << APEX_CONFIG4_PED_HI_EN_TH_SEL_POS),
778 APEX_CONFIG4_PEDO_HI_ENRGY_TH_104_MG = (1 << APEX_CONFIG4_PED_HI_EN_TH_SEL_POS),
779 APEX_CONFIG4_PEDO_HI_ENRGY_TH_133_MG = (2 << APEX_CONFIG4_PED_HI_EN_TH_SEL_POS),
780 APEX_CONFIG4_PEDO_HI_ENRGY_TH_155_MG = (3 << APEX_CONFIG4_PED_HI_EN_TH_SEL_POS),
781 } APEX_CONFIG4_PEDO_HI_ENRGY_TH_t;
782
783 /*
784 * APEX_CONFIG5_MREG1
785 * Register Name: APEX_CONFIG5
786 */
787
788 /* TILT_WAIT_TIME_SEL */
789 typedef enum {
790 APEX_CONFIG5_TILT_WAIT_TIME_0_S = (0 << APEX_CONFIG5_TILT_WAIT_TIME_SEL_POS),
791 APEX_CONFIG5_TILT_WAIT_TIME_2_S = (1 << APEX_CONFIG5_TILT_WAIT_TIME_SEL_POS),
792 APEX_CONFIG5_TILT_WAIT_TIME_4_S = (2 << APEX_CONFIG5_TILT_WAIT_TIME_SEL_POS),
793 APEX_CONFIG5_TILT_WAIT_TIME_6_S = (3 << APEX_CONFIG5_TILT_WAIT_TIME_SEL_POS),
794 } APEX_CONFIG5_TILT_WAIT_TIME_t;
795
796 /* LOWG_PEAK_TH_HYST_SEL */
797 typedef enum {
798 APEX_CONFIG5_LOWG_PEAK_TH_HYST_31_MG = (0 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS),
799 APEX_CONFIG5_LOWG_PEAK_TH_HYST_63_MG = (1 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS),
800 APEX_CONFIG5_LOWG_PEAK_TH_HYST_94_MG = (2 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS),
801 APEX_CONFIG5_LOWG_PEAK_TH_HYST_125_MG = (3 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS),
802 APEX_CONFIG5_LOWG_PEAK_TH_HYST_156_MG = (4 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS),
803 APEX_CONFIG5_LOWG_PEAK_TH_HYST_188_MG = (5 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS),
804 APEX_CONFIG5_LOWG_PEAK_TH_HYST_219_MG = (6 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS),
805 APEX_CONFIG5_LOWG_PEAK_TH_HYST_250_MG = (7 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS),
806 } APEX_CONFIG5_LOWG_PEAK_TH_HYST_t;
807
808 /* HIGHG_PEAK_TH_HYST_SEL */
809 typedef enum {
810 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_31_MG = (0 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS),
811 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_63_MG = (1 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS),
812 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_94_MG = (2 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS),
813 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_125_MG = (3 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS),
814 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_156_MG = (4 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS),
815 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_188_MG = (5 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS),
816 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_219_MG = (6 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS),
817 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_250_MG = (7 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS),
818 } APEX_CONFIG5_HIGHG_PEAK_TH_HYST_t;
819
820 /*
821 * APEX_CONFIG9_MREG1
822 * Register Name: APEX_CONFIG9
823 */
824
825 /* FF_DEBOUNCE_DURATION_SEL */
826 typedef enum {
827 APEX_CONFIG9_FF_DEBOUNCE_DURATION_0_MS = (0 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
828 APEX_CONFIG9_FF_DEBOUNCE_DURATION_1250_MS = (1 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
829 APEX_CONFIG9_FF_DEBOUNCE_DURATION_1375_MS = (2 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
830 APEX_CONFIG9_FF_DEBOUNCE_DURATION_1500_MS = (3 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
831 APEX_CONFIG9_FF_DEBOUNCE_DURATION_1625_MS = (4 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
832 APEX_CONFIG9_FF_DEBOUNCE_DURATION_1750_MS = (5 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
833 APEX_CONFIG9_FF_DEBOUNCE_DURATION_1875_MS = (6 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
834 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2000_MS = (7 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
835 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2125_MS = (8 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
836 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2250_MS = (9 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
837 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2375_MS = (10 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
838 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2500_MS = (11 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
839 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2625_MS = (12 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
840 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2750_MS = (13 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
841 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2875_MS = (14 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
842 APEX_CONFIG9_FF_DEBOUNCE_DURATION_3000_MS = (15 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS),
843 } APEX_CONFIG9_FF_DEBOUNCE_DURATION_t;
844
845 /* SMD_SENSITIVITY_SEL */
846 typedef enum {
847 APEX_CONFIG9_SMD_SENSITIVITY_0 = (0 << APEX_CONFIG9_SMD_SENSITIVITY_SEL_POS),
848 APEX_CONFIG9_SMD_SENSITIVITY_1 = (1 << APEX_CONFIG9_SMD_SENSITIVITY_SEL_POS),
849 APEX_CONFIG9_SMD_SENSITIVITY_2 = (2 << APEX_CONFIG9_SMD_SENSITIVITY_SEL_POS),
850 APEX_CONFIG9_SMD_SENSITIVITY_3 = (3 << APEX_CONFIG9_SMD_SENSITIVITY_SEL_POS),
851 APEX_CONFIG9_SMD_SENSITIVITY_4 = (4 << APEX_CONFIG9_SMD_SENSITIVITY_SEL_POS),
852 } APEX_CONFIG9_SMD_SENSITIVITY_t;
853
854 /* SMD_SENSITIVITY_MODE */
855 typedef enum {
856 APEX_CONFIG9_SENSITIVITY_MODE_NORMAL = (0 << APEX_CONFIG9_SENSITIVITY_MODE_POS),
857 APEX_CONFIG9_SENSITIVITY_MODE_SLOW_WALK = (1 << APEX_CONFIG9_SENSITIVITY_MODE_POS),
858 } APEX_CONFIG9_SENSITIVITY_MODE_t;
859
860 /*
861 * APEX_CONFIG10_MREG1
862 * Register Name: APEX_CONFIG10
863 */
864
865 /* LOWG_PEAK_TH_SEL */
866 typedef enum {
867 APEX_CONFIG10_LOWG_PEAK_TH_31_MG = (0x00 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
868 APEX_CONFIG10_LOWG_PEAK_TH_63_MG = (0x01 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
869 APEX_CONFIG10_LOWG_PEAK_TH_94_MG = (0x02 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
870 APEX_CONFIG10_LOWG_PEAK_TH_125_MG = (0x03 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
871 APEX_CONFIG10_LOWG_PEAK_TH_156_MG = (0x04 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
872 APEX_CONFIG10_LOWG_PEAK_TH_188_MG = (0x05 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
873 APEX_CONFIG10_LOWG_PEAK_TH_219_MG = (0x06 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
874 APEX_CONFIG10_LOWG_PEAK_TH_250_MG = (0x07 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
875 APEX_CONFIG10_LOWG_PEAK_TH_281_MG = (0x08 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
876 APEX_CONFIG10_LOWG_PEAK_TH_313_MG = (0x09 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
877 APEX_CONFIG10_LOWG_PEAK_TH_344_MG = (0x0A << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
878 APEX_CONFIG10_LOWG_PEAK_TH_375_MG = (0x0B << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
879 APEX_CONFIG10_LOWG_PEAK_TH_406_MG = (0x0C << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
880 APEX_CONFIG10_LOWG_PEAK_TH_438_MG = (0x0D << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
881 APEX_CONFIG10_LOWG_PEAK_TH_469_MG = (0x0E << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
882 APEX_CONFIG10_LOWG_PEAK_TH_500_MG = (0x0F << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
883 APEX_CONFIG10_LOWG_PEAK_TH_531_MG = (0x10 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
884 APEX_CONFIG10_LOWG_PEAK_TH_563_MG = (0x11 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
885 APEX_CONFIG10_LOWG_PEAK_TH_594_MG = (0x12 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
886 APEX_CONFIG10_LOWG_PEAK_TH_625_MG = (0x13 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
887 APEX_CONFIG10_LOWG_PEAK_TH_656_MG = (0x14 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
888 APEX_CONFIG10_LOWG_PEAK_TH_688_MG = (0x15 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
889 APEX_CONFIG10_LOWG_PEAK_TH_719_MG = (0x16 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
890 APEX_CONFIG10_LOWG_PEAK_TH_750_MG = (0x17 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
891 APEX_CONFIG10_LOWG_PEAK_TH_781_MG = (0x18 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
892 APEX_CONFIG10_LOWG_PEAK_TH_813_MG = (0x19 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
893 APEX_CONFIG10_LOWG_PEAK_TH_844_MG = (0x1A << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
894 APEX_CONFIG10_LOWG_PEAK_TH_875_MG = (0x1B << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
895 APEX_CONFIG10_LOWG_PEAK_TH_906_MG = (0x1C << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
896 APEX_CONFIG10_LOWG_PEAK_TH_938_MG = (0x1D << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
897 APEX_CONFIG10_LOWG_PEAK_TH_969_MG = (0x1E << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
898 APEX_CONFIG10_LOWG_PEAK_TH_1000_MG = (0x1F << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS),
899 } APEX_CONFIG10_LOWG_PEAK_TH_t;
900
901 /* LOWG_TIME_TH_SEL */
902 typedef enum {
903 APEX_CONFIG10_LOWG_TIME_TH_1_SAMPLE = (0x00 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS),
904 APEX_CONFIG10_LOWG_TIME_TH_2_SAMPLES = (0x01 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS),
905 APEX_CONFIG10_LOWG_TIME_TH_3_SAMPLES = (0x02 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS),
906 APEX_CONFIG10_LOWG_TIME_TH_4_SAMPLES = (0x03 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS),
907 APEX_CONFIG10_LOWG_TIME_TH_5_SAMPLES = (0x04 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS),
908 APEX_CONFIG10_LOWG_TIME_TH_6_SAMPLES = (0x05 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS),
909 APEX_CONFIG10_LOWG_TIME_TH_7_SAMPLES = (0x06 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS),
910 APEX_CONFIG10_LOWG_TIME_TH_8_SAMPLES = (0x07 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS),
911 } APEX_CONFIG10_LOWG_TIME_TH_SAMPLES_t;
912
913 /*
914 * APEX_CONFIG11_MREG1
915 * Register Name: APEX_CONFIG11
916 */
917
918 /* HIGHG_PEAK_TH_SEL */
919 typedef enum {
920 APEX_CONFIG11_HIGHG_PEAK_TH_250_MG = (0x00 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
921 APEX_CONFIG11_HIGHG_PEAK_TH_500_MG = (0x01 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
922 APEX_CONFIG11_HIGHG_PEAK_TH_750_MG = (0x02 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
923 APEX_CONFIG11_HIGHG_PEAK_TH_1000MG = (0x03 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
924 APEX_CONFIG11_HIGHG_PEAK_TH_1250_MG = (0x04 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
925 APEX_CONFIG11_HIGHG_PEAK_TH_1500_MG = (0x05 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
926 APEX_CONFIG11_HIGHG_PEAK_TH_1750_MG = (0x06 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
927 APEX_CONFIG11_HIGHG_PEAK_TH_2000_MG = (0x07 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
928 APEX_CONFIG11_HIGHG_PEAK_TH_2250_MG = (0x08 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
929 APEX_CONFIG11_HIGHG_PEAK_TH_2500_MG = (0x09 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
930 APEX_CONFIG11_HIGHG_PEAK_TH_2750_MG = (0x0A << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
931 APEX_CONFIG11_HIGHG_PEAK_TH_3000_MG = (0x0B << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
932 APEX_CONFIG11_HIGHG_PEAK_TH_3250_MG = (0x0C << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
933 APEX_CONFIG11_HIGHG_PEAK_TH_3500_MG = (0x0D << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
934 APEX_CONFIG11_HIGHG_PEAK_TH_3750_MG = (0x0E << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
935 APEX_CONFIG11_HIGHG_PEAK_TH_4000_MG = (0x0F << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
936 APEX_CONFIG11_HIGHG_PEAK_TH_4250_MG = (0x10 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
937 APEX_CONFIG11_HIGHG_PEAK_TH_4500_MG = (0x11 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
938 APEX_CONFIG11_HIGHG_PEAK_TH_4750_MG = (0x12 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
939 APEX_CONFIG11_HIGHG_PEAK_TH_5000_MG = (0x13 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
940 APEX_CONFIG11_HIGHG_PEAK_TH_5250_MG = (0x14 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
941 APEX_CONFIG11_HIGHG_PEAK_TH_5500_MG = (0x15 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
942 APEX_CONFIG11_HIGHG_PEAK_TH_5750_MG = (0x16 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
943 APEX_CONFIG11_HIGHG_PEAK_TH_6000_MG = (0x17 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
944 APEX_CONFIG11_HIGHG_PEAK_TH_6250_MG = (0x18 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
945 APEX_CONFIG11_HIGHG_PEAK_TH_6500_MG = (0x19 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
946 APEX_CONFIG11_HIGHG_PEAK_TH_6750_MG = (0x1A << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
947 APEX_CONFIG11_HIGHG_PEAK_TH_7000_MG = (0x1B << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
948 APEX_CONFIG11_HIGHG_PEAK_TH_7250_MG = (0x1C << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
949 APEX_CONFIG11_HIGHG_PEAK_TH_7500_MG = (0x1D << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
950 APEX_CONFIG11_HIGHG_PEAK_TH_7750_MG = (0x1E << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS),
951 } APEX_CONFIG11_HIGHG_PEAK_TH_t;
952
953 /* HIGHG_TIME_TH_SEL */
954 typedef enum {
955 APEX_CONFIG11_HIGHG_TIME_TH_1_SAMPLE = (0x00 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS),
956 APEX_CONFIG11_HIGHG_TIME_TH_2_SAMPLES = (0x01 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS),
957 APEX_CONFIG11_HIGHG_TIME_TH_3_SAMPLES = (0x02 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS),
958 APEX_CONFIG11_HIGHG_TIME_TH_4_SAMPLES = (0x03 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS),
959 APEX_CONFIG11_HIGHG_TIME_TH_5_SAMPLES = (0x04 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS),
960 APEX_CONFIG11_HIGHG_TIME_TH_6_SAMPLES = (0x05 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS),
961 APEX_CONFIG11_HIGHG_TIME_TH_7_SAMPLES = (0x06 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS),
962 APEX_CONFIG11_HIGHG_TIME_TH_8_SAMPLES = (0x07 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS),
963 } APEX_CONFIG11_HIGHG_TIME_TH_SAMPLES_t;
964
965 /*
966 * FDR_CONFIG_MREG1
967 * Register Name: FDR_CONFIG
968 */
969
970 /* FDR_SEL */
971 typedef enum {
972 FDR_CONFIG_FDR_SEL_DIS = (0x0 << FDR_CONFIG_FDR_SEL_POS),
973 FDR_CONFIG_FDR_SEL_FACTOR_2 = (0x8 << FDR_CONFIG_FDR_SEL_POS),
974 FDR_CONFIG_FDR_SEL_FACTOR_4 = (0x9 << FDR_CONFIG_FDR_SEL_POS),
975 FDR_CONFIG_FDR_SEL_FACTOR_8 = (0xA << FDR_CONFIG_FDR_SEL_POS),
976 FDR_CONFIG_FDR_SEL_FACTOR_16 = (0xB << FDR_CONFIG_FDR_SEL_POS),
977 FDR_CONFIG_FDR_SEL_FACTOR_32 = (0xC << FDR_CONFIG_FDR_SEL_POS),
978 FDR_CONFIG_FDR_SEL_FACTOR_64 = (0xD << FDR_CONFIG_FDR_SEL_POS),
979 FDR_CONFIG_FDR_SEL_FACTOR_128 = (0xE << FDR_CONFIG_FDR_SEL_POS),
980 FDR_CONFIG_FDR_SEL_FACTOR_256 = (0xF << FDR_CONFIG_FDR_SEL_POS),
981 } FDR_CONFIG_FDR_SEL_t;
982
983 /*
984 * APEX_CONFIG12_MREG1
985 * Register Name: APEX_CONFIG12
986 */
987 /* FF_MAX_DURATION_SEL */
988 typedef enum {
989 APEX_CONFIG12_FF_MAX_DURATION_102_CM = (0 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
990 APEX_CONFIG12_FF_MAX_DURATION_120_CM = (1 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
991 APEX_CONFIG12_FF_MAX_DURATION_139_CM = (2 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
992 APEX_CONFIG12_FF_MAX_DURATION_159_CM = (3 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
993 APEX_CONFIG12_FF_MAX_DURATION_181_CM = (4 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
994 APEX_CONFIG12_FF_MAX_DURATION_204_CM = (5 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
995 APEX_CONFIG12_FF_MAX_DURATION_228_CM = (6 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
996 APEX_CONFIG12_FF_MAX_DURATION_254_CM = (7 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
997 APEX_CONFIG12_FF_MAX_DURATION_281_CM = (8 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
998 APEX_CONFIG12_FF_MAX_DURATION_310_CM = (9 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
999 APEX_CONFIG12_FF_MAX_DURATION_339_CM = (10 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
1000 APEX_CONFIG12_FF_MAX_DURATION_371_CM = (11 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
1001 APEX_CONFIG12_FF_MAX_DURATION_403_CM = (12 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
1002 APEX_CONFIG12_FF_MAX_DURATION_438_CM = (13 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
1003 APEX_CONFIG12_FF_MAX_DURATION_473_CM = (14 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
1004 APEX_CONFIG12_FF_MAX_DURATION_510_CM = (15 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS),
1005 } APEX_CONFIG12_FF_MAX_DURATION_t;
1006
1007 /* FF_MIN_DURATION_SEL */
1008 typedef enum {
1009 APEX_CONFIG12_FF_MIN_DURATION_10_CM = (0 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1010 APEX_CONFIG12_FF_MIN_DURATION_12_CM = (1 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1011 APEX_CONFIG12_FF_MIN_DURATION_13_CM = (2 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1012 APEX_CONFIG12_FF_MIN_DURATION_16_CM = (3 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1013 APEX_CONFIG12_FF_MIN_DURATION_18_CM = (4 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1014 APEX_CONFIG12_FF_MIN_DURATION_20_CM = (5 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1015 APEX_CONFIG12_FF_MIN_DURATION_23_CM = (6 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1016 APEX_CONFIG12_FF_MIN_DURATION_25_CM = (7 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1017 APEX_CONFIG12_FF_MIN_DURATION_28_CM = (8 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1018 APEX_CONFIG12_FF_MIN_DURATION_31_CM = (9 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1019 APEX_CONFIG12_FF_MIN_DURATION_34_CM = (10 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1020 APEX_CONFIG12_FF_MIN_DURATION_38_CM = (11 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1021 APEX_CONFIG12_FF_MIN_DURATION_41_CM = (12 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1022 APEX_CONFIG12_FF_MIN_DURATION_45_CM = (13 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1023 APEX_CONFIG12_FF_MIN_DURATION_48_CM = (14 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1024 APEX_CONFIG12_FF_MIN_DURATION_52_CM = (15 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS),
1025 } APEX_CONFIG12_FF_MIN_DURATION_t;
1026
1027 /* ---------------------------------------------------------------------------
1028 * register bank MREG2
1029 * ---------------------------------------------------------------------------- */
1030
1031 /*
1032 * OTP_CTRL7_MREG2
1033 * Register Name: OTP_CTRL7
1034 */
1035
1036 /* OTP_CTRL7 */
1037 typedef enum {
1038 OTP_CTRL7_OTP_RELOAD_EN = (1 << OTP_CTRL7_OTP_RELOAD_POS),
1039 OTP_CTRL7_OTP_RELOAD_DIS = (0 << OTP_CTRL7_OTP_RELOAD_POS),
1040 } OTP_CTRL7_OTP_RELOAD_t;
1041
1042 /* OTP_PWR_DOWN */
1043 typedef enum {
1044 OTP_CTRL7_PWR_DOWN_EN = (1 << OTP_CTRL7_OTP_PWR_DOWN_POS),
1045 OTP_CTRL7_PWR_DOWN_DIS = (0 << OTP_CTRL7_OTP_PWR_DOWN_POS),
1046 } OTP_CTRL7_PWR_DOWN_t;
1047
1048 #ifdef __cplusplus
1049 }
1050 #endif
1051
1052 #endif /* #ifndef _INV_IMU_DEFS_H_ */
SELFTEST_ACCEL_GYRO_ST_EN_t
SELFTEST_ACCEL_GYRO_ST_EN_t
Definition: inv_imu_defs.h:668
SELFTEST_DIS
@ SELFTEST_DIS
Definition: inv_imu_defs.h:669
SELFTEST_ACCEL_EN
@ SELFTEST_ACCEL_EN
Definition: inv_imu_defs.h:670
PWR_MGMT0_IDLE_t
PWR_MGMT0_IDLE_t
Definition: inv_imu_defs.h:274
PWR_MGMT0_IDLE_EN
@ PWR_MGMT0_IDLE_EN
Definition: inv_imu_defs.h:276
PWR_MGMT0_IDLE_DIS
@ PWR_MGMT0_IDLE_DIS
Definition: inv_imu_defs.h:275
APEX_CONFIG0_DMP_POWER_SAVE_t
APEX_CONFIG0_DMP_POWER_SAVE_t
Definition: inv_imu_defs.h:406
APEX_CONFIG0_DMP_POWER_SAVE_EN
@ APEX_CONFIG0_DMP_POWER_SAVE_EN
Definition: inv_imu_defs.h:407
APEX_CONFIG0_DMP_POWER_SAVE_DIS
@ APEX_CONFIG0_DMP_POWER_SAVE_DIS
Definition: inv_imu_defs.h:408
APEX_CONFIG3_PEDO_AMP_TH_t
APEX_CONFIG3_PEDO_AMP_TH_t
Definition: inv_imu_defs.h:739
APEX_CONFIG3_PEDO_AMP_TH_82_MG
@ APEX_CONFIG3_PEDO_AMP_TH_82_MG
Definition: inv_imu_defs.h:753
APEX_CONFIG3_PEDO_AMP_TH_54_MG
@ APEX_CONFIG3_PEDO_AMP_TH_54_MG
Definition: inv_imu_defs.h:746
APEX_CONFIG3_PEDO_AMP_TH_46_MG
@ APEX_CONFIG3_PEDO_AMP_TH_46_MG
Definition: inv_imu_defs.h:744
APEX_CONFIG3_PEDO_AMP_TH_30_MG
@ APEX_CONFIG3_PEDO_AMP_TH_30_MG
Definition: inv_imu_defs.h:740
APEX_CONFIG3_PEDO_AMP_TH_86_MG
@ APEX_CONFIG3_PEDO_AMP_TH_86_MG
Definition: inv_imu_defs.h:754
APEX_CONFIG3_PEDO_AMP_TH_74_MG
@ APEX_CONFIG3_PEDO_AMP_TH_74_MG
Definition: inv_imu_defs.h:751
APEX_CONFIG3_PEDO_AMP_TH_78_MG
@ APEX_CONFIG3_PEDO_AMP_TH_78_MG
Definition: inv_imu_defs.h:752
APEX_CONFIG3_PEDO_AMP_TH_90_MG
@ APEX_CONFIG3_PEDO_AMP_TH_90_MG
Definition: inv_imu_defs.h:755
APEX_CONFIG3_PEDO_AMP_TH_62_MG
@ APEX_CONFIG3_PEDO_AMP_TH_62_MG
Definition: inv_imu_defs.h:748
APEX_CONFIG3_PEDO_AMP_TH_50_MG
@ APEX_CONFIG3_PEDO_AMP_TH_50_MG
Definition: inv_imu_defs.h:745
APEX_CONFIG3_PEDO_AMP_TH_34_MG
@ APEX_CONFIG3_PEDO_AMP_TH_34_MG
Definition: inv_imu_defs.h:741
APEX_CONFIG3_PEDO_AMP_TH_38_MG
@ APEX_CONFIG3_PEDO_AMP_TH_38_MG
Definition: inv_imu_defs.h:742
APEX_CONFIG3_PEDO_AMP_TH_58_MG
@ APEX_CONFIG3_PEDO_AMP_TH_58_MG
Definition: inv_imu_defs.h:747
APEX_CONFIG3_PEDO_AMP_TH_70_MG
@ APEX_CONFIG3_PEDO_AMP_TH_70_MG
Definition: inv_imu_defs.h:750
APEX_CONFIG3_PEDO_AMP_TH_42_MG
@ APEX_CONFIG3_PEDO_AMP_TH_42_MG
Definition: inv_imu_defs.h:743
APEX_CONFIG3_PEDO_AMP_TH_66_MG
@ APEX_CONFIG3_PEDO_AMP_TH_66_MG
Definition: inv_imu_defs.h:749
WOM_CONFIG_WOM_INT_MODE_t
WOM_CONFIG_WOM_INT_MODE_t
Definition: inv_imu_defs.h:474
WOM_CONFIG_WOM_INT_MODE_ORED
@ WOM_CONFIG_WOM_INT_MODE_ORED
Definition: inv_imu_defs.h:476
WOM_CONFIG_WOM_INT_MODE_ANDED
@ WOM_CONFIG_WOM_INT_MODE_ANDED
Definition: inv_imu_defs.h:475
APEX_CONFIG1_TILT_ENABLE_t
APEX_CONFIG1_TILT_ENABLE_t
Definition: inv_imu_defs.h:441
APEX_CONFIG1_TILT_ENABLE_DIS
@ APEX_CONFIG1_TILT_ENABLE_DIS
Definition: inv_imu_defs.h:442
APEX_CONFIG1_TILT_ENABLE_EN
@ APEX_CONFIG1_TILT_ENABLE_EN
Definition: inv_imu_defs.h:443
INTF_CONFIG0_FIFO_COUNT_REC_t
INTF_CONFIG0_FIFO_COUNT_REC_t
Definition: inv_imu_defs.h:544
INTF_CONFIG0_FIFO_COUNT_REC_RECORD
@ INTF_CONFIG0_FIFO_COUNT_REC_RECORD
Definition: inv_imu_defs.h:545
INTF_CONFIG0_FIFO_COUNT_REC_BYTE
@ INTF_CONFIG0_FIFO_COUNT_REC_BYTE
Definition: inv_imu_defs.h:546
PWR_MGMT0_ACCEL_LP_CLK_t
PWR_MGMT0_ACCEL_LP_CLK_t
Definition: inv_imu_defs.h:268
PWR_MGMT0_ACCEL_LP_CLK_WUOSC
@ PWR_MGMT0_ACCEL_LP_CLK_WUOSC
Definition: inv_imu_defs.h:269
PWR_MGMT0_ACCEL_LP_CLK_RCOSC
@ PWR_MGMT0_ACCEL_LP_CLK_RCOSC
Definition: inv_imu_defs.h:270
APEX_CONFIG11_HIGHG_PEAK_TH_t
APEX_CONFIG11_HIGHG_PEAK_TH_t
Definition: inv_imu_defs.h:919
APEX_CONFIG11_HIGHG_PEAK_TH_250_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_250_MG
Definition: inv_imu_defs.h:920
APEX_CONFIG11_HIGHG_PEAK_TH_6750_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_6750_MG
Definition: inv_imu_defs.h:946
APEX_CONFIG11_HIGHG_PEAK_TH_500_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_500_MG
Definition: inv_imu_defs.h:921
APEX_CONFIG11_HIGHG_PEAK_TH_2000_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_2000_MG
Definition: inv_imu_defs.h:927
APEX_CONFIG11_HIGHG_PEAK_TH_4000_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_4000_MG
Definition: inv_imu_defs.h:935
APEX_CONFIG11_HIGHG_PEAK_TH_6000_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_6000_MG
Definition: inv_imu_defs.h:943
APEX_CONFIG11_HIGHG_PEAK_TH_3500_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_3500_MG
Definition: inv_imu_defs.h:933
APEX_CONFIG11_HIGHG_PEAK_TH_5000_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_5000_MG
Definition: inv_imu_defs.h:939
APEX_CONFIG11_HIGHG_PEAK_TH_6500_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_6500_MG
Definition: inv_imu_defs.h:945
APEX_CONFIG11_HIGHG_PEAK_TH_2750_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_2750_MG
Definition: inv_imu_defs.h:930
APEX_CONFIG11_HIGHG_PEAK_TH_2500_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_2500_MG
Definition: inv_imu_defs.h:929
APEX_CONFIG11_HIGHG_PEAK_TH_3000_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_3000_MG
Definition: inv_imu_defs.h:931
APEX_CONFIG11_HIGHG_PEAK_TH_5750_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_5750_MG
Definition: inv_imu_defs.h:942
APEX_CONFIG11_HIGHG_PEAK_TH_7250_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_7250_MG
Definition: inv_imu_defs.h:948
APEX_CONFIG11_HIGHG_PEAK_TH_7000_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_7000_MG
Definition: inv_imu_defs.h:947
APEX_CONFIG11_HIGHG_PEAK_TH_3750_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_3750_MG
Definition: inv_imu_defs.h:934
APEX_CONFIG11_HIGHG_PEAK_TH_5250_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_5250_MG
Definition: inv_imu_defs.h:940
APEX_CONFIG11_HIGHG_PEAK_TH_7750_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_7750_MG
Definition: inv_imu_defs.h:950
APEX_CONFIG11_HIGHG_PEAK_TH_7500_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_7500_MG
Definition: inv_imu_defs.h:949
APEX_CONFIG11_HIGHG_PEAK_TH_1250_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_1250_MG
Definition: inv_imu_defs.h:924
APEX_CONFIG11_HIGHG_PEAK_TH_5500_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_5500_MG
Definition: inv_imu_defs.h:941
APEX_CONFIG11_HIGHG_PEAK_TH_750_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_750_MG
Definition: inv_imu_defs.h:922
APEX_CONFIG11_HIGHG_PEAK_TH_1750_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_1750_MG
Definition: inv_imu_defs.h:926
APEX_CONFIG11_HIGHG_PEAK_TH_1500_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_1500_MG
Definition: inv_imu_defs.h:925
APEX_CONFIG11_HIGHG_PEAK_TH_3250_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_3250_MG
Definition: inv_imu_defs.h:932
APEX_CONFIG11_HIGHG_PEAK_TH_4500_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_4500_MG
Definition: inv_imu_defs.h:937
APEX_CONFIG11_HIGHG_PEAK_TH_4250_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_4250_MG
Definition: inv_imu_defs.h:936
APEX_CONFIG11_HIGHG_PEAK_TH_1000MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_1000MG
Definition: inv_imu_defs.h:923
APEX_CONFIG11_HIGHG_PEAK_TH_6250_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_6250_MG
Definition: inv_imu_defs.h:944
APEX_CONFIG11_HIGHG_PEAK_TH_4750_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_4750_MG
Definition: inv_imu_defs.h:938
APEX_CONFIG11_HIGHG_PEAK_TH_2250_MG
@ APEX_CONFIG11_HIGHG_PEAK_TH_2250_MG
Definition: inv_imu_defs.h:928
WOM_CONFIG_WOM_INT_DUR_t
WOM_CONFIG_WOM_INT_DUR_t
Definition: inv_imu_defs.h:466
WOM_CONFIG_WOM_INT_DUR_2_SMPL
@ WOM_CONFIG_WOM_INT_DUR_2_SMPL
Definition: inv_imu_defs.h:468
WOM_CONFIG_WOM_INT_DUR_1_SMPL
@ WOM_CONFIG_WOM_INT_DUR_1_SMPL
Definition: inv_imu_defs.h:467
WOM_CONFIG_WOM_INT_DUR_3_SMPL
@ WOM_CONFIG_WOM_INT_DUR_3_SMPL
Definition: inv_imu_defs.h:469
WOM_CONFIG_WOM_INT_DUR_4_SMPL
@ WOM_CONFIG_WOM_INT_DUR_4_SMPL
Definition: inv_imu_defs.h:470
APEX_CONFIG4_PEDO_SB_TIMER_TH_t
APEX_CONFIG4_PEDO_SB_TIMER_TH_t
Definition: inv_imu_defs.h:764
APEX_CONFIG4_PEDO_SB_TIMER_TH_225_SAMPLES
@ APEX_CONFIG4_PEDO_SB_TIMER_TH_225_SAMPLES
Definition: inv_imu_defs.h:772
APEX_CONFIG4_PEDO_SB_TIMER_TH_50_SAMPLES
@ APEX_CONFIG4_PEDO_SB_TIMER_TH_50_SAMPLES
Definition: inv_imu_defs.h:765
APEX_CONFIG4_PEDO_SB_TIMER_TH_150_SAMPLES
@ APEX_CONFIG4_PEDO_SB_TIMER_TH_150_SAMPLES
Definition: inv_imu_defs.h:769
APEX_CONFIG4_PEDO_SB_TIMER_TH_200_SAMPLES
@ APEX_CONFIG4_PEDO_SB_TIMER_TH_200_SAMPLES
Definition: inv_imu_defs.h:771
APEX_CONFIG4_PEDO_SB_TIMER_TH_175_SAMPLES
@ APEX_CONFIG4_PEDO_SB_TIMER_TH_175_SAMPLES
Definition: inv_imu_defs.h:770
APEX_CONFIG4_PEDO_SB_TIMER_TH_75_SAMPLES
@ APEX_CONFIG4_PEDO_SB_TIMER_TH_75_SAMPLES
Definition: inv_imu_defs.h:766
APEX_CONFIG4_PEDO_SB_TIMER_TH_125_SAMPLES
@ APEX_CONFIG4_PEDO_SB_TIMER_TH_125_SAMPLES
Definition: inv_imu_defs.h:768
APEX_CONFIG4_PEDO_SB_TIMER_TH_100_SAMPLES
@ APEX_CONFIG4_PEDO_SB_TIMER_TH_100_SAMPLES
Definition: inv_imu_defs.h:767
DEVICE_CONFIG_SPI_AP_4WIRE_t
DEVICE_CONFIG_SPI_AP_4WIRE_t
Definition: inv_imu_defs.h:197
DEVICE_CONFIG_SPI_3WIRE
@ DEVICE_CONFIG_SPI_3WIRE
Definition: inv_imu_defs.h:199
DEVICE_CONFIG_SPI_4WIRE
@ DEVICE_CONFIG_SPI_4WIRE
Definition: inv_imu_defs.h:198
INT_CONFIG_INT1_DRIVE_CIRCUIT_t
INT_CONFIG_INT1_DRIVE_CIRCUIT_t
Definition: inv_imu_defs.h:251
INT_CONFIG_INT1_DRIVE_CIRCUIT_OD
@ INT_CONFIG_INT1_DRIVE_CIRCUIT_OD
Definition: inv_imu_defs.h:253
INT_CONFIG_INT1_DRIVE_CIRCUIT_PP
@ INT_CONFIG_INT1_DRIVE_CIRCUIT_PP
Definition: inv_imu_defs.h:252
ACCEL_CONFIG1_ACCEL_FILT_BW_t
ACCEL_CONFIG1_ACCEL_FILT_BW_t
Definition: inv_imu_defs.h:389
ACCEL_CONFIG1_ACCEL_FILT_BW_25
@ ACCEL_CONFIG1_ACCEL_FILT_BW_25
Definition: inv_imu_defs.h:391
ACCEL_CONFIG1_ACCEL_FILT_BW_NO_FILTER
@ ACCEL_CONFIG1_ACCEL_FILT_BW_NO_FILTER
Definition: inv_imu_defs.h:397
ACCEL_CONFIG1_ACCEL_FILT_BW_121
@ ACCEL_CONFIG1_ACCEL_FILT_BW_121
Definition: inv_imu_defs.h:395
ACCEL_CONFIG1_ACCEL_FILT_BW_180
@ ACCEL_CONFIG1_ACCEL_FILT_BW_180
Definition: inv_imu_defs.h:396
ACCEL_CONFIG1_ACCEL_FILT_BW_73
@ ACCEL_CONFIG1_ACCEL_FILT_BW_73
Definition: inv_imu_defs.h:394
ACCEL_CONFIG1_ACCEL_FILT_BW_34
@ ACCEL_CONFIG1_ACCEL_FILT_BW_34
Definition: inv_imu_defs.h:392
ACCEL_CONFIG1_ACCEL_FILT_BW_16
@ ACCEL_CONFIG1_ACCEL_FILT_BW_16
Definition: inv_imu_defs.h:390
ACCEL_CONFIG1_ACCEL_FILT_BW_53
@ ACCEL_CONFIG1_ACCEL_FILT_BW_53
Definition: inv_imu_defs.h:393
APEX_CONFIG5_TILT_WAIT_TIME_t
APEX_CONFIG5_TILT_WAIT_TIME_t
Definition: inv_imu_defs.h:789
APEX_CONFIG5_TILT_WAIT_TIME_2_S
@ APEX_CONFIG5_TILT_WAIT_TIME_2_S
Definition: inv_imu_defs.h:791
APEX_CONFIG5_TILT_WAIT_TIME_4_S
@ APEX_CONFIG5_TILT_WAIT_TIME_4_S
Definition: inv_imu_defs.h:792
APEX_CONFIG5_TILT_WAIT_TIME_0_S
@ APEX_CONFIG5_TILT_WAIT_TIME_0_S
Definition: inv_imu_defs.h:790
APEX_CONFIG5_TILT_WAIT_TIME_6_S
@ APEX_CONFIG5_TILT_WAIT_TIME_6_S
Definition: inv_imu_defs.h:793
FIFO_CONFIG5_TMST_FSYNC_t
FIFO_CONFIG5_TMST_FSYNC_t
Definition: inv_imu_defs.h:605
FIFO_CONFIG5_TMST_FSYNC_EN
@ FIFO_CONFIG5_TMST_FSYNC_EN
Definition: inv_imu_defs.h:606
FIFO_CONFIG5_TMST_FSYNC_DIS
@ FIFO_CONFIG5_TMST_FSYNC_DIS
Definition: inv_imu_defs.h:607
APEX_CONFIG10_LOWG_TIME_TH_SAMPLES_t
APEX_CONFIG10_LOWG_TIME_TH_SAMPLES_t
Definition: inv_imu_defs.h:902
APEX_CONFIG10_LOWG_TIME_TH_1_SAMPLE
@ APEX_CONFIG10_LOWG_TIME_TH_1_SAMPLE
Definition: inv_imu_defs.h:903
APEX_CONFIG10_LOWG_TIME_TH_3_SAMPLES
@ APEX_CONFIG10_LOWG_TIME_TH_3_SAMPLES
Definition: inv_imu_defs.h:905
APEX_CONFIG10_LOWG_TIME_TH_8_SAMPLES
@ APEX_CONFIG10_LOWG_TIME_TH_8_SAMPLES
Definition: inv_imu_defs.h:910
APEX_CONFIG10_LOWG_TIME_TH_7_SAMPLES
@ APEX_CONFIG10_LOWG_TIME_TH_7_SAMPLES
Definition: inv_imu_defs.h:909
APEX_CONFIG10_LOWG_TIME_TH_6_SAMPLES
@ APEX_CONFIG10_LOWG_TIME_TH_6_SAMPLES
Definition: inv_imu_defs.h:908
APEX_CONFIG10_LOWG_TIME_TH_4_SAMPLES
@ APEX_CONFIG10_LOWG_TIME_TH_4_SAMPLES
Definition: inv_imu_defs.h:906
APEX_CONFIG10_LOWG_TIME_TH_5_SAMPLES
@ APEX_CONFIG10_LOWG_TIME_TH_5_SAMPLES
Definition: inv_imu_defs.h:907
APEX_CONFIG10_LOWG_TIME_TH_2_SAMPLES
@ APEX_CONFIG10_LOWG_TIME_TH_2_SAMPLES
Definition: inv_imu_defs.h:904
APEX_CONFIG1_FF_ENABLE_t
APEX_CONFIG1_FF_ENABLE_t
Definition: inv_imu_defs.h:435
APEX_CONFIG1_FF_ENABLE_EN
@ APEX_CONFIG1_FF_ENABLE_EN
Definition: inv_imu_defs.h:437
APEX_CONFIG1_FF_ENABLE_DIS
@ APEX_CONFIG1_FF_ENABLE_DIS
Definition: inv_imu_defs.h:436
FIFO_CONFIG1_FIFO_MODE_t
FIFO_CONFIG1_FIFO_MODE_t
Definition: inv_imu_defs.h:497
FIFO_CONFIG1_FIFO_MODE_SNAPSHOT
@ FIFO_CONFIG1_FIFO_MODE_SNAPSHOT
Definition: inv_imu_defs.h:498
FIFO_CONFIG1_FIFO_MODE_STREAM
@ FIFO_CONFIG1_FIFO_MODE_STREAM
Definition: inv_imu_defs.h:499
TMST_CONFIG1_TMST_FSYNC_EN_t
TMST_CONFIG1_TMST_FSYNC_EN_t
Definition: inv_imu_defs.h:577
TMST_CONFIG1_TMST_FSYNC_EN
@ TMST_CONFIG1_TMST_FSYNC_EN
Definition: inv_imu_defs.h:578
TMST_CONFIG1_TMST_FSYNC_DIS
@ TMST_CONFIG1_TMST_FSYNC_DIS
Definition: inv_imu_defs.h:579
ACCEL_CONFIG0_FS_SEL_t
ACCEL_CONFIG0_FS_SEL_t
Definition: inv_imu_defs.h:332
ACCEL_CONFIG0_FS_SEL_4g
@ ACCEL_CONFIG0_FS_SEL_4g
Definition: inv_imu_defs.h:334
ACCEL_CONFIG0_FS_SEL_16g
@ ACCEL_CONFIG0_FS_SEL_16g
Definition: inv_imu_defs.h:336
ACCEL_CONFIG0_FS_SEL_2g
@ ACCEL_CONFIG0_FS_SEL_2g
Definition: inv_imu_defs.h:333
ACCEL_CONFIG0_FS_SEL_8g
@ ACCEL_CONFIG0_FS_SEL_8g
Definition: inv_imu_defs.h:335
APEX_CONFIG0_DMP_MEM_RESET_t
APEX_CONFIG0_DMP_MEM_RESET_t
Definition: inv_imu_defs.h:418
APEX_CONFIG0_DMP_MEM_RESET_APEX_ST_EN
@ APEX_CONFIG0_DMP_MEM_RESET_APEX_ST_EN
Definition: inv_imu_defs.h:419
APEX_CONFIG0_DMP_MEM_RESET_DIS
@ APEX_CONFIG0_DMP_MEM_RESET_DIS
Definition: inv_imu_defs.h:420
APEX_CONFIG5_LOWG_PEAK_TH_HYST_t
APEX_CONFIG5_LOWG_PEAK_TH_HYST_t
Definition: inv_imu_defs.h:797
APEX_CONFIG5_LOWG_PEAK_TH_HYST_250_MG
@ APEX_CONFIG5_LOWG_PEAK_TH_HYST_250_MG
Definition: inv_imu_defs.h:805
APEX_CONFIG5_LOWG_PEAK_TH_HYST_219_MG
@ APEX_CONFIG5_LOWG_PEAK_TH_HYST_219_MG
Definition: inv_imu_defs.h:804
APEX_CONFIG5_LOWG_PEAK_TH_HYST_156_MG
@ APEX_CONFIG5_LOWG_PEAK_TH_HYST_156_MG
Definition: inv_imu_defs.h:802
APEX_CONFIG5_LOWG_PEAK_TH_HYST_125_MG
@ APEX_CONFIG5_LOWG_PEAK_TH_HYST_125_MG
Definition: inv_imu_defs.h:801
APEX_CONFIG5_LOWG_PEAK_TH_HYST_94_MG
@ APEX_CONFIG5_LOWG_PEAK_TH_HYST_94_MG
Definition: inv_imu_defs.h:800
APEX_CONFIG5_LOWG_PEAK_TH_HYST_31_MG
@ APEX_CONFIG5_LOWG_PEAK_TH_HYST_31_MG
Definition: inv_imu_defs.h:798
APEX_CONFIG5_LOWG_PEAK_TH_HYST_63_MG
@ APEX_CONFIG5_LOWG_PEAK_TH_HYST_63_MG
Definition: inv_imu_defs.h:799
APEX_CONFIG5_LOWG_PEAK_TH_HYST_188_MG
@ APEX_CONFIG5_LOWG_PEAK_TH_HYST_188_MG
Definition: inv_imu_defs.h:803
APEX_CONFIG1_SMD_ENABLE_t
APEX_CONFIG1_SMD_ENABLE_t
Definition: inv_imu_defs.h:429
APEX_CONFIG1_SMD_ENABLE_EN
@ APEX_CONFIG1_SMD_ENABLE_EN
Definition: inv_imu_defs.h:431
APEX_CONFIG1_SMD_ENABLE_DIS
@ APEX_CONFIG1_SMD_ENABLE_DIS
Definition: inv_imu_defs.h:430
SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_t
SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_t
Definition: inv_imu_defs.h:208
SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_EN
@ SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_EN
Definition: inv_imu_defs.h:209
SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_DIS
@ SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_DIS
Definition: inv_imu_defs.h:211
APEX_CONFIG4_PEDO_HI_ENRGY_TH_t
APEX_CONFIG4_PEDO_HI_ENRGY_TH_t
Definition: inv_imu_defs.h:776
APEX_CONFIG4_PEDO_HI_ENRGY_TH_104_MG
@ APEX_CONFIG4_PEDO_HI_ENRGY_TH_104_MG
Definition: inv_imu_defs.h:778
APEX_CONFIG4_PEDO_HI_ENRGY_TH_88_MG
@ APEX_CONFIG4_PEDO_HI_ENRGY_TH_88_MG
Definition: inv_imu_defs.h:777
APEX_CONFIG4_PEDO_HI_ENRGY_TH_133_MG
@ APEX_CONFIG4_PEDO_HI_ENRGY_TH_133_MG
Definition: inv_imu_defs.h:779
APEX_CONFIG4_PEDO_HI_ENRGY_TH_155_MG
@ APEX_CONFIG4_PEDO_HI_ENRGY_TH_155_MG
Definition: inv_imu_defs.h:780
APEX_CONFIG12_FF_MIN_DURATION_t
APEX_CONFIG12_FF_MIN_DURATION_t
Definition: inv_imu_defs.h:1008
APEX_CONFIG12_FF_MIN_DURATION_34_CM
@ APEX_CONFIG12_FF_MIN_DURATION_34_CM
Definition: inv_imu_defs.h:1019
APEX_CONFIG12_FF_MIN_DURATION_10_CM
@ APEX_CONFIG12_FF_MIN_DURATION_10_CM
Definition: inv_imu_defs.h:1009
APEX_CONFIG12_FF_MIN_DURATION_38_CM
@ APEX_CONFIG12_FF_MIN_DURATION_38_CM
Definition: inv_imu_defs.h:1020
APEX_CONFIG12_FF_MIN_DURATION_41_CM
@ APEX_CONFIG12_FF_MIN_DURATION_41_CM
Definition: inv_imu_defs.h:1021
APEX_CONFIG12_FF_MIN_DURATION_20_CM
@ APEX_CONFIG12_FF_MIN_DURATION_20_CM
Definition: inv_imu_defs.h:1014
APEX_CONFIG12_FF_MIN_DURATION_31_CM
@ APEX_CONFIG12_FF_MIN_DURATION_31_CM
Definition: inv_imu_defs.h:1018
APEX_CONFIG12_FF_MIN_DURATION_23_CM
@ APEX_CONFIG12_FF_MIN_DURATION_23_CM
Definition: inv_imu_defs.h:1015
APEX_CONFIG12_FF_MIN_DURATION_28_CM
@ APEX_CONFIG12_FF_MIN_DURATION_28_CM
Definition: inv_imu_defs.h:1017
APEX_CONFIG12_FF_MIN_DURATION_25_CM
@ APEX_CONFIG12_FF_MIN_DURATION_25_CM
Definition: inv_imu_defs.h:1016
APEX_CONFIG12_FF_MIN_DURATION_16_CM
@ APEX_CONFIG12_FF_MIN_DURATION_16_CM
Definition: inv_imu_defs.h:1012
APEX_CONFIG12_FF_MIN_DURATION_48_CM
@ APEX_CONFIG12_FF_MIN_DURATION_48_CM
Definition: inv_imu_defs.h:1023
APEX_CONFIG12_FF_MIN_DURATION_45_CM
@ APEX_CONFIG12_FF_MIN_DURATION_45_CM
Definition: inv_imu_defs.h:1022
APEX_CONFIG12_FF_MIN_DURATION_13_CM
@ APEX_CONFIG12_FF_MIN_DURATION_13_CM
Definition: inv_imu_defs.h:1011
APEX_CONFIG12_FF_MIN_DURATION_52_CM
@ APEX_CONFIG12_FF_MIN_DURATION_52_CM
Definition: inv_imu_defs.h:1024
APEX_CONFIG12_FF_MIN_DURATION_12_CM
@ APEX_CONFIG12_FF_MIN_DURATION_12_CM
Definition: inv_imu_defs.h:1010
APEX_CONFIG12_FF_MIN_DURATION_18_CM
@ APEX_CONFIG12_FF_MIN_DURATION_18_CM
Definition: inv_imu_defs.h:1013
TMST_CONFIG1_TMST_EN_t
TMST_CONFIG1_TMST_EN_t
Definition: inv_imu_defs.h:583
TMST_CONFIG1_TMST_EN
@ TMST_CONFIG1_TMST_EN
Definition: inv_imu_defs.h:584
TMST_CONFIG1_TMST_DIS
@ TMST_CONFIG1_TMST_DIS
Definition: inv_imu_defs.h:585
FIFO_CONFIG5_WM_GT_t
FIFO_CONFIG5_WM_GT_t
Definition: inv_imu_defs.h:593
FIFO_CONFIG5_WM_GT_TH_EN
@ FIFO_CONFIG5_WM_GT_TH_EN
Definition: inv_imu_defs.h:594
FIFO_CONFIG5_WM_GT_TH_DIS
@ FIFO_CONFIG5_WM_GT_TH_DIS
Definition: inv_imu_defs.h:595
FIFO_CONFIG5_HIRES_t
FIFO_CONFIG5_HIRES_t
Definition: inv_imu_defs.h:599
FIFO_CONFIG5_HIRES_DIS
@ FIFO_CONFIG5_HIRES_DIS
Definition: inv_imu_defs.h:601
FIFO_CONFIG5_HIRES_EN
@ FIFO_CONFIG5_HIRES_EN
Definition: inv_imu_defs.h:600
APEX_CONFIG5_HIGHG_PEAK_TH_HYST_t
APEX_CONFIG5_HIGHG_PEAK_TH_HYST_t
Definition: inv_imu_defs.h:809
APEX_CONFIG5_HIGHG_PEAK_TH_HYST_219_MG
@ APEX_CONFIG5_HIGHG_PEAK_TH_HYST_219_MG
Definition: inv_imu_defs.h:816
APEX_CONFIG5_HIGHG_PEAK_TH_HYST_94_MG
@ APEX_CONFIG5_HIGHG_PEAK_TH_HYST_94_MG
Definition: inv_imu_defs.h:812
APEX_CONFIG5_HIGHG_PEAK_TH_HYST_125_MG
@ APEX_CONFIG5_HIGHG_PEAK_TH_HYST_125_MG
Definition: inv_imu_defs.h:813
APEX_CONFIG5_HIGHG_PEAK_TH_HYST_63_MG
@ APEX_CONFIG5_HIGHG_PEAK_TH_HYST_63_MG
Definition: inv_imu_defs.h:811
APEX_CONFIG5_HIGHG_PEAK_TH_HYST_31_MG
@ APEX_CONFIG5_HIGHG_PEAK_TH_HYST_31_MG
Definition: inv_imu_defs.h:810
APEX_CONFIG5_HIGHG_PEAK_TH_HYST_188_MG
@ APEX_CONFIG5_HIGHG_PEAK_TH_HYST_188_MG
Definition: inv_imu_defs.h:815
APEX_CONFIG5_HIGHG_PEAK_TH_HYST_250_MG
@ APEX_CONFIG5_HIGHG_PEAK_TH_HYST_250_MG
Definition: inv_imu_defs.h:817
APEX_CONFIG5_HIGHG_PEAK_TH_HYST_156_MG
@ APEX_CONFIG5_HIGHG_PEAK_TH_HYST_156_MG
Definition: inv_imu_defs.h:814
WOM_CONFIG_WOM_EN_t
WOM_CONFIG_WOM_EN_t
Definition: inv_imu_defs.h:486
WOM_CONFIG_WOM_EN_ENABLE
@ WOM_CONFIG_WOM_EN_ENABLE
Definition: inv_imu_defs.h:487
WOM_CONFIG_WOM_EN_DISABLE
@ WOM_CONFIG_WOM_EN_DISABLE
Definition: inv_imu_defs.h:488
INTF_CONFIG0_FIFO_COUNT_ENDIAN_t
INTF_CONFIG0_FIFO_COUNT_ENDIAN_t
Definition: inv_imu_defs.h:550
INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN
@ INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN
Definition: inv_imu_defs.h:552
INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN
@ INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN
Definition: inv_imu_defs.h:551
SIGNAL_PATH_RESET_FIFO_FLUSH_t
SIGNAL_PATH_RESET_FIFO_FLUSH_t
Definition: inv_imu_defs.h:216
SIGNAL_PATH_RESET_FIFO_FLUSH_EN
@ SIGNAL_PATH_RESET_FIFO_FLUSH_EN
Definition: inv_imu_defs.h:217
SIGNAL_PATH_RESET_FIFO_FLUSH_DIS
@ SIGNAL_PATH_RESET_FIFO_FLUSH_DIS
Definition: inv_imu_defs.h:218
OTP_CTRL7_PWR_DOWN_t
OTP_CTRL7_PWR_DOWN_t
Definition: inv_imu_defs.h:1043
OTP_CTRL7_PWR_DOWN_EN
@ OTP_CTRL7_PWR_DOWN_EN
Definition: inv_imu_defs.h:1044
OTP_CTRL7_PWR_DOWN_DIS
@ OTP_CTRL7_PWR_DOWN_DIS
Definition: inv_imu_defs.h:1045
APEX_DATA_STEP_ACTIVITY_t
struct APEX_DATA_STEP_ACTIVITY APEX_DATA_STEP_ACTIVITY_t
APEX_CONFIG2_DMP_POWER_SAVE_TIME_t
APEX_CONFIG2_DMP_POWER_SAVE_TIME_t
Definition: inv_imu_defs.h:714
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_48_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_48_S
Definition: inv_imu_defs.h:727
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_16_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_16_S
Definition: inv_imu_defs.h:719
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_8_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_8_S
Definition: inv_imu_defs.h:717
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_60_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_60_S
Definition: inv_imu_defs.h:730
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_20_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_20_S
Definition: inv_imu_defs.h:720
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_24_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_24_S
Definition: inv_imu_defs.h:721
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_56_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_56_S
Definition: inv_imu_defs.h:729
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_0_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_0_S
Definition: inv_imu_defs.h:715
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_36_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_36_S
Definition: inv_imu_defs.h:724
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_32_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_32_S
Definition: inv_imu_defs.h:723
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_40_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_40_S
Definition: inv_imu_defs.h:725
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_28_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_28_S
Definition: inv_imu_defs.h:722
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_4_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_4_S
Definition: inv_imu_defs.h:716
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_44_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_44_S
Definition: inv_imu_defs.h:726
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_12_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_12_S
Definition: inv_imu_defs.h:718
APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_52_S
@ APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_52_S
Definition: inv_imu_defs.h:728
FIFO_CONFIG1_FIFO_BYPASS_t
FIFO_CONFIG1_FIFO_BYPASS_t
Definition: inv_imu_defs.h:503
FIFO_CONFIG1_FIFO_BYPASS_OFF
@ FIFO_CONFIG1_FIFO_BYPASS_OFF
Definition: inv_imu_defs.h:505
FIFO_CONFIG1_FIFO_BYPASS_ON
@ FIFO_CONFIG1_FIFO_BYPASS_ON
Definition: inv_imu_defs.h:504
TMST_CONFIG1_RESOL_t
TMST_CONFIG1_RESOL_t
Definition: inv_imu_defs.h:571
TMST_CONFIG1_RESOL_1us
@ TMST_CONFIG1_RESOL_1us
Definition: inv_imu_defs.h:573
TMST_CONFIG1_RESOL_16us
@ TMST_CONFIG1_RESOL_16us
Definition: inv_imu_defs.h:572
INT_CONFIG_INT2_POLARITY_t
INT_CONFIG_INT2_POLARITY_t
Definition: inv_imu_defs.h:239
INT_CONFIG_INT2_POLARITY_HIGH
@ INT_CONFIG_INT2_POLARITY_HIGH
Definition: inv_imu_defs.h:240
INT_CONFIG_INT2_POLARITY_LOW
@ INT_CONFIG_INT2_POLARITY_LOW
Definition: inv_imu_defs.h:241
APEX_CONFIG9_SENSITIVITY_MODE_t
APEX_CONFIG9_SENSITIVITY_MODE_t
Definition: inv_imu_defs.h:855
APEX_CONFIG9_SENSITIVITY_MODE_SLOW_WALK
@ APEX_CONFIG9_SENSITIVITY_MODE_SLOW_WALK
Definition: inv_imu_defs.h:857
APEX_CONFIG9_SENSITIVITY_MODE_NORMAL
@ APEX_CONFIG9_SENSITIVITY_MODE_NORMAL
Definition: inv_imu_defs.h:856
APEX_CONFIG1_PED_ENABLE_t
APEX_CONFIG1_PED_ENABLE_t
Definition: inv_imu_defs.h:447
APEX_CONFIG1_PED_ENABLE_EN
@ APEX_CONFIG1_PED_ENABLE_EN
Definition: inv_imu_defs.h:449
APEX_CONFIG1_PED_ENABLE_DIS
@ APEX_CONFIG1_PED_ENABLE_DIS
Definition: inv_imu_defs.h:448
APEX_CONFIG1_DMP_ODR_t
APEX_CONFIG1_DMP_ODR_t
Definition: inv_imu_defs.h:453
APEX_CONFIG1_DMP_ODR_100Hz
@ APEX_CONFIG1_DMP_ODR_100Hz
Definition: inv_imu_defs.h:456
APEX_CONFIG1_DMP_ODR_25Hz
@ APEX_CONFIG1_DMP_ODR_25Hz
Definition: inv_imu_defs.h:454
APEX_CONFIG1_DMP_ODR_400Hz
@ APEX_CONFIG1_DMP_ODR_400Hz
Definition: inv_imu_defs.h:457
APEX_CONFIG1_DMP_ODR_50Hz
@ APEX_CONFIG1_DMP_ODR_50Hz
Definition: inv_imu_defs.h:455
ACCEL_CONFIG1_ACCEL_FILT_AVG_t
ACCEL_CONFIG1_ACCEL_FILT_AVG_t
Definition: inv_imu_defs.h:379
ACCEL_CONFIG1_ACCEL_FILT_AVG_64
@ ACCEL_CONFIG1_ACCEL_FILT_AVG_64
Definition: inv_imu_defs.h:380
ACCEL_CONFIG1_ACCEL_FILT_AVG_2
@ ACCEL_CONFIG1_ACCEL_FILT_AVG_2
Definition: inv_imu_defs.h:385
ACCEL_CONFIG1_ACCEL_FILT_AVG_4
@ ACCEL_CONFIG1_ACCEL_FILT_AVG_4
Definition: inv_imu_defs.h:384
ACCEL_CONFIG1_ACCEL_FILT_AVG_32
@ ACCEL_CONFIG1_ACCEL_FILT_AVG_32
Definition: inv_imu_defs.h:381
ACCEL_CONFIG1_ACCEL_FILT_AVG_16
@ ACCEL_CONFIG1_ACCEL_FILT_AVG_16
Definition: inv_imu_defs.h:382
ACCEL_CONFIG1_ACCEL_FILT_AVG_8
@ ACCEL_CONFIG1_ACCEL_FILT_AVG_8
Definition: inv_imu_defs.h:383
APEX_CONFIG9_FF_DEBOUNCE_DURATION_t
APEX_CONFIG9_FF_DEBOUNCE_DURATION_t
Definition: inv_imu_defs.h:826
APEX_CONFIG9_FF_DEBOUNCE_DURATION_3000_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_3000_MS
Definition: inv_imu_defs.h:842
APEX_CONFIG9_FF_DEBOUNCE_DURATION_0_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_0_MS
Definition: inv_imu_defs.h:827
APEX_CONFIG9_FF_DEBOUNCE_DURATION_2500_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_2500_MS
Definition: inv_imu_defs.h:838
APEX_CONFIG9_FF_DEBOUNCE_DURATION_2125_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_2125_MS
Definition: inv_imu_defs.h:835
APEX_CONFIG9_FF_DEBOUNCE_DURATION_1750_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_1750_MS
Definition: inv_imu_defs.h:832
APEX_CONFIG9_FF_DEBOUNCE_DURATION_1875_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_1875_MS
Definition: inv_imu_defs.h:833
APEX_CONFIG9_FF_DEBOUNCE_DURATION_2375_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_2375_MS
Definition: inv_imu_defs.h:837
APEX_CONFIG9_FF_DEBOUNCE_DURATION_1500_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_1500_MS
Definition: inv_imu_defs.h:830
APEX_CONFIG9_FF_DEBOUNCE_DURATION_2750_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_2750_MS
Definition: inv_imu_defs.h:840
APEX_CONFIG9_FF_DEBOUNCE_DURATION_2250_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_2250_MS
Definition: inv_imu_defs.h:836
APEX_CONFIG9_FF_DEBOUNCE_DURATION_1375_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_1375_MS
Definition: inv_imu_defs.h:829
APEX_CONFIG9_FF_DEBOUNCE_DURATION_1250_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_1250_MS
Definition: inv_imu_defs.h:828
APEX_CONFIG9_FF_DEBOUNCE_DURATION_2875_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_2875_MS
Definition: inv_imu_defs.h:841
APEX_CONFIG9_FF_DEBOUNCE_DURATION_2000_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_2000_MS
Definition: inv_imu_defs.h:834
APEX_CONFIG9_FF_DEBOUNCE_DURATION_1625_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_1625_MS
Definition: inv_imu_defs.h:831
APEX_CONFIG9_FF_DEBOUNCE_DURATION_2625_MS
@ APEX_CONFIG9_FF_DEBOUNCE_DURATION_2625_MS
Definition: inv_imu_defs.h:839
APEX_CONFIG12_FF_MAX_DURATION_t
APEX_CONFIG12_FF_MAX_DURATION_t
Definition: inv_imu_defs.h:988
APEX_CONFIG12_FF_MAX_DURATION_254_CM
@ APEX_CONFIG12_FF_MAX_DURATION_254_CM
Definition: inv_imu_defs.h:996
APEX_CONFIG12_FF_MAX_DURATION_438_CM
@ APEX_CONFIG12_FF_MAX_DURATION_438_CM
Definition: inv_imu_defs.h:1002
APEX_CONFIG12_FF_MAX_DURATION_371_CM
@ APEX_CONFIG12_FF_MAX_DURATION_371_CM
Definition: inv_imu_defs.h:1000
APEX_CONFIG12_FF_MAX_DURATION_403_CM
@ APEX_CONFIG12_FF_MAX_DURATION_403_CM
Definition: inv_imu_defs.h:1001
APEX_CONFIG12_FF_MAX_DURATION_204_CM
@ APEX_CONFIG12_FF_MAX_DURATION_204_CM
Definition: inv_imu_defs.h:994
APEX_CONFIG12_FF_MAX_DURATION_102_CM
@ APEX_CONFIG12_FF_MAX_DURATION_102_CM
Definition: inv_imu_defs.h:989
APEX_CONFIG12_FF_MAX_DURATION_228_CM
@ APEX_CONFIG12_FF_MAX_DURATION_228_CM
Definition: inv_imu_defs.h:995
APEX_CONFIG12_FF_MAX_DURATION_120_CM
@ APEX_CONFIG12_FF_MAX_DURATION_120_CM
Definition: inv_imu_defs.h:990
APEX_CONFIG12_FF_MAX_DURATION_139_CM
@ APEX_CONFIG12_FF_MAX_DURATION_139_CM
Definition: inv_imu_defs.h:991
APEX_CONFIG12_FF_MAX_DURATION_181_CM
@ APEX_CONFIG12_FF_MAX_DURATION_181_CM
Definition: inv_imu_defs.h:993
APEX_CONFIG12_FF_MAX_DURATION_310_CM
@ APEX_CONFIG12_FF_MAX_DURATION_310_CM
Definition: inv_imu_defs.h:998
APEX_CONFIG12_FF_MAX_DURATION_339_CM
@ APEX_CONFIG12_FF_MAX_DURATION_339_CM
Definition: inv_imu_defs.h:999
APEX_CONFIG12_FF_MAX_DURATION_473_CM
@ APEX_CONFIG12_FF_MAX_DURATION_473_CM
Definition: inv_imu_defs.h:1003
APEX_CONFIG12_FF_MAX_DURATION_159_CM
@ APEX_CONFIG12_FF_MAX_DURATION_159_CM
Definition: inv_imu_defs.h:992
APEX_CONFIG12_FF_MAX_DURATION_510_CM
@ APEX_CONFIG12_FF_MAX_DURATION_510_CM
Definition: inv_imu_defs.h:1004
APEX_CONFIG12_FF_MAX_DURATION_281_CM
@ APEX_CONFIG12_FF_MAX_DURATION_281_CM
Definition: inv_imu_defs.h:997
APEX_DATA3_ACTIVITY_CLASS_t
APEX_DATA3_ACTIVITY_CLASS_t
Definition: inv_imu_defs.h:532
APEX_DATA3_ACTIVITY_CLASS_WALK
@ APEX_DATA3_ACTIVITY_CLASS_WALK
Definition: inv_imu_defs.h:534
APEX_DATA3_ACTIVITY_CLASS_RUN
@ APEX_DATA3_ACTIVITY_CLASS_RUN
Definition: inv_imu_defs.h:535
APEX_DATA3_ACTIVITY_CLASS_OTHER
@ APEX_DATA3_ACTIVITY_CLASS_OTHER
Definition: inv_imu_defs.h:533
ST_CONFIG_NUM_SAMPLES_t
ST_CONFIG_NUM_SAMPLES_t
Definition: inv_imu_defs.h:647
ST_CONFIG_200_SAMPLES
@ ST_CONFIG_200_SAMPLES
Definition: inv_imu_defs.h:649
ST_CONFIG_16_SAMPLES
@ ST_CONFIG_16_SAMPLES
Definition: inv_imu_defs.h:648
WOM_CONFIG_WOM_MODE_t
WOM_CONFIG_WOM_MODE_t
Definition: inv_imu_defs.h:480
WOM_CONFIG_WOM_MODE_CMP_INIT
@ WOM_CONFIG_WOM_MODE_CMP_INIT
Definition: inv_imu_defs.h:482
WOM_CONFIG_WOM_MODE_CMP_PREV
@ WOM_CONFIG_WOM_MODE_CMP_PREV
Definition: inv_imu_defs.h:481
APEX_CONFIG9_SMD_SENSITIVITY_t
APEX_CONFIG9_SMD_SENSITIVITY_t
Definition: inv_imu_defs.h:846
APEX_CONFIG9_SMD_SENSITIVITY_1
@ APEX_CONFIG9_SMD_SENSITIVITY_1
Definition: inv_imu_defs.h:848
APEX_CONFIG9_SMD_SENSITIVITY_0
@ APEX_CONFIG9_SMD_SENSITIVITY_0
Definition: inv_imu_defs.h:847
APEX_CONFIG9_SMD_SENSITIVITY_3
@ APEX_CONFIG9_SMD_SENSITIVITY_3
Definition: inv_imu_defs.h:850
APEX_CONFIG9_SMD_SENSITIVITY_4
@ APEX_CONFIG9_SMD_SENSITIVITY_4
Definition: inv_imu_defs.h:851
APEX_CONFIG9_SMD_SENSITIVITY_2
@ APEX_CONFIG9_SMD_SENSITIVITY_2
Definition: inv_imu_defs.h:849
INT_CONFIG_INT1_MODE_t
INT_CONFIG_INT1_MODE_t
Definition: inv_imu_defs.h:245
INT_CONFIG_INT1_MODE_LATCHED
@ INT_CONFIG_INT1_MODE_LATCHED
Definition: inv_imu_defs.h:246
INT_CONFIG_INT1_MODE_PULSED
@ INT_CONFIG_INT1_MODE_PULSED
Definition: inv_imu_defs.h:247
APEX_DATA3_DMP_IDLE_OFF_t
APEX_DATA3_DMP_IDLE_OFF_t
Definition: inv_imu_defs.h:526
APEX_DATA3_DMP_IDLE_ON
@ APEX_DATA3_DMP_IDLE_ON
Definition: inv_imu_defs.h:527
APEX_DATA3_DMP_IDLE_OFF
@ APEX_DATA3_DMP_IDLE_OFF
Definition: inv_imu_defs.h:528
ST_CONFIG_ACCEL_ST_LIM_t
ST_CONFIG_ACCEL_ST_LIM_t
Definition: inv_imu_defs.h:652
ST_CONFIG_ACCEL_ST_LIM_50
@ ST_CONFIG_ACCEL_ST_LIM_50
Definition: inv_imu_defs.h:653
INTF_CONFIG0_DATA_ENDIAN_t
INTF_CONFIG0_DATA_ENDIAN_t
Definition: inv_imu_defs.h:556
INTF_CONFIG0_DATA_LITTLE_ENDIAN
@ INTF_CONFIG0_DATA_LITTLE_ENDIAN
Definition: inv_imu_defs.h:558
INTF_CONFIG0_DATA_BIG_ENDIAN
@ INTF_CONFIG0_DATA_BIG_ENDIAN
Definition: inv_imu_defs.h:557
APEX_CONFIG2_LOW_ENERGY_AMP_TH_t
APEX_CONFIG2_LOW_ENERGY_AMP_TH_t
Definition: inv_imu_defs.h:694
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_85_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_85_MG
Definition: inv_imu_defs.h:706
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_35_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_35_MG
Definition: inv_imu_defs.h:696
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_45_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_45_MG
Definition: inv_imu_defs.h:698
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_90_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_90_MG
Definition: inv_imu_defs.h:707
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_50_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_50_MG
Definition: inv_imu_defs.h:699
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_55_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_55_MG
Definition: inv_imu_defs.h:700
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_60_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_60_MG
Definition: inv_imu_defs.h:701
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_40_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_40_MG
Definition: inv_imu_defs.h:697
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_100_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_100_MG
Definition: inv_imu_defs.h:709
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_95_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_95_MG
Definition: inv_imu_defs.h:708
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_65_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_65_MG
Definition: inv_imu_defs.h:702
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_75_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_75_MG
Definition: inv_imu_defs.h:704
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_105_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_105_MG
Definition: inv_imu_defs.h:710
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_70_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_70_MG
Definition: inv_imu_defs.h:703
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_80_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_80_MG
Definition: inv_imu_defs.h:705
APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_30_MG
@ APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_30_MG
Definition: inv_imu_defs.h:695
FIFO_CONFIG5_ACCEL_t
FIFO_CONFIG5_ACCEL_t
Definition: inv_imu_defs.h:619
FIFO_CONFIG5_ACCEL_EN
@ FIFO_CONFIG5_ACCEL_EN
Definition: inv_imu_defs.h:620
FIFO_CONFIG5_ACCEL_DIS
@ FIFO_CONFIG5_ACCEL_DIS
Definition: inv_imu_defs.h:621
OTP_CTRL7_OTP_RELOAD_t
OTP_CTRL7_OTP_RELOAD_t
Definition: inv_imu_defs.h:1037
OTP_CTRL7_OTP_RELOAD_EN
@ OTP_CTRL7_OTP_RELOAD_EN
Definition: inv_imu_defs.h:1038
OTP_CTRL7_OTP_RELOAD_DIS
@ OTP_CTRL7_OTP_RELOAD_DIS
Definition: inv_imu_defs.h:1039
INT_CONFIG_INT2_DRIVE_CIRCUIT_t
INT_CONFIG_INT2_DRIVE_CIRCUIT_t
Definition: inv_imu_defs.h:233
INT_CONFIG_INT2_DRIVE_CIRCUIT_OD
@ INT_CONFIG_INT2_DRIVE_CIRCUIT_OD
Definition: inv_imu_defs.h:235
INT_CONFIG_INT2_DRIVE_CIRCUIT_PP
@ INT_CONFIG_INT2_DRIVE_CIRCUIT_PP
Definition: inv_imu_defs.h:234
APEX_CONFIG10_LOWG_PEAK_TH_t
APEX_CONFIG10_LOWG_PEAK_TH_t
Definition: inv_imu_defs.h:866
APEX_CONFIG10_LOWG_PEAK_TH_125_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_125_MG
Definition: inv_imu_defs.h:870
APEX_CONFIG10_LOWG_PEAK_TH_438_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_438_MG
Definition: inv_imu_defs.h:880
APEX_CONFIG10_LOWG_PEAK_TH_63_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_63_MG
Definition: inv_imu_defs.h:868
APEX_CONFIG10_LOWG_PEAK_TH_219_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_219_MG
Definition: inv_imu_defs.h:873
APEX_CONFIG10_LOWG_PEAK_TH_406_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_406_MG
Definition: inv_imu_defs.h:879
APEX_CONFIG10_LOWG_PEAK_TH_156_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_156_MG
Definition: inv_imu_defs.h:871
APEX_CONFIG10_LOWG_PEAK_TH_781_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_781_MG
Definition: inv_imu_defs.h:891
APEX_CONFIG10_LOWG_PEAK_TH_906_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_906_MG
Definition: inv_imu_defs.h:895
APEX_CONFIG10_LOWG_PEAK_TH_500_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_500_MG
Definition: inv_imu_defs.h:882
APEX_CONFIG10_LOWG_PEAK_TH_688_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_688_MG
Definition: inv_imu_defs.h:888
APEX_CONFIG10_LOWG_PEAK_TH_563_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_563_MG
Definition: inv_imu_defs.h:884
APEX_CONFIG10_LOWG_PEAK_TH_94_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_94_MG
Definition: inv_imu_defs.h:869
APEX_CONFIG10_LOWG_PEAK_TH_656_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_656_MG
Definition: inv_imu_defs.h:887
APEX_CONFIG10_LOWG_PEAK_TH_594_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_594_MG
Definition: inv_imu_defs.h:885
APEX_CONFIG10_LOWG_PEAK_TH_969_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_969_MG
Definition: inv_imu_defs.h:897
APEX_CONFIG10_LOWG_PEAK_TH_344_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_344_MG
Definition: inv_imu_defs.h:877
APEX_CONFIG10_LOWG_PEAK_TH_1000_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_1000_MG
Definition: inv_imu_defs.h:898
APEX_CONFIG10_LOWG_PEAK_TH_531_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_531_MG
Definition: inv_imu_defs.h:883
APEX_CONFIG10_LOWG_PEAK_TH_313_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_313_MG
Definition: inv_imu_defs.h:876
APEX_CONFIG10_LOWG_PEAK_TH_31_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_31_MG
Definition: inv_imu_defs.h:867
APEX_CONFIG10_LOWG_PEAK_TH_375_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_375_MG
Definition: inv_imu_defs.h:878
APEX_CONFIG10_LOWG_PEAK_TH_719_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_719_MG
Definition: inv_imu_defs.h:889
APEX_CONFIG10_LOWG_PEAK_TH_469_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_469_MG
Definition: inv_imu_defs.h:881
APEX_CONFIG10_LOWG_PEAK_TH_750_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_750_MG
Definition: inv_imu_defs.h:890
APEX_CONFIG10_LOWG_PEAK_TH_250_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_250_MG
Definition: inv_imu_defs.h:874
APEX_CONFIG10_LOWG_PEAK_TH_844_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_844_MG
Definition: inv_imu_defs.h:893
APEX_CONFIG10_LOWG_PEAK_TH_188_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_188_MG
Definition: inv_imu_defs.h:872
APEX_CONFIG10_LOWG_PEAK_TH_625_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_625_MG
Definition: inv_imu_defs.h:886
APEX_CONFIG10_LOWG_PEAK_TH_875_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_875_MG
Definition: inv_imu_defs.h:894
APEX_CONFIG10_LOWG_PEAK_TH_813_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_813_MG
Definition: inv_imu_defs.h:892
APEX_CONFIG10_LOWG_PEAK_TH_938_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_938_MG
Definition: inv_imu_defs.h:896
APEX_CONFIG10_LOWG_PEAK_TH_281_MG
@ APEX_CONFIG10_LOWG_PEAK_TH_281_MG
Definition: inv_imu_defs.h:875
FDR_CONFIG_FDR_SEL_t
FDR_CONFIG_FDR_SEL_t
Definition: inv_imu_defs.h:971
FDR_CONFIG_FDR_SEL_FACTOR_128
@ FDR_CONFIG_FDR_SEL_FACTOR_128
Definition: inv_imu_defs.h:979
FDR_CONFIG_FDR_SEL_DIS
@ FDR_CONFIG_FDR_SEL_DIS
Definition: inv_imu_defs.h:972
FDR_CONFIG_FDR_SEL_FACTOR_16
@ FDR_CONFIG_FDR_SEL_FACTOR_16
Definition: inv_imu_defs.h:976
FDR_CONFIG_FDR_SEL_FACTOR_64
@ FDR_CONFIG_FDR_SEL_FACTOR_64
Definition: inv_imu_defs.h:978
FDR_CONFIG_FDR_SEL_FACTOR_32
@ FDR_CONFIG_FDR_SEL_FACTOR_32
Definition: inv_imu_defs.h:977
FDR_CONFIG_FDR_SEL_FACTOR_4
@ FDR_CONFIG_FDR_SEL_FACTOR_4
Definition: inv_imu_defs.h:974
FDR_CONFIG_FDR_SEL_FACTOR_256
@ FDR_CONFIG_FDR_SEL_FACTOR_256
Definition: inv_imu_defs.h:980
FDR_CONFIG_FDR_SEL_FACTOR_2
@ FDR_CONFIG_FDR_SEL_FACTOR_2
Definition: inv_imu_defs.h:973
FDR_CONFIG_FDR_SEL_FACTOR_8
@ FDR_CONFIG_FDR_SEL_FACTOR_8
Definition: inv_imu_defs.h:975
OTP_CONFIG_COPY_MODE_t
OTP_CONFIG_COPY_MODE_t
Definition: inv_imu_defs.h:683
OTP_CONFIG_OTP_COPY_ST_DATA
@ OTP_CONFIG_OTP_COPY_ST_DATA
Definition: inv_imu_defs.h:685
OTP_CONFIG_OTP_COPY_TRIM
@ OTP_CONFIG_OTP_COPY_TRIM
Definition: inv_imu_defs.h:684
INT_CONFIG_INT2_MODE_t
INT_CONFIG_INT2_MODE_t
Definition: inv_imu_defs.h:227
INT_CONFIG_INT2_MODE_LATCHED
@ INT_CONFIG_INT2_MODE_LATCHED
Definition: inv_imu_defs.h:228
INT_CONFIG_INT2_MODE_PULSED
@ INT_CONFIG_INT2_MODE_PULSED
Definition: inv_imu_defs.h:229
INT_CONFIG_INT1_POLARITY_t
INT_CONFIG_INT1_POLARITY_t
Definition: inv_imu_defs.h:257
INT_CONFIG_INT1_POLARITY_HIGH
@ INT_CONFIG_INT1_POLARITY_HIGH
Definition: inv_imu_defs.h:258
INT_CONFIG_INT1_POLARITY_LOW
@ INT_CONFIG_INT1_POLARITY_LOW
Definition: inv_imu_defs.h:259
APEX_CONFIG0_DMP_INIT_t
APEX_CONFIG0_DMP_INIT_t
Definition: inv_imu_defs.h:412
APEX_CONFIG0_DMP_INIT_EN
@ APEX_CONFIG0_DMP_INIT_EN
Definition: inv_imu_defs.h:413
APEX_CONFIG0_DMP_INIT_DIS
@ APEX_CONFIG0_DMP_INIT_DIS
Definition: inv_imu_defs.h:414
APEX_CONFIG11_HIGHG_TIME_TH_SAMPLES_t
APEX_CONFIG11_HIGHG_TIME_TH_SAMPLES_t
Definition: inv_imu_defs.h:954
APEX_CONFIG11_HIGHG_TIME_TH_8_SAMPLES
@ APEX_CONFIG11_HIGHG_TIME_TH_8_SAMPLES
Definition: inv_imu_defs.h:962
APEX_CONFIG11_HIGHG_TIME_TH_5_SAMPLES
@ APEX_CONFIG11_HIGHG_TIME_TH_5_SAMPLES
Definition: inv_imu_defs.h:959
APEX_CONFIG11_HIGHG_TIME_TH_1_SAMPLE
@ APEX_CONFIG11_HIGHG_TIME_TH_1_SAMPLE
Definition: inv_imu_defs.h:955
APEX_CONFIG11_HIGHG_TIME_TH_6_SAMPLES
@ APEX_CONFIG11_HIGHG_TIME_TH_6_SAMPLES
Definition: inv_imu_defs.h:960
APEX_CONFIG11_HIGHG_TIME_TH_2_SAMPLES
@ APEX_CONFIG11_HIGHG_TIME_TH_2_SAMPLES
Definition: inv_imu_defs.h:956
APEX_CONFIG11_HIGHG_TIME_TH_3_SAMPLES
@ APEX_CONFIG11_HIGHG_TIME_TH_3_SAMPLES
Definition: inv_imu_defs.h:957
APEX_CONFIG11_HIGHG_TIME_TH_7_SAMPLES
@ APEX_CONFIG11_HIGHG_TIME_TH_7_SAMPLES
Definition: inv_imu_defs.h:961
APEX_CONFIG11_HIGHG_TIME_TH_4_SAMPLES
@ APEX_CONFIG11_HIGHG_TIME_TH_4_SAMPLES
Definition: inv_imu_defs.h:958
PWR_MGMT0_ACCEL_MODE_t
PWR_MGMT0_ACCEL_MODE_t
Definition: inv_imu_defs.h:290
PWR_MGMT0_ACCEL_MODE_OFF
@ PWR_MGMT0_ACCEL_MODE_OFF
Definition: inv_imu_defs.h:293
PWR_MGMT0_ACCEL_MODE_LP
@ PWR_MGMT0_ACCEL_MODE_LP
Definition: inv_imu_defs.h:292
PWR_MGMT0_ACCEL_MODE_LN
@ PWR_MGMT0_ACCEL_MODE_LN
Definition: inv_imu_defs.h:291
ACCEL_CONFIG0_ODR_t
ACCEL_CONFIG0_ODR_t
Definition: inv_imu_defs.h:340
ACCEL_CONFIG0_ODR_50_HZ
@ ACCEL_CONFIG0_ODR_50_HZ
Definition: inv_imu_defs.h:346
ACCEL_CONFIG0_ODR_800_HZ
@ ACCEL_CONFIG0_ODR_800_HZ
Definition: inv_imu_defs.h:350
ACCEL_CONFIG0_ODR_25_HZ
@ ACCEL_CONFIG0_ODR_25_HZ
Definition: inv_imu_defs.h:345
ACCEL_CONFIG0_ODR_1600_HZ
@ ACCEL_CONFIG0_ODR_1600_HZ
Definition: inv_imu_defs.h:351
ACCEL_CONFIG0_ODR_12_5_HZ
@ ACCEL_CONFIG0_ODR_12_5_HZ
Definition: inv_imu_defs.h:344
ACCEL_CONFIG0_ODR_3_125_HZ
@ ACCEL_CONFIG0_ODR_3_125_HZ
Definition: inv_imu_defs.h:342
ACCEL_CONFIG0_ODR_100_HZ
@ ACCEL_CONFIG0_ODR_100_HZ
Definition: inv_imu_defs.h:347
ACCEL_CONFIG0_ODR_200_HZ
@ ACCEL_CONFIG0_ODR_200_HZ
Definition: inv_imu_defs.h:348
ACCEL_CONFIG0_ODR_400_HZ
@ ACCEL_CONFIG0_ODR_400_HZ
Definition: inv_imu_defs.h:349
ACCEL_CONFIG0_ODR_1_5625_HZ
@ ACCEL_CONFIG0_ODR_1_5625_HZ
Definition: inv_imu_defs.h:341
ACCEL_CONFIG0_ODR_6_25_HZ
@ ACCEL_CONFIG0_ODR_6_25_HZ
Definition: inv_imu_defs.h:343
DEVICE_CONFIG_SPI_MODE_t
DEVICE_CONFIG_SPI_MODE_t
Definition: inv_imu_defs.h:191
DEVICE_CONFIG_SPI_MODE_1_2
@ DEVICE_CONFIG_SPI_MODE_1_2
Definition: inv_imu_defs.h:192
DEVICE_CONFIG_SPI_MODE_0_3
@ DEVICE_CONFIG_SPI_MODE_0_3
Definition: inv_imu_defs.h:193
fifo_header_t
Describe the content of the FIFO header.
Definition: inv_imu_defs.h:144
fifo_header_t::accel_odr_different
unsigned char accel_odr_different
Definition: inv_imu_defs.h:152
fifo_header_t::reserved2
unsigned char reserved2
Definition: inv_imu_defs.h:156
fifo_header_t::msg_bit
unsigned char msg_bit
Definition: inv_imu_defs.h:166
fifo_header_t::Byte
unsigned char Byte
Definition: inv_imu_defs.h:145
fifo_header_t::reserved1
unsigned char reserved1
Definition: inv_imu_defs.h:150
fifo_header_t::reserved3
unsigned char reserved3
Definition: inv_imu_defs.h:163
fifo_header_t::accel_bit
unsigned char accel_bit
Definition: inv_imu_defs.h:165
fifo_header_t::twentybits_bit
unsigned char twentybits_bit
Definition: inv_imu_defs.h:159
fifo_header_t::timestamp_bit
unsigned char timestamp_bit
Definition: inv_imu_defs.h:158
APEX_DATA_STEP_ACTIVITY
Definition: inv_imu_defs.h:514
APEX_DATA_STEP_ACTIVITY::step_cadence
uint8_t step_cadence
Definition: inv_imu_defs.h:516
APEX_DATA_STEP_ACTIVITY::activity_class
uint8_t activity_class
Definition: inv_imu_defs.h:517
APEX_DATA_STEP_ACTIVITY::step_cnt
uint16_t step_cnt
Definition: inv_imu_defs.h:515