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Icm426xxDefs.h
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1 /*
2 * ________________________________________________________________________________________________________
3 * Copyright (c) 2017 InvenSense Inc. All rights reserved.
4 *
5 * This software, related documentation and any modifications thereto (collectively “Software”) is subject
6 * to InvenSense and its licensors' intellectual property rights under U.S. and international copyright
7 * and other intellectual property rights laws.
8 *
9 * InvenSense and its licensors retain all intellectual property and proprietary rights in and to the Software
10 * and any use, reproduction, disclosure or distribution of the Software without an express license agreement
11 * from InvenSense is strictly prohibited.
12 *
13 * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE SOFTWARE IS
14 * PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
15 * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
16 * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL
17 * INVENSENSE BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY
18 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
19 * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THE SOFTWARE.
21 * ________________________________________________________________________________________________________
22 */
23
24 #ifndef _INV_ICM426XX_DEFS_H_
25 #define _INV_ICM426XX_DEFS_H_
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
35 #include <stdint.h>
36
37 /* List whoami values for all icm426xx variants*/
38 #define ICM40608_WHOAMI 0x39
39 #define ICM42600_WHOAMI 0x40
40 #define ICM42602_WHOAMI 0x41
41 #define ICM42605_WHOAMI 0x42
42 #define ICM42622_WHOAMI 0x46
43 #define ICM42631_WHOAMI 0x5C
44 #define ICM42633_WHOAMI 0x5B
45 #define ICM42686P_WHOAMI 0x44
46 #define ICM42688P_WHOAMI 0x47
47 #define ICM42686V_WHOAMI 0xDA
48 #define ICM42688V_WHOAMI 0xDB
49 #define ICM42608_WHOAMI 0x48
50
51 /* Define whoami value for the targeted product and make sure the target is valid */
52 #if defined(ICM42600)
53 #define ICM_WHOAMI ICM42600_WHOAMI
54 #elif defined(ICM42602)
55 #define ICM_WHOAMI ICM42602_WHOAMI
56 #elif defined(ICM42605)
57 #define ICM_WHOAMI ICM42605_WHOAMI
58 #elif defined(ICM42622)
59 #define ICM_WHOAMI ICM42622_WHOAMI
60 #elif defined(ICM42631)
61 #define ICM_WHOAMI ICM42631_WHOAMI
62 #elif defined(ICM42633)
63 #define ICM_WHOAMI ICM42633_WHOAMI
64 #elif defined(ICM42686V)
65 #define ICM_WHOAMI ICM42686V_WHOAMI
66 #elif defined(ICM42688V)
67 #define ICM_WHOAMI ICM42688V_WHOAMI
68 #elif defined(ICM42686P)
69 #define ICM_WHOAMI ICM42686P_WHOAMI
70 #elif defined(ICM42688P)
71 #define ICM_WHOAMI ICM42688P_WHOAMI
72 #elif defined(ICM42608)
73 #define ICM_WHOAMI ICM42608_WHOAMI
74 #elif defined(ICM40608)
75 #define ICM_WHOAMI ICM40608_WHOAMI
76 #else
77 #error "Please define which ICM variant is targeted. Possible values: " \
78 "ICM42600, " \
79 "ICM42602, " \
80 "ICM42605, " \
81 "ICM42622, " \
82 "ICM42631, " \
83 "ICM42633, " \
84 "ICM42686V, " \
85 "ICM42688V, " \
86 "ICM42686P, " \
87 "ICM42688P, " \
88 "ICM42608, " \
89 "ICM40608"
90 #endif
91
95 #if (defined(ICM42631) || defined(ICM42633))
96 #define ICM_FAMILY_CPLUS
97 #else
98 #define ICM_FAMILY_BPLUS
99 #endif
100
101 /* ----------------------------------------------------------------------------
102 * Device Register map
103 *
104 * Next macros defines address for all icm426xx registers as listed by device
105 * datasheet.
106 * Macros name is MPUREG_<REGISTER_NAME> with REGISTER_NAME being the name of
107 * the corresponding register in datasheet.
108 * Note that macro name is MPUREG_<REGISTER_NAME>_Bx with x being the bank
109 * number for registers that are in bank 1 and 2 (suffix is ommitted for
110 * bank0 registers)
111 * ---------------------------------------------------------------------------- */
112
113 /* Bank 0 */
114 #define MPUREG_DEVICE_CONFIG 0x11
115 #define MPUREG_CHIP_CONFIG MPUREG_DEVICE_CONFIG // Retro-compatibility
116 #define MPUREG_DRIVE_CONFIG 0x13
117 #define MPUREG_INT_CONFIG 0x14
118 #define MPUREG_FIFO_CONFIG 0x16
119 #define MPUREG_TEMP_DATA0_UI 0x1D
120 #define MPUREG_ACCEL_DATA_X0_UI 0x1F
121 #define MPUREG_GYRO_DATA_X0_UI 0x25
122 #define MPUREG_TMST_FSYNCH 0x2B
123 #define MPUREG_TMST_FSYNC1 MPUREG_TMST_FSYNCH // Retro-compatibility
124 #define MPUREG_INT_STATUS 0x2D
125 #define MPUREG_FIFO_COUNTH 0x2E
126 #define MPUREG_FIFO_BYTE_COUNT1 MPUREG_FIFO_COUNTH // Retro-compatibility
127 #define MPUREG_FIFO_COUNTL 0x2F
128 #define MPUREG_FIFO_BYTE_COUNT2 MPUREG_FIFO_COUNTL // Retro-compatibility
129 #define MPUREG_FIFO_DATA 0x30
130 #define MPUREG_APEX_DATA0 0x31
131 #define MPUREG_APEX_DATA1 0x32
132 #define MPUREG_APEX_DATA2 0x33
133 #define MPUREG_APEX_DATA3 0x34
134 #define MPUREG_APEX_DATA4 0x35
135 #define MPUREG_APEX_DATA5 0x36
136 #define MPUREG_INT_STATUS2 0x37
137 #define MPUREG_INT_STATUS3 0x38
138 #define MPUREG_SIGNAL_PATH_RESET 0x4B
139 #define MPUREG_INTF_CONFIG0 0x4C
140 #define MPUREG_INTF_CONFIG1 0x4D
141 #define MPUREG_PWR_MGMT_0 0x4E
142 #define MPUREG_GYRO_CONFIG0 0x4F
143 #define MPUREG_ACCEL_CONFIG0 0x50
144 #define MPUREG_GYRO_CONFIG1 0x51
145 #define MPUREG_ACCEL_GYRO_CONFIG0 0x52
146 #define MPUREG_ACCEL_CONFIG1 0x53
147 #define MPUREG_TMST_CONFIG 0x54
148 #define MPUREG_APEX_CONFIG0 0x56
149 #define MPUREG_SMD_CONFIG 0x57
150 #define MPUREG_FIFO_CONFIG1 0x5F
151 #define MPUREG_FIFO_CONFIG2 0x60
152 #define MPUREG_FSYNC_CONFIG 0x62
153 #define MPUREG_INT_CONFIG0 0x63
154 #define MPUREG_INT_CONFIG1 0x64
155 #define MPUREG_INT_SOURCE0 0x65
156 #define MPUREG_INT_SOURCE1 0x66
157 #define MPUREG_INT_SOURCE2 0x67
158 #define MPUREG_INT_SOURCE3 0x68
159 #define MPUREG_INT_SOURCE4 0x69
160 #define MPUREG_INT_SOURCE5 0x6A
161 #define MPUREG_FIFO_LOST_PKT0 0x6C
162 #define MPUREG_SELF_TEST_CONFIG 0x70
163 #define MPUREG_WHO_AM_I 0x75
164 #define MPUREG_SCAN0 0x71
165 #define MPUREG_MEM_BANK_SEL 0x72
166 #define MPUREG_MEM_START_ADDR 0x73
167 #define MPUREG_MEM_R_W 0x74
168 #define MPUREG_REG_BANK_SEL 0x76
169
170 /* Bank 1 */
171 #define MPUREG_SENSOR_CONFIG1_B1 0x04
172 #define MPUREG_GYRO_CONFIG_STATIC2_B1 0x0B
173 #define MPUREG_GYRO_CONFIG_STATIC3_B1 0x0C
174 #define MPUREG_GYRO_CONFIG_STATIC4_B1 0x0D
175 #define MPUREG_GYRO_CONFIG_STATIC5_B1 0x0E
176 #define MPUREG_XG_ST_DATA_B1 0x5F
177 #define MPUREG_YG_ST_DATA_B1 0x60
178 #define MPUREG_ZG_ST_DATA_B1 0x61
179 #define MPUREG_TMST_VAL0_B1 0x62
180 #define MPUREG_INTF_CONFIG4_B1 0x7A
181 #define MPUREG_INTF_CONFIG5_B1 0x7B
182 #define MPUREG_INTF_CONFIG6_B1 0x7C
183 #define MPUREG_INTF_CONFIG3_B1 0x79
184
185 /* Bank 2 */
186 #define MPUREG_ACCEL_CONFIG_STATIC2_B2 0x03
187 #define MPUREG_ACCEL_CONFIG_STATIC3_B2 0x04
188 #define MPUREG_ACCEL_CONFIG_STATIC4_B2 0x05
189 #define MPUREG_ACCEL_CONFIG_STATIC0_B2 0x39
190 #define MPUREG_XA_ST_DATA_B2 0x3B
191 #define MPUREG_YA_ST_DATA_B2 0x3C
192 #define MPUREG_ZA_ST_DATA_B2 0x3D
193 /* Only accessible from AUX1 */
194 #define MPUREG_OIS1_CONFIG1_B2 0x44
195 #define MPUREG_OIS1_CONFIG2_B2 0x45
196 #define MPUREG_OIS1_CONFIG3_B2 0x46
197 #define MPUREG_ACCEL_DATA_X0_OIS1_B2 0x49
198 #define MPUREG_GYRO_DATA_X0_OIS1_B2 0x4F
199 #define MPUREG_INT_STATUS_OIS1_B2 0x57
200 /* End of Only accessible from AUX1 */
201 /* Only accessible from AUX2 */
202 #define MPUREG_OIS2_CONFIG1_B2 0x59
203 #define MPUREG_OIS2_CONFIG2_B2 0x5A
204 #define MPUREG_OIS2_CONFIG3_B2 0x5B
205 #define MPUREG_ACCEL_DATA_X0_OIS2_B2 0x5E
206 #define MPUREG_GYRO_DATA_X0_OIS2_B2 0x64
207 #define MPUREG_INT_STATUS_OIS2_B2 0x6C
208 /* End of Only accessible from AUX2 */
209 #define MPUREG_TMD4_B2 0x70
210 #define MPUREG_TMD5_B2 0x71
211 #define MPUREG_TMD6_B2 0x72
212 #define MPUREG_TMD7_B2 0x73
213
214 /* Bank 3 */
215 #define MPUREG_PU_PD_CONFIG1_B3 0x06
216 #define MPUREG_PU_PD_CONFIG2_B3 0x0E
217
218 /* Bank 4 */
219 #define MPUREG_FDR_CONFIG_B4 0x09
220 #define MPUREG_APEX_CONFIG1_B4 0x40
221 #define MPUREG_APEX_CONFIG2_B4 0x41
222 #define MPUREG_APEX_CONFIG3_B4 0x42
223 #define MPUREG_APEX_CONFIG4_B4 0x43
224 #define MPUREG_APEX_CONFIG5_B4 0x44
225 #define MPUREG_APEX_CONFIG6_B4 0x45
226 #define MPUREG_APEX_CONFIG7_B4 0x46
227 #define MPUREG_APEX_CONFIG8_B4 0x47
228 #define MPUREG_APEX_CONFIG9_B4 0x48
229 #define MPUREG_APEX_CONFIG10_B4 0x49
230 #define MPUREG_ACCEL_WOM_X_THR_B4 0x4A
231 #define MPUREG_ACCEL_WOM_Y_THR_B4 0x4B
232 #define MPUREG_ACCEL_WOM_Z_THR_B4 0x4C
233 #define MPUREG_INT_SOURCE6_B4 0x4D
234 #define MPUREG_INT_SOURCE7_B4 0x4E
235 #define MPUREG_INT_SOURCE8_B4 0x4F
236 #define MPUREG_INT_SOURCE9_B4 0x50
237 #define MPUREG_INT_SOURCE10_B4 0x51
238 #define MPUREG_OFFSET_USER_0_B4 0x77
239 #define MPUREG_OFFSET_USER_1_B4 0x78
240 #define MPUREG_OFFSET_USER_2_B4 0x79
241 #define MPUREG_OFFSET_USER_3_B4 0x7A
242 #define MPUREG_OFFSET_USER_4_B4 0x7B
243 #define MPUREG_OFFSET_USER_5_B4 0x7C
244 #define MPUREG_OFFSET_USER_6_B4 0x7D
245 #define MPUREG_OFFSET_USER_7_B4 0x7E
246 #define MPUREG_OFFSET_USER_8_B4 0x7F
247
248 /* ----------------------------------------------------------------------------
249 * Device features
250 *
251 * Next macros define some of the device features such as FIFO, sensor data
252 * size or whoami value.
253 * ---------------------------------------------------------------------------- */
254
255 #define ACCEL_DATA_SIZE 6
256 #define GYRO_DATA_SIZE 6
257 #define TEMP_DATA_SIZE 2
258
259 #define FIFO_HEADER_SIZE 1
260 #define FIFO_ACCEL_DATA_SIZE ACCEL_DATA_SIZE
261 #define FIFO_GYRO_DATA_SIZE GYRO_DATA_SIZE
262 #define FIFO_TEMP_DATA_SIZE 1
263 #define FIFO_TS_FSYNC_SIZE 2
264 #define FIFO_TEMP_HIGH_RES_SIZE 1
265 #define FIFO_ACCEL_GYRO_HIGH_RES_SIZE 3
266
267 #define FIFO_16BYTES_PACKET_SIZE \
268 (FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + \
269 FIFO_TS_FSYNC_SIZE)
270 #define FIFO_20BYTES_PACKET_SIZE \
271 (FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + \
272 FIFO_TS_FSYNC_SIZE + FIFO_TEMP_HIGH_RES_SIZE + FIFO_ACCEL_GYRO_HIGH_RES_SIZE)
273
274 #define FIFO_HEADER_ODR_ACCEL 0x01
275 #define FIFO_HEADER_ODR_GYRO 0x02
276 #define FIFO_HEADER_FSYNC 0x04
277 #define FIFO_HEADER_TMST 0x08
278 #define FIFO_HEADER_HEADER_20 0x10
279 #define FIFO_HEADER_GYRO 0x20
280 #define FIFO_HEADER_ACC 0x40
281 #define FIFO_HEADER_MSG 0x80
282
283 #define INVALID_VALUE_FIFO ((int16_t)0x8000)
284 #define INVALID_VALUE_FIFO_1B ((int8_t)0x80)
285
287 typedef union {
288 unsigned char Byte;
289 struct {
290 unsigned char gyro_odr_different : 1;
291 unsigned char accel_odr_different : 1;
292 unsigned char fsync_bit : 1;
293 unsigned char timestamp_bit : 1;
294 unsigned char twentybits_bit : 1;
295 unsigned char gyro_bit : 1;
296 unsigned char accel_bit : 1;
297 unsigned char msg_bit : 1;
298 } bits;
299 } fifo_header_t;
300
301 #define I3C_IBI_PAYLOAD_ALL 0xFF
302 #define I3C_IBI_PAYLOAD_TIMEC 0x80
303 #define I3C_IBI_PAYLOAD_CAT_MISC 0x40
304 #define I3C_IBI_PAYLOAD_CAT_ERROR 0x20
305 #define I3C_IBI_PAYLOAD_CAT_APEX2 0x10
306 #define I3C_IBI_PAYLOAD_CAT_APEX1 0x08
307 #define I3C_IBI_PAYLOAD_CAT_OIS1_DRDY 0x04
308 #define I3C_IBI_PAYLOAD_CAT_FIFO 0x02
309 #define I3C_IBI_PAYLOAD_CAT_UI_DRDY 0x01
310
311 /* ----------------------------------------------------------------------------
312 * Device registers description
313 *
314 * Next section defines some of the registers bitfield and declare corresponding
315 * accessors.
316 * Note that descriptors and accessors are not provided for all the registers
317 * but only for the most useful ones.
318 * For all details on registers and bitfields functionalities please refer to
319 * the device datasheet.
320 * ---------------------------------------------------------------------------- */
321
322 /* ---------------------------------------------------------------------------
323 * register bank 0
324 * ---------------------------------------------------------------------------- */
325
326 /*
327 * MPUREG_DEVICE_CONFIG
328 * Register Name : DEVICE_CONFIG
329 */
330
331 /* SPI_MODE */
332 #define BIT_DEVICE_CONFIG_SPI_MODE_POS 4
333 #define BIT_DEVICE_CONFIG_SPI_MODE_MASK (0x1 << BIT_DEVICE_CONFIG_SPI_MODE_POS)
334 #define BIT_CHIP_CONFIG_SPI_MODE_MASK BIT_DEVICE_CONFIG_SPI_MODE_MASK //retro-compatibility
335 #define BIT_CHIP_CONFIG_SPI_MODE_POS BIT_DEVICE_CONFIG_SPI_MODE_POS //retro-compatibility
336
337 typedef enum {
338 ICM426XX_DEVICE_CONFIG_SPI_MODE_1_2 = (0x1 << BIT_DEVICE_CONFIG_SPI_MODE_POS),
339 ICM426XX_DEVICE_CONFIG_SPI_MODE_0_3 = (0x0 << BIT_DEVICE_CONFIG_SPI_MODE_POS),
340 } ICM426XX_DEVICE_CONFIG_SPI_MODE_t;
341
342 typedef enum {
343 ICM426XX_CHIP_CONFIG_SPI_MODE_1_2 = (0x1 << BIT_CHIP_CONFIG_SPI_MODE_POS),
344 ICM426XX_CHIP_CONFIG_SPI_MODE_0_3 = (0x0 << BIT_CHIP_CONFIG_SPI_MODE_POS),
345 } ICM426XX_CHIP_CONFIG_SPI_MODE_t; //retro-compatibility
346
347 /* SOFT_RESET */
348 #define BIT_DEVICE_CONFIG_RESET_POS 0
349 #define BIT_DEVICE_CONFIG_RESET_MASK 0x01
350 #define BIT_CHIP_CONFIG_RESET_MASK BIT_DEVICE_CONFIG_RESET_MASK //retro-compatibility
351 #define BIT_CHIP_CONFIG_RESET_POS BIT_DEVICE_CONFIG_RESET_POS //retro-compatibility
352
353 typedef enum {
354 ICM426XX_DEVICE_CONFIG_RESET_EN = 0x01,
355 ICM426XX_DEVICE_CONFIG_RESET_NONE = 0x00,
356 } ICM426XX_DEVICE_CONFIG_RESET_t;
357
358 typedef enum {
359 ICM426XX_CHIP_CONFIG_RESET_EN = 0x01,
360 ICM426XX_CHIP_CONFIG_RESET_NONE = 0x00,
361 } ICM426XX_CHIP_CONFIG_RESET_t; //retro-compatibility
362
363 /*
364 * MPUREG_INT_CONFIG
365 * Register Name: INT_CONFIG
366 */
367
368 /* INT2_DRIVE_CIRCUIT */
369 #define BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS 4
370 #define BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS)
371
372 typedef enum {
373 ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_PP = (0x01 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS),
374 ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_OD = (0x00 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS),
375 } ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_t;
376
377 /* INT2_POLARITY */
378 #define BIT_INT_CONFIG_INT2_POLARITY_POS 3
379 #define BIT_INT_CONFIG_INT2_POLARITY_MASK (0x01 << BIT_INT_CONFIG_INT2_POLARITY_POS)
380
381 typedef enum {
382 ICM426XX_INT_CONFIG_INT2_POLARITY_HIGH = (0x01 << BIT_INT_CONFIG_INT2_POLARITY_POS),
383 ICM426XX_INT_CONFIG_INT2_POLARITY_LOW = (0x00 << BIT_INT_CONFIG_INT2_POLARITY_POS),
384 } ICM426XX_INT_CONFIG_INT2_POLARITY_t;
385
386 /* INT1_DRIVE_CIRCUIT */
387 #define BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS 1
388 #define BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS)
389
390 typedef enum {
391 ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_PP = (0x01 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS),
392 ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_OD = (0x00 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS),
393 } ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t;
394
395 /* INT1_POLARITY */
396 #define BIT_INT_CONFIG_INT1_POLARITY_POS 0
397 #define BIT_INT_CONFIG_INT1_POLARITY_MASK 0x01
398
399 typedef enum {
400 ICM426XX_INT_CONFIG_INT1_POLARITY_HIGH = 0x01,
401 ICM426XX_INT_CONFIG_INT1_POLARITY_LOW = 0x00,
402 } ICM426XX_INT_CONFIG_INT1_POLARITY_t;
403
404 /*
405 * MPUREG_FIFO_CONFIG
406 * Register Name: FIFO_CONFIG
407 */
408
409 /* FIFO_MODE */
410 #define BIT_FIFO_CONFIG_MODE_POS 6
411 #define BIT_FIFO_CONFIG_MODE_MASK (0x03 << BIT_FIFO_CONFIG_MODE_POS)
412
413 typedef enum {
414 ICM426XX_FIFO_CONFIG_MODE_STOP_ON_FULL = (0x02 << BIT_FIFO_CONFIG_MODE_POS),
415 ICM426XX_FIFO_CONFIG_MODE_STREAM = (0x01 << BIT_FIFO_CONFIG_MODE_POS),
416 ICM426XX_FIFO_CONFIG_MODE_BYPASS = (0x00 << BIT_FIFO_CONFIG_MODE_POS),
417 } ICM426XX_FIFO_CONFIG_MODE_t;
418
419 #define ICM426XX_FIFO_CONFIG_MODE_SNAPSHOT \
420 = ICM426XX_FIFO_CONFIG_MODE_STOP_ON_FULL; // For retro-compatibility
421 /*
422 * MPUREG_INT_STATUS
423 * Register Name: INT_STATUS
424 */
425 #define BIT_INT_STATUS_UI_FSYNC 0x40
426 #define BIT_INT_STATUS_PLL_RDY 0x20
427 #define BIT_INT_STATUS_RESET_DONE 0x10
428 #define BIT_INT_STATUS_DRDY 0x08
429 #define BIT_INT_STATUS_FIFO_THS 0x04
430 #define BIT_INT_STATUS_FIFO_FULL 0x02
431 #define BIT_INT_STATUS_AGC_RDY 0x01
432
433 /*
434 * MPUREG_APEX_DATA0
435 * MPUREG_APEX_DATA1
436 * MPUREG_APEX_DATA2
437 * MPUREG_APEX_DATA3
438 * Register Name: APEX_DATA0
439 * Register Name: APEX_DATA1
440 * Register Name: APEX_DATA2
441 * Register Name: APEX_DATA3
442 */
443
444 /* ACTIVITY_CLASS */
445 #define BIT_APEX_DATA3_ACTIVITY_CLASS_POS 0
446 #define BIT_APEX_DATA3_ACTIVITY_CLASS_MASK 0x03
447
448 typedef enum {
449 ICM426XX_APEX_DATA3_ACTIVITY_CLASS_OTHER = 0x0,
450 ICM426XX_APEX_DATA3_ACTIVITY_CLASS_WALK = 0x1,
451 ICM426XX_APEX_DATA3_ACTIVITY_CLASS_RUN = 0x2,
452 } ICM426XX_APEX_DATA3_ACTIVITY_CLASS_t;
453
454 /* DMP_IDLE */
455 #define BIT_APEX_DATA3_DMP_IDLE_POS 2
456 #define BIT_APEX_DATA3_DMP_IDLE_MASK (0x01 << BIT_APEX_DATA3_DMP_IDLE_POS)
457
458 typedef enum {
459 ICM426XX_APEX_DATA3_DMP_IDLE_ON = (0x01 << BIT_APEX_DATA3_DMP_IDLE_POS),
460 ICM426XX_APEX_DATA3_DMP_IDLE_OFF = (0x00 << BIT_APEX_DATA3_DMP_IDLE_POS),
461 } ICM426XX_APEX_DATA3_DMP_IDLE_OFF_t;
462
463 /*
464 * MPUREG_APEX_DATA4
465 * Register Name: APEX_DATA4
466 */
467
474 /* TAP_NUM */
475 #define BIT_APEX_DATA4_TAP_NUM_POS 3
476 #define BIT_APEX_DATA4_TAP_NUM_MASK (0x03 << BIT_APEX_DATA4_TAP_NUM_POS)
477 typedef enum {
478 ICM426XX_APEX_DATA4_TAP_NUM_DOUBLE = (0x02 << BIT_APEX_DATA4_TAP_NUM_POS),
479 ICM426XX_APEX_DATA4_TAP_NUM_SINGLE = (0x01 << BIT_APEX_DATA4_TAP_NUM_POS),
480 } ICM426XX_APEX_DATA4_TAP_NUM_t;
481
482 /* TAP_AXIS */
483 #define BIT_APEX_DATA4_TAP_AXIS_POS 1
484 #define BIT_APEX_DATA4_TAP_AXIS_MASK (0x03 << BIT_APEX_DATA4_TAP_AXIS_POS)
485 typedef enum {
486 ICM426XX_APEX_DATA4_TAP_AXIS_Z = (0x02 << BIT_APEX_DATA4_TAP_AXIS_POS),
487 ICM426XX_APEX_DATA4_TAP_AXIS_Y = (0x01 << BIT_APEX_DATA4_TAP_AXIS_POS),
488 ICM426XX_APEX_DATA4_TAP_AXIS_X = (0x00 << BIT_APEX_DATA4_TAP_AXIS_POS),
489 } ICM426XX_APEX_DATA4_TAP_AXIS_t;
490
491 /* TAP_DIR */
492 #define BIT_APEX_DATA4_TAP_DIR_POS 0
493 #define BIT_APEX_DATA4_TAP_DIR_MASK 0x01
494 typedef enum {
495 ICM426XX_APEX_DATA4_TAP_DIR_POSITIVE = (0x01 << BIT_APEX_DATA4_TAP_DIR_POS),
496 ICM426XX_APEX_DATA4_TAP_DIR_NEGATIVE = (0x00 << BIT_APEX_DATA4_TAP_DIR_POS),
497 } ICM426XX_APEX_DATA4_TAP_DIR_t;
498
499 /*
500 * MPUREG_APEX_DATA5
501 * Register Name: APEX_DATA5
502 */
503
504 /* DOUBLE_TAP_TIMING */
505 #define BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS 0
506 #define BIT_APEX_DATA5_DOUBLE_TAP_TIMING_MASK (0x3F << BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS)
507
508 /*
509 * MPUREG_INT_STATUS2
510 * Register Name: INT_STATUS2
511 */
512 #define BIT_INT_STATUS2_SMD_INT 0x08
513 #define BIT_INT_STATUS2_WOM_Z_INT 0x04
514 #define BIT_INT_STATUS2_WOM_Y_INT 0x02
515 #define BIT_INT_STATUS2_WOM_X_INT 0x01
516
517 /*
518 * MPUREG_INT_STATUS3
519 * Register Name: INT_STATUS3
520 */
521 #define BIT_INT_STATUS3_STEP_DET 0x20
522 #define BIT_INT_STATUS3_STEP_CNT_OVFL 0x10
523 #define BIT_INT_STATUS3_TILT_DET 0x08
524 #if defined(ICM_FAMILY_BPLUS)
525 #define BIT_INT_STATUS3_WAKE_DET 0x04
526 #define BIT_INT_STATUS3_SLEEP_DET 0x02
527 #elif defined(ICM_FAMILY_CPLUS)
528 #define BIT_INT_STATUS3_LOWG_DET 0x04
529 #define BIT_INT_STATUS3_FF_DET 0x02
530 #endif
531 #define BIT_INT_STATUS3_TAP_DET 0x01
532
533 /*
534 * MPUREG_SIGNAL_PATH_RESET
535 * Register Name: SIGNAL_PATH_RESET
536 */
537
538 /* DMP_INIT_EN */
539 #define BIT_SIGNAL_PATH_RESET_DMP_INIT_POS 6
540 #define BIT_SIGNAL_PATH_RESET_DMP_INIT_MASK (0x01 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS)
541
542 typedef enum {
543 ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_EN = (0x01 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS),
544 ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS),
545 } ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_t;
546
547 /* DMP_MEM_RESET_EN */
548 #define BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS 5
549 #define BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_MASK (0x01 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS)
550
551 typedef enum {
552 ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN = (0x01 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS),
553 ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_DIS =
554 (0x00 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS),
555 } ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_t;
556
557 /* TMST_STROBE */
558 #define BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS 2
559 #define BIT_SIGNAL_PATH_RESET_TMST_STROBE_MASK (0x01 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS)
560
561 typedef enum {
562 ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_EN = (0x01 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS),
563 ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS),
564 } ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_t;
565
566 /* FIFO_FLUSH */
567 #define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS 1
568 #define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_MASK (0x01 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS)
569
570 typedef enum {
571 ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_EN = (0x01 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS),
572 ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS),
573 } ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_t;
574
575 /*
576 * MPUREG_INTF_CONFIG0
577 * Register Name: INTF_CONFIG0
578 */
579
580 /* FIFO_SREG_INVALID_IND */
581 #define BIT_FIFO_SREG_INVALID_IND_POS 7
582 #define BIT_FIFO_SREG_INVALID_IND_MASK (0x01 << BIT_FIFO_SREG_INVALID_IND_POS)
583
584 typedef enum {
585 ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_DIS = (0x01 << BIT_FIFO_SREG_INVALID_IND_POS),
586 ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_EN = (0x00 << BIT_FIFO_SREG_INVALID_IND_POS),
587 } ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t;
588
589 /* FIFO_COUNT_REC */
590 #define BIT_FIFO_COUNT_REC_POS 6
591 #define BIT_FIFO_COUNT_REC_MASK (0x01 << BIT_FIFO_COUNT_REC_POS)
592
593 typedef enum {
594 ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_RECORD = (0x01 << BIT_FIFO_COUNT_REC_POS),
595 ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_BYTE = (0x00 << BIT_FIFO_COUNT_REC_POS),
596 } ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_t;
597
598 /* FIFO_COUNT_ENDIAN */
599 #define BIT_FIFO_COUNT_ENDIAN_POS 5
600 #define BIT_FIFO_COUNT_ENDIAN_MASK (0x01 << BIT_FIFO_COUNT_ENDIAN_POS)
601
602 typedef enum {
603 ICM426XX_INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN = (0x01 << BIT_FIFO_COUNT_ENDIAN_POS),
604 ICM426XX_INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN = (0x00 << BIT_FIFO_COUNT_ENDIAN_POS),
605 } ICM426XX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t;
606
607 /* DATA_ENDIAN */
608 #define BIT_DATA_ENDIAN_POS 4
609 #define BIT_DATA_ENDIAN_MASK (0x01 << BIT_DATA_ENDIAN_POS)
610
611 typedef enum {
612 ICM426XX_INTF_CONFIG0_DATA_BIG_ENDIAN = (0x01 << BIT_DATA_ENDIAN_POS),
613 ICM426XX_INTF_CONFIG0_DATA_LITTLE_ENDIAN = (0x00 << BIT_DATA_ENDIAN_POS),
614 } ICM426XX_INTF_CONFIG0_DATA_ENDIAN_t;
615
616 /* SPI_MODE_OIS2 */
617 #define BIT_SPI_MODE_OIS2_POS 3
618 #define BIT_SPI_MODE_OIS2_MASK (0x01 << BIT_SPI_MODE_OIS2_POS)
619
620 typedef enum {
621 ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_1_2 = (0x01 << BIT_SPI_MODE_OIS2_POS),
622 ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_0_3 = (0x00 << BIT_SPI_MODE_OIS2_POS),
623 } ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_t;
624
625 /* SPI_MODE_AUX1 */
626 #define BIT_SPI_MODE_OIS1_POS 2
627 #define BIT_SPI_MODE_OIS1_MASK (0x01 << BIT_SPI_MODE_OIS1_POS)
628
629 typedef enum {
630 ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_1_2 = (0x01 << BIT_SPI_MODE_OIS1_POS),
631 ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_0_3 = (0x00 << BIT_SPI_MODE_OIS1_POS),
632 } ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_t;
633
634 /*
635 * MPUREG_INTF_CONFIG1
636 * Register Name: INTF_CONFIG1
637 */
638
639 /* ACCEL_LP_CLK_SEL */
640 #define BIT_ACCEL_LP_CLK_SEL_POS 3
641 #define BIT_ACCEL_LP_CLK_SEL_MASK (0x01 << BIT_ACCEL_LP_CLK_SEL_POS)
642
643 typedef enum {
644 ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_WUOSC = (0x00 << BIT_ACCEL_LP_CLK_SEL_POS),
645 ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_RCOSC = (0x01 << BIT_ACCEL_LP_CLK_SEL_POS),
646 } ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_t;
647
648 /* RTC_MODE */
649 #define BIT_RTC_MODE_POS 2
650 #define BIT_RTC_MODE_MASK (0x01 << BIT_RTC_MODE_POS)
651
652 typedef enum {
653 ICM426XX_INTF_CONFIG1_RTC_MODE_DIS = (0x00 << BIT_RTC_MODE_POS),
654 ICM426XX_INTF_CONFIG1_RTC_MODE_EN = (0x01 << BIT_RTC_MODE_POS),
655 } ICM426XX_INTF_CONFIG1_RTC_MODE_t;
656
657 /*
658 * MPUREG_PWR_MGMT_0
659 * Register Name: PWR_MGMT_0
660 */
661
662 /* TEMP_DIS */
663 #define BIT_PWR_MGMT_0_TEMP_POS 5
664 #define BIT_PWR_MGMT_0_TEMP_MASK (0x01 << BIT_PWR_MGMT_0_TEMP_POS)
665
666 typedef enum {
667 ICM426XX_PWR_MGMT_0_TEMP_DIS = (0x01 << BIT_PWR_MGMT_0_TEMP_POS),
668 ICM426XX_PWR_MGMT_0_TEMP_EN = (0x00 << BIT_PWR_MGMT_0_TEMP_POS),
669 } ICM426XX_PWR_MGMT_0_TEMP_t;
670
671 /* IDLE */
672 #define BIT_PWR_MGMT_0_IDLE_POS 4
673 #define BIT_PWR_MGMT_0_IDLE_MASK (0x01 << BIT_PWR_MGMT_0_IDLE_POS)
674
675 typedef enum {
676 ICM426XX_PWR_MGMT_0_IDLE_DIS = (0x01 << BIT_PWR_MGMT_0_IDLE_POS),
677 ICM426XX_PWR_MGMT_0_IDLE_EN = (0x00 << BIT_PWR_MGMT_0_IDLE_POS),
678 } ICM426XX_PWR_MGMT_0_IDLE_t;
679
680 /* GYRO_MODE */
681 #define BIT_PWR_MGMT_0_GYRO_MODE_POS 2
682 #define BIT_PWR_MGMT_0_GYRO_MODE_MASK (0x03 << BIT_PWR_MGMT_0_GYRO_MODE_POS)
683
684 typedef enum {
685 ICM426XX_PWR_MGMT_0_GYRO_MODE_LN = (0x03 << BIT_PWR_MGMT_0_GYRO_MODE_POS),
686 ICM426XX_PWR_MGMT_0_GYRO_MODE_STANDBY = (0x01 << BIT_PWR_MGMT_0_GYRO_MODE_POS),
687 ICM426XX_PWR_MGMT_0_GYRO_MODE_OFF = (0x00 << BIT_PWR_MGMT_0_GYRO_MODE_POS),
688 } ICM426XX_PWR_MGMT_0_GYRO_MODE_t;
689
690 /* ACCEL_MODE */
691 #define BIT_PWR_MGMT_0_ACCEL_MODE_POS 0
692 #define BIT_PWR_MGMT_0_ACCEL_MODE_MASK 0x03
693
694 typedef enum {
695 ICM426XX_PWR_MGMT_0_ACCEL_MODE_LN = 0x03,
696 ICM426XX_PWR_MGMT_0_ACCEL_MODE_LP = 0x02,
697 ICM426XX_PWR_MGMT_0_ACCEL_MODE_OFF = 0x00,
698 } ICM426XX_PWR_MGMT_0_ACCEL_MODE_t;
699
700 /*
701 * MPUREG_GYRO_CONFIG0
702 * Register Name: GYRO_CONFIG0
703 */
704
705 /* GYRO_FS_SEL*/
706 #define BIT_GYRO_CONFIG0_FS_SEL_POS 5
707 #define BIT_GYRO_CONFIG0_FS_SEL_MASK (7 << BIT_GYRO_CONFIG0_FS_SEL_POS)
708
711 typedef enum {
712 #if defined(ICM42686P) || defined(ICM42686V)
713 ICM426XX_GYRO_CONFIG0_FS_SEL_31dps = (7 << BIT_GYRO_CONFIG0_FS_SEL_POS),
714 ICM426XX_GYRO_CONFIG0_FS_SEL_62dps = (6 << BIT_GYRO_CONFIG0_FS_SEL_POS),
715 ICM426XX_GYRO_CONFIG0_FS_SEL_125dps = (5 << BIT_GYRO_CONFIG0_FS_SEL_POS),
716 ICM426XX_GYRO_CONFIG0_FS_SEL_250dps = (4 << BIT_GYRO_CONFIG0_FS_SEL_POS),
717 ICM426XX_GYRO_CONFIG0_FS_SEL_500dps = (3 << BIT_GYRO_CONFIG0_FS_SEL_POS),
718 ICM426XX_GYRO_CONFIG0_FS_SEL_1000dps = (2 << BIT_GYRO_CONFIG0_FS_SEL_POS),
719 ICM426XX_GYRO_CONFIG0_FS_SEL_2000dps = (1 << BIT_GYRO_CONFIG0_FS_SEL_POS),
720 ICM426XX_GYRO_CONFIG0_FS_SEL_4000dps = (0 << BIT_GYRO_CONFIG0_FS_SEL_POS),
721 #else
722 ICM426XX_GYRO_CONFIG0_FS_SEL_16dps = (7 << BIT_GYRO_CONFIG0_FS_SEL_POS),
723 ICM426XX_GYRO_CONFIG0_FS_SEL_31dps = (6 << BIT_GYRO_CONFIG0_FS_SEL_POS),
724 ICM426XX_GYRO_CONFIG0_FS_SEL_62dps = (5 << BIT_GYRO_CONFIG0_FS_SEL_POS),
725 ICM426XX_GYRO_CONFIG0_FS_SEL_125dps = (4 << BIT_GYRO_CONFIG0_FS_SEL_POS),
726 ICM426XX_GYRO_CONFIG0_FS_SEL_250dps = (3 << BIT_GYRO_CONFIG0_FS_SEL_POS),
727 ICM426XX_GYRO_CONFIG0_FS_SEL_500dps = (2 << BIT_GYRO_CONFIG0_FS_SEL_POS),
728 ICM426XX_GYRO_CONFIG0_FS_SEL_1000dps = (1 << BIT_GYRO_CONFIG0_FS_SEL_POS),
729 ICM426XX_GYRO_CONFIG0_FS_SEL_2000dps = (0 << BIT_GYRO_CONFIG0_FS_SEL_POS),
730 #endif
731 } ICM426XX_GYRO_CONFIG0_FS_SEL_t;
732
733 /* GYRO_ODR */
734 #define BIT_GYRO_CONFIG0_ODR_POS 0
735 #define BIT_GYRO_CONFIG0_ODR_MASK 0x0F
736
739 typedef enum {
740 ICM426XX_GYRO_CONFIG0_ODR_500_HZ = 0x0F,
741 ICM426XX_GYRO_CONFIG0_ODR_12_5_HZ = 0x0B,
742 ICM426XX_GYRO_CONFIG0_ODR_25_HZ = 0x0A,
743 ICM426XX_GYRO_CONFIG0_ODR_50_HZ = 0x09,
744 ICM426XX_GYRO_CONFIG0_ODR_100_HZ = 0x08,
745 ICM426XX_GYRO_CONFIG0_ODR_200_HZ = 0x07,
746 ICM426XX_GYRO_CONFIG0_ODR_1_KHZ = 0x06,
747 ICM426XX_GYRO_CONFIG0_ODR_2_KHZ = 0x05,
748 ICM426XX_GYRO_CONFIG0_ODR_4_KHZ = 0x04,
749 ICM426XX_GYRO_CONFIG0_ODR_8_KHZ = 0x03,
750 ICM426XX_GYRO_CONFIG0_ODR_16_KHZ = 0x02,
751 ICM426XX_GYRO_CONFIG0_ODR_32_KHZ = 0x01,
752 } ICM426XX_GYRO_CONFIG0_ODR_t;
753
754 /*
755 * MPUREG_ACCEL_CONFIG0
756 * Register Name: ACCEL_CONFIG0
757 */
758
759 /* ACCEL_FS_SEL */
760 #define BIT_ACCEL_CONFIG0_FS_SEL_POS 5
761 #define BIT_ACCEL_CONFIG0_FS_SEL_MASK (0x7 << BIT_ACCEL_CONFIG0_FS_SEL_POS)
762
765 typedef enum {
766 #if defined(ICM42686P) || defined(ICM42686V)
767 ICM426XX_ACCEL_CONFIG0_FS_SEL_2g = (0x4 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
768 ICM426XX_ACCEL_CONFIG0_FS_SEL_4g = (0x3 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
769 ICM426XX_ACCEL_CONFIG0_FS_SEL_8g = (0x2 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
770 ICM426XX_ACCEL_CONFIG0_FS_SEL_16g = (0x1 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
771 ICM426XX_ACCEL_CONFIG0_FS_SEL_32g = (0x0 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
772 #else
773 ICM426XX_ACCEL_CONFIG0_FS_SEL_RESERVED = (0x4 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
774 ICM426XX_ACCEL_CONFIG0_FS_SEL_2g = (0x3 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
775 ICM426XX_ACCEL_CONFIG0_FS_SEL_4g = (0x2 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
776 ICM426XX_ACCEL_CONFIG0_FS_SEL_8g = (0x1 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
777 ICM426XX_ACCEL_CONFIG0_FS_SEL_16g = (0x0 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
778 #endif
779 } ICM426XX_ACCEL_CONFIG0_FS_SEL_t;
780
781 /* ACCEL_ODR */
782 #define BIT_ACCEL_CONFIG0_ODR_POS 0
783 #define BIT_ACCEL_CONFIG0_ODR_MASK 0x0F
784
787 typedef enum {
788 ICM426XX_ACCEL_CONFIG0_ODR_500_HZ = 0xF,
789 ICM426XX_ACCEL_CONFIG0_ODR_1_5625_HZ = 0xE,
790 ICM426XX_ACCEL_CONFIG0_ODR_3_125_HZ = 0xD,
791 ICM426XX_ACCEL_CONFIG0_ODR_6_25_HZ = 0xC,
792 ICM426XX_ACCEL_CONFIG0_ODR_12_5_HZ = 0xB,
793 ICM426XX_ACCEL_CONFIG0_ODR_25_HZ = 0xA,
794 ICM426XX_ACCEL_CONFIG0_ODR_50_HZ = 0x9,
795 ICM426XX_ACCEL_CONFIG0_ODR_100_HZ = 0x8,
796 ICM426XX_ACCEL_CONFIG0_ODR_200_HZ = 0x7,
797 ICM426XX_ACCEL_CONFIG0_ODR_1_KHZ = 0x6,
798 ICM426XX_ACCEL_CONFIG0_ODR_2_KHZ = 0x5,
799 ICM426XX_ACCEL_CONFIG0_ODR_4_KHZ = 0x4,
800 ICM426XX_ACCEL_CONFIG0_ODR_8_KHZ = 0x3,
801 ICM426XX_ACCEL_CONFIG0_ODR_16_KHZ = 0x2,
802 ICM426XX_ACCEL_CONFIG0_ODR_32_KHZ = 0x1,
803 } ICM426XX_ACCEL_CONFIG0_ODR_t;
804
805 /*
806 * MPUREG_GYRO_CONFIG1
807 * Register Name: GYRO_CONFIG1
808 */
809
810 /* TEMP_FILT_BW */
811 #define BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS 5
812 #define BIT_GYRO_CONFIG1_TEMP_FILT_BW_MASK (0x7 << BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS)
813
814 /* GYRO_UI_FILT_ORD */
815 #define BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS 2
816 #define BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_MASK (0x3 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS)
817
818 typedef enum {
819 ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_1ST_ORDER =
820 (0x0 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS),
821 ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_2ND_ORDER =
822 (0x1 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS),
823 ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_3RD_ORDER =
824 (0x2 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS),
825 } ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_t;
826
827 /* GYRO_DEC2_M2_ORD */
828 #define BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_POS 0
829 #define BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_MASK 0x3
830
831 /*
832 * MPUREG_ACCEL_GYRO_CONFIG0
833 * Register Name: GYRO_ACCEL_CONFIG0
834 */
835
836 /* ACCEL_UI_FILT_BW_IND */
837 #define BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS 4
838 #define BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_MASK (0xF << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS)
839
840 typedef enum {
841 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_40 = (0x7 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
842 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_20 = (0x6 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
843 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_16 = (0x5 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
844 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_10 = (0x4 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
845 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_8 = (0x3 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
846 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_5 = (0x2 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
847 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_4 = (0x1 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
848 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_2 = (0x0 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
849 } ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t;
850
851 typedef enum {
852 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_16 = (0x6 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
853 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_1 = (0x1 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
854 } ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t;
855
856 /* GYRO_UI_FILT_BW_IND */
857 #define BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_POS 0
858 #define BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_MASK 0x0F
859
860 typedef enum {
861 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_40 = 0x07,
862 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_20 = 0x06,
863 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_16 = 0x05,
864 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_10 = 0x04,
865 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_8 = 0x03,
866 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_5 = 0x02,
867 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_4 = 0x01,
868 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_2 = 0x00,
869 } ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t;
870
871 /*
872 * MPUREG_ACCEL_CONFIG1
873 * Register Name: ACCEL_CONFIG1
874 */
875
876 /* ACCEL_UI_FILT_ORD */
877 #define BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS 3
878 #define BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS)
879
880 typedef enum {
881 ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_1ST_ORDER =
882 (0x0 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS),
883 ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_2ND_ORDER =
884 (0x1 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS),
885 ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_3RD_ORDER =
886 (0x2 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS),
887 } ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_t;
888
889 /* ACCEL_DEC2_M2_ORD */
890 #define BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS 1
891 #define BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS)
892
893 /*
894 * MPUREG_TMST_CONFIG
895 * Register Name: TMST_CONFIG
896 */
897
898 /* TMST_TO_REGS */
899 #define BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS 4
900 #define BIT_TMST_CONFIG_TMST_TO_REGS_EN_MASK (0x1 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS)
901
902 typedef enum {
903 ICM426XX_TMST_CONFIG_TMST_TO_REGS_EN = (0x1 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS),
904 ICM426XX_TMST_CONFIG_TMST_TO_REGS_DIS = (0x0 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS),
905 } ICM426XX_TMST_CONFIG_TMST_TO_REGS_EN_t;
906
907 /* TMST_RES */
908 #define BIT_TMST_CONFIG_RESOL_POS 3
909 #define BIT_TMST_CONFIG_RESOL_MASK (0x1 << BIT_TMST_CONFIG_RESOL_POS)
910
911 typedef enum {
912 ICM426XX_TMST_CONFIG_RESOL_16us = (0x01 << BIT_TMST_CONFIG_RESOL_POS),
913 ICM426XX_TMST_CONFIG_RESOL_1us = (0x00 << BIT_TMST_CONFIG_RESOL_POS),
914 } ICM426XX_TMST_CONFIG_RESOL_t;
915
916 /* TMST_FSYNC */
917 #define BIT_TMST_CONFIG_TMST_FSYNC_POS 1
918 #define BIT_TMST_CONFIG_TMST_FSYNC_MASK (0x1 << BIT_TMST_CONFIG_TMST_FSYNC_POS)
919
920 typedef enum {
921 ICM426XX_TMST_CONFIG_TMST_FSYNC_EN = (0x01 << BIT_TMST_CONFIG_TMST_FSYNC_POS),
922 ICM426XX_TMST_CONFIG_TMST_FSYNC_DIS = (0x00 << BIT_TMST_CONFIG_TMST_FSYNC_POS),
923 } ICM426XX_TMST_CONFIG_TMST_FSYNC_EN_t;
924
925 /* TMST_EN */
926 #define BIT_TMST_CONFIG_TMST_EN_POS 0
927 #define BIT_TMST_CONFIG_TMST_EN_MASK 0x1
928
929 typedef enum {
930 ICM426XX_TMST_CONFIG_TMST_EN = 0x01,
931 ICM426XX_TMST_CONFIG_TMST_DIS = 0x00,
932 } ICM426XX_TMST_CONFIG_TMST_EN_t;
933
934 /*
935 * MPUREG_APEX_CONFIG0
936 * Register Name: APEX_CONFIG0
937 */
938
939 /* DMP_POWER_SAVE_EN */
940 #define BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS 7
941 #define BIT_APEX_CONFIG0_DMP_POWER_SAVE_MASK (0x1 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS)
942
943 typedef enum {
944 ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_EN = (0x1 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS),
945 ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_DIS = (0x0 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS),
946 } ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_t;
947
948 /* TAP_ENABLE */
949 #define BIT_APEX_CONFIG0_TAP_ENABLE_POS 6
950 #define BIT_APEX_CONFIG0_TAP_ENABLE_MASK (0x1 << BIT_APEX_CONFIG0_TAP_ENABLE_POS)
951
952 typedef enum {
953 ICM426XX_APEX_CONFIG0_TAP_ENABLE_EN = (0x1 << BIT_APEX_CONFIG0_TAP_ENABLE_POS),
954 ICM426XX_APEX_CONFIG0_TAP_ENABLE_DIS = (0x0 << BIT_APEX_CONFIG0_TAP_ENABLE_POS),
955 } ICM426XX_APEX_CONFIG0_TAP_ENABLE_t;
956
957 /* PEDO_EN */
958 #define BIT_APEX_CONFIG0_PEDO_EN_POS 5
959 #define BIT_APEX_CONFIG0_PEDO_EN_MASK (0x1 << BIT_APEX_CONFIG0_PEDO_EN_POS)
960
961 typedef enum {
962 ICM426XX_APEX_CONFIG0_PEDO_EN_EN = (0x1 << BIT_APEX_CONFIG0_PEDO_EN_POS),
963 ICM426XX_APEX_CONFIG0_PEDO_EN_DIS = (0x0 << BIT_APEX_CONFIG0_PEDO_EN_POS),
964 } ICM426XX_APEX_CONFIG0_PEDO_EN_t;
965
966 #if defined(ICM_FAMILY_BPLUS)
967
968 /* R2W_EN */
969 #define BIT_APEX_CONFIG0_R2W_EN_POS 3
970 #define BIT_APEX_CONFIG0_R2W_EN_MASK (0x1 << BIT_APEX_CONFIG0_R2W_EN_POS)
971
972 typedef enum {
973 ICM426XX_APEX_CONFIG0_R2W_EN_EN = (0x1 << BIT_APEX_CONFIG0_R2W_EN_POS),
974 ICM426XX_APEX_CONFIG0_R2W_EN_DIS = (0x0 << BIT_APEX_CONFIG0_R2W_EN_POS),
975 } ICM426XX_APEX_CONFIG0_R2W_EN_t;
976
977 #elif defined(ICM_FAMILY_CPLUS)
978
979 /* FF_EN */
980 #define BIT_APEX_CONFIG0_FF_EN_POS 2
981 #define BIT_APEX_CONFIG0_FF_EN_MASK (0x1 << BIT_APEX_CONFIG0_FF_EN_POS)
982
983 typedef enum {
984 ICM426XX_APEX_CONFIG0_FF_EN_EN = (0x1 << BIT_APEX_CONFIG0_FF_EN_POS),
985 ICM426XX_APEX_CONFIG0_FF_EN_DIS = (0x0 << BIT_APEX_CONFIG0_FF_EN_POS),
986 } ICM426XX_APEX_CONFIG0_FF_EN_t;
987
988 /* LOWG_EN */
989 #define BIT_APEX_CONFIG0_LOWG_EN_POS 3
990 #define BIT_APEX_CONFIG0_LOWG_EN_MASK (0x1 << BIT_APEX_CONFIG0_LOWG_EN_POS)
991
992 typedef enum {
993 ICM426XX_APEX_CONFIG0_LOWG_EN_EN = (0x1 << BIT_APEX_CONFIG0_LOWG_EN_POS),
994 ICM426XX_APEX_CONFIG0_LOWG_EN_DIS = (0x0 << BIT_APEX_CONFIG0_LOWG_EN_POS),
995 } ICM426XX_APEX_CONFIG0_LOWG_EN_t;
996
997 #endif
998
999 /* TILT_EN */
1000 #define BIT_APEX_CONFIG0_TILT_EN_POS 4
1001 #define BIT_APEX_CONFIG0_TILT_EN_MASK (0x1 << BIT_APEX_CONFIG0_TILT_EN_POS)
1002
1003 typedef enum {
1004 ICM426XX_APEX_CONFIG0_TILT_EN_EN = (0x1 << BIT_APEX_CONFIG0_TILT_EN_POS),
1005 ICM426XX_APEX_CONFIG0_TILT_EN_DIS = (0x0 << BIT_APEX_CONFIG0_TILT_EN_POS),
1006 } ICM426XX_APEX_CONFIG0_TILT_EN_t;
1007
1008 /* DMP_ODR */
1009 #define BIT_APEX_CONFIG0_DMP_ODR_POS 0
1010 #define BIT_APEX_CONFIG0_DMP_ODR_MASK (0x3 << BIT_APEX_CONFIG0_DMP_ODR_POS)
1011
1014 typedef enum {
1015 ICM426XX_APEX_CONFIG0_DMP_ODR_25Hz = (0x0 << BIT_APEX_CONFIG0_DMP_ODR_POS),
1016 ICM426XX_APEX_CONFIG0_DMP_ODR_50Hz = (0x2 << BIT_APEX_CONFIG0_DMP_ODR_POS),
1017 ICM426XX_APEX_CONFIG0_DMP_ODR_100Hz =
1018 (0x3 << BIT_APEX_CONFIG0_DMP_ODR_POS),
1019 ICM426XX_APEX_CONFIG0_DMP_ODR_500Hz =
1020 (0x1 << BIT_APEX_CONFIG0_DMP_ODR_POS),
1021 } ICM426XX_APEX_CONFIG0_DMP_ODR_t;
1022
1023 /*
1024 * MPUREG_SMD_CONFIG
1025 * Register Name: SMD_CONFIG
1026 */
1027
1028 /* WOM_INT_MODE */
1029 #define BIT_SMD_CONFIG_WOM_INT_MODE_POS 3
1030 #define BIT_SMD_CONFIG_WOM_INT_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_INT_MODE_POS)
1031
1032 typedef enum {
1033 ICM426XX_SMD_CONFIG_WOM_INT_MODE_ANDED = (0x01 << BIT_SMD_CONFIG_WOM_INT_MODE_POS),
1034 ICM426XX_SMD_CONFIG_WOM_INT_MODE_ORED = (0x00 << BIT_SMD_CONFIG_WOM_INT_MODE_POS),
1035 } ICM426XX_SMD_CONFIG_WOM_INT_MODE_t;
1036
1037 /* WOM_MODE */
1038 #define BIT_SMD_CONFIG_WOM_MODE_POS 2
1039 #define BIT_SMD_CONFIG_WOM_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_MODE_POS)
1040
1041 typedef enum {
1042 ICM426XX_SMD_CONFIG_WOM_MODE_CMP_PREV = (0x01 << BIT_SMD_CONFIG_WOM_MODE_POS),
1043 ICM426XX_SMD_CONFIG_WOM_MODE_CMP_INIT = (0x00 << BIT_SMD_CONFIG_WOM_MODE_POS),
1044 } ICM426XX_SMD_CONFIG_WOM_MODE_t;
1045
1046 /* SMD_MODE */
1047 #define BIT_SMD_CONFIG_SMD_MODE_POS 0
1048 #define BIT_SMD_CONFIG_SMD_MODE_MASK 0x3
1049
1050 typedef enum {
1051 ICM426XX_SMD_CONFIG_SMD_MODE_LONG = 0x03,
1052 ICM426XX_SMD_CONFIG_SMD_MODE_SHORT = 0x02,
1053 ICM426XX_SMD_CONFIG_SMD_MODE_WOM = 0x01,
1054 ICM426XX_SMD_CONFIG_SMD_MODE_DISABLED = 0x00,
1055 } ICM426XX_SMD_CONFIG_SMD_MODE_t;
1056
1057 /*
1058 * MPUREG_FIFO_CONFIG1
1059 * Register Name: FIFO_CONFIG1
1060 */
1061 #define BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS 6
1062 #define BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_MASK (0x1 << BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS)
1063
1064 /* FIFO_WM_GT_TH */
1065 #define BIT_FIFO_CONFIG1_WM_GT_TH_POS 5
1066 #define BIT_FIFO_CONFIG1_WM_GT_TH_MASK (0x1 << BIT_FIFO_CONFIG1_WM_GT_TH_POS)
1067
1068 typedef enum {
1069 ICM426XX_FIFO_CONFIG1_WM_GT_TH_EN = (0x1 << BIT_FIFO_CONFIG1_WM_GT_TH_POS),
1070 ICM426XX_FIFO_CONFIG1_WM_GT_TH_DIS = (0x0 << BIT_FIFO_CONFIG1_WM_GT_TH_POS),
1071 } ICM426XX_FIFO_CONFIG1_WM_GT_t;
1072
1073 /* FIFO_HIRES_EN */
1074 #define BIT_FIFO_CONFIG1_HIRES_POS 4
1075 #define BIT_FIFO_CONFIG1_HIRES_MASK (0x1 << BIT_FIFO_CONFIG1_HIRES_POS)
1076
1077 typedef enum {
1078 ICM426XX_FIFO_CONFIG1_HIRES_EN = (0x1 << BIT_FIFO_CONFIG1_HIRES_POS),
1079 ICM426XX_FIFO_CONFIG1_HIRES_DIS = (0x0 << BIT_FIFO_CONFIG1_HIRES_POS),
1080 } ICM426XX_FIFO_CONFIG1_HIRES_t;
1081
1082 /* FIFO_TMST_FSYNC_EN */
1083 #define BIT_FIFO_CONFIG1_TMST_FSYNC_POS 3
1084 #define BIT_FIFO_CONFIG1_TMST_FSYNC_MASK (0x1 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS)
1085
1086 typedef enum {
1087 ICM426XX_FIFO_CONFIG1_TMST_FSYNC_EN = (0x1 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS),
1088 ICM426XX_FIFO_CONFIG1_TMST_FSYNC_DIS = (0x0 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS),
1089 } ICM426XX_FIFO_CONFIG1_TMST_FSYNC_t;
1090
1091 /* FIFO_TEMP_EN */
1092 #define BIT_FIFO_CONFIG1_TEMP_POS 2
1093 #define BIT_FIFO_CONFIG1_TEMP_MASK (0x1 << BIT_FIFO_CONFIG1_TEMP_POS)
1094
1095 typedef enum {
1096 ICM426XX_FIFO_CONFIG1_TEMP_EN = (0x1 << BIT_FIFO_CONFIG1_TEMP_POS),
1097 ICM426XX_FIFO_CONFIG1_TEMP_DIS = (0x0 << BIT_FIFO_CONFIG1_TEMP_POS),
1098 } ICM426XX_FIFO_CONFIG1_TEMP_t;
1099
1100 /* FIFO_GYRO_EN */
1101 #define BIT_FIFO_CONFIG1_GYRO_POS 1
1102 #define BIT_FIFO_CONFIG1_GYRO_MASK (0x1 << BIT_FIFO_CONFIG1_GYRO_POS)
1103
1104 typedef enum {
1105 ICM426XX_FIFO_CONFIG1_GYRO_EN = (0x1 << BIT_FIFO_CONFIG1_GYRO_POS),
1106 ICM426XX_FIFO_CONFIG1_GYRO_DIS = (0x0 << BIT_FIFO_CONFIG1_GYRO_POS),
1107 } ICM426XX_FIFO_CONFIG1_GYRO_t;
1108
1109 /* FIFO_ACCEL_EN*/
1110 #define BIT_FIFO_CONFIG1_ACCEL_POS 0
1111 #define BIT_FIFO_CONFIG1_ACCEL_MASK 0x1
1112
1113 typedef enum {
1114 ICM426XX_FIFO_CONFIG1_ACCEL_EN = 0x01,
1115 ICM426XX_FIFO_CONFIG1_ACCEL_DIS = 0x00,
1116 } ICM426XX_FIFO_CONFIG1_ACCEL_t;
1117
1118 /*
1119 * MPUREG_FSYNC_CONFIG
1120 * Register Name: FSYNC_CONFIG
1121 */
1122
1123 /* FSYNC_UI_SEL */
1124 #define BIT_FSYNC_CONFIG_UI_SEL_POS 4
1125 #define BIT_FSYNC_CONFIG_UI_SEL_MASK (0x7 << BIT_FSYNC_CONFIG_UI_SEL_POS)
1126
1127 typedef enum {
1128 ICM426XX_FSYNC_CONFIG_UI_SEL_NO = (0x0 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1129 ICM426XX_FSYNC_CONFIG_UI_SEL_TEMP = (0x1 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1130 ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_X = (0x2 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1131 ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_Y = (0x3 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1132 ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_Z = (0x4 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1133 ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_X = (0x5 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1134 ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_Y = (0x6 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1135 ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_Z = (0x7 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1136 } ICM426XX_FSYNC_CONFIG_UI_SEL_t;
1137
1138 /*
1139 * MPUREG_INT_CONFIG1
1140 * Register Name: INT_CONFIG1
1141 */
1142
1143 /* INT_TPULSE_DURATION */
1144 #define BIT_INT_TPULSE_DURATION_POS 6
1145 #define BIT_INT_TPULSE_DURATION_MASK (0x1 << BIT_INT_TPULSE_DURATION_POS)
1146
1147 typedef enum {
1148 ICM426XX_INT_TPULSE_DURATION_8_US = (0x1 << BIT_INT_TPULSE_DURATION_POS),
1149 ICM426XX_INT_TPULSE_DURATION_100_US = (0x0 << BIT_INT_TPULSE_DURATION_POS),
1150 } ICM426XX_INT_TPULSE_DURATION_t;
1151
1152 /* INT_TDEASSERT_DISABLE */
1153 #define BIT_INT_TDEASSERT_POS 5
1154 #define BIT_INT_TDEASSERT_MASK (0x1 << BIT_INT_TDEASSERT_POS)
1155
1156 typedef enum {
1157 ICM426XX_INT_TDEASSERT_DISABLED = (0x1 << BIT_INT_TDEASSERT_POS),
1158 ICM426XX_INT_TDEASSERT_ENABLED = (0x0 << BIT_INT_TDEASSERT_POS),
1159 } ICM426XX_INT_TDEASSERT_t;
1160
1161 /* ASY_RESET_DISABLE */
1162 #define BIT_INT_CONFIG1_ASY_RST_POS 4
1163 #define BIT_INT_CONFIG1_ASY_RST_MASK (0x1 << BIT_INT_CONFIG1_ASY_RST_POS)
1164
1165 typedef enum {
1166 ICM426XX_INT_CONFIG1_ASY_RST_DISABLED = (0x1 << BIT_INT_CONFIG1_ASY_RST_POS),
1167 ICM426XX_INT_CONFIG1_ASY_RST_ENABLED = (0x0 << BIT_INT_CONFIG1_ASY_RST_POS),
1168 } ICM426XX_INT_CONFIG1_ASY_RST_t;
1169
1170 /*
1171 * MPUREG_INT_SOURCE0
1172 * Register Name: INT_SOURCE0
1173 */
1174 #define BIT_INT_UI_FSYNC_INT_EN_POS 6
1175 #define BIT_INT_PLL_RDY_INT_EN_POS 5
1176 #define BIT_INT_RESET_DONE_INT_EN_POS 4
1177 #define BIT_INT_UI_DRDY_INT_EN_POS 3
1178 #define BIT_INT_FIFO_THS_INT_EN_POS 2
1179 #define BIT_INT_FIFO_FULL_INT_EN_POS 1
1180 #define BIT_INT_UI_AGC_RDY_INT_EN_POS 0
1181
1182 #define BIT_INT_SOURCE0_UI_FSYNC_INT1_EN 0x40
1183 #define BIT_INT_SOURCE0_PLL_RDY_INT1_EN 0x20
1184 #define BIT_INT_SOURCE0_RESET_DONE_INT1_EN 0x10
1185 #define BIT_INT_SOURCE0_UI_DRDY_INT1_EN 0x08
1186 #define BIT_INT_SOURCE0_FIFO_THS_INT1_EN 0x04
1187 #define BIT_INT_SOURCE0_FIFO_FULL_INT1_EN 0x02
1188 #define BIT_INT_SOURCE0_UI_AGC_RDY_INT1_EN 0x01
1189
1190 /*
1191 * MPUREG_INT_SOURCE1
1192 * Register Name: INT_SOURCE1
1193 */
1194 #define BIT_INT_SMD_INT_EN_POS 3
1195 #define BIT_INT_WOM_Z_INT_EN_POS 2
1196 #define BIT_INT_WOM_Y_INT_EN_POS 1
1197 #define BIT_INT_WOM_X_INT_EN_POS 0
1198
1199 #define BIT_INT_SOURCE1_SMD_INT1_EN 0x08
1200 #define BIT_INT_SOURCE1_WOM_Z_INT1_EN 0x04
1201 #define BIT_INT_SOURCE1_WOM_Y_INT1_EN 0x02
1202 #define BIT_INT_SOURCE1_WOM_X_INT1_EN 0x01
1203
1204 /*
1205 * MPUREG_INT_SOURCE2
1206 * Register Name: INT_SOURCE2
1207 */
1208 #define BIT_INT_SOURCE2_OIS2_AGC_RDY_INT1_EN 0x20
1209 #define BIT_INT_SOURCE2_OIS2_FSYNC_INT1_EN 0x10
1210 #define BIT_INT_SOURCE2_OIS2_DRDY_INT1_EN 0x08
1211 #define BIT_INT_SOURCE2_OIS1_AGC_RDY_INT1_EN 0x04
1212 #define BIT_INT_SOURCE2_OIS1_FSYNC_INT1_EN 0x02
1213 #define BIT_INT_SOURCE2_OIS1_DRDY_INT1_EN 0x01
1214
1215 /*
1216 * MPUREG_INT_SOURCE3
1217 * Register Name: INT_SOURCE3
1218 */
1219 #define BIT_INT_SOURCE3_UI_FSYNC_INT2_EN 0x40
1220 #define BIT_INT_SOURCE3_PLL_RDY_INT2_EN 0x20
1221 #define BIT_INT_SOURCE3_RESET_DONE_INT2_EN 0x10
1222 #define BIT_INT_SOURCE3_UI_DRDY_INT2_EN 0x08
1223 #define BIT_INT_SOURCE3_FIFO_THS_INT2_EN 0x04
1224 #define BIT_INT_SOURCE3_FIFO_FULL_INT2_EN 0x02
1225 #define BIT_INT_SOURCE3_UI_AGC_RDY_INT2_EN 0x01
1226
1227 /*
1228 * MPUREG_INT_SOURCE4
1229 * Register Name: INT_SOURCE4
1230 */
1231 #define BIT_INT_SOURCE4_SMD_INT2_EN 0x08
1232 #define BIT_INT_SOURCE4_WOM_Z_INT2_EN 0x04
1233 #define BIT_INT_SOURCE4_WOM_Y_INT2_EN 0x02
1234 #define BIT_INT_SOURCE4_WOM_X_INT2_EN 0x01
1235
1236 /*
1237 * MPUREG_INT_SOURCE5
1238 * Register Name: INT_SOURCE5
1239 */
1240 #define BIT_INT_SOURCE5_OIS2_AGC_RDY_INT2_EN 0x20
1241 #define BIT_INT_SOURCE5_OIS2_FSYNC_INT2_EN 0x10
1242 #define BIT_INT_SOURCE5_OIS2_DRDY_INT2_EN 0x08
1243 #define BIT_INT_SOURCE5_OIS1_AGC_RDY_INT2_EN 0x04
1244 #define BIT_INT_SOURCE5_OIS1_FSYNC_INT2_EN 0x02
1245 #define BIT_INT_SOURCE5_OIS1_DRDY_INT2_EN 0x01
1246
1247 /*
1248 * MPUREG_SELF_TEST_CONFIG
1249 * Register Name: SELF_TEST_CONFIG
1250 */
1251 #define BIT_ST_REGULATOR_EN 0x40
1252 #define BIT_ACCEL_Z_ST_EN 0x20
1253 #define BIT_ACCEL_Y_ST_EN 0x10
1254 #define BIT_ACCEL_X_ST_EN 0x08
1255 #define BIT_GYRO_Z_ST_EN 0x04
1256 #define BIT_GYRO_Y_ST_EN 0x02
1257 #define BIT_GYRO_X_ST_EN 0x01
1258
1259 /*
1260 * MPUREG_SCAN0
1261 * Register Name: SCAN0
1262 */
1263 #define BIT_DMP_MEM_ACCESS_EN 0x08
1264 #define BIT_MEM_OTP_ACCESS_EN 0x04
1265 #define BIT_FIFO_MEM_RD_SYS 0x02
1266 #define BIT_FIFO_MEM_WR_SER 0x01
1267
1268 /* ----------------------------------------------------------------------------
1269 * Register bank 1
1270 * ---------------------------------------------------------------------------- */
1271
1272 #define BIT_SENSOR_CONFIG2_OIS_MODE_POS 4
1273 #define BIT_SENSOR_CONFIG2_OIS_MODE_MASK (0x03 << BIT_SENSOR_CONFIG2_OIS_MODE_POS)
1274
1275 typedef enum {
1276 ICM426XX_SENSOR_CONFIG2_OIS_MODE_32KHZ = (0x2 << BIT_SENSOR_CONFIG2_OIS_MODE_POS),
1277 ICM426XX_SENSOR_CONFIG2_OIS_MODE_8KHZ = (0x1 << BIT_SENSOR_CONFIG2_OIS_MODE_POS),
1278 ICM426XX_SENSOR_CONFIG2_OIS_MODE_DIS = (0x0 << BIT_SENSOR_CONFIG2_OIS_MODE_POS)
1279 } ICM426XX_SENSOR_CONFIG2_OIS_MODE_t;
1280
1281 /*
1282 * MPUREG_GYRO_CONFIG_STATIC2_B1
1283 * Register Name: GYRO_CONFIG_STATIC2
1284 */
1285
1286 /* GYRO_AAF_DIS */
1287 #define BIT_GYRO_AAF_DIS_POS 1
1288 #define BIT_GYRO_AAF_DIS_MASK (0x01 << BIT_GYRO_AAF_DIS_POS)
1289
1290 typedef enum {
1291 ICM426XX_GYRO_AAF_EN = (0x0 << BIT_GYRO_AAF_DIS_POS),
1292 ICM426XX_GYRO_AAF_DIS = (0x1 << BIT_GYRO_AAF_DIS_POS),
1293 } ICM426XX_GYRO_AAF_DIS_t;
1294
1295 /* GYRO_NF_DIS */
1296 #define BIT_GYRO_NF_DIS_POS 0
1297 #define BIT_GYRO_NF_DIS_MASK (0x01 << BIT_GYRO_NF_DIS_POS)
1298 typedef enum {
1299 ICM426XX_GYRO_NF_EN = (0x0 << BIT_GYRO_NF_DIS_POS),
1300 ICM426XX_GYRO_NF_DIS = (0x1 << BIT_GYRO_NF_DIS_POS),
1301 } ICM426XX_GYRO_NF_DIS_t;
1302
1303 /*
1304 * MPUREG_GYRO_CONFIG_STATIC3_B1
1305 * Register Name: GYRO_CONFIG_STATIC3
1306 */
1307
1308 /* GYRO_AAF_DELT */
1309 #define BIT_GYRO_AAF_DELT_POS 0
1310 #define BIT_GYRO_AAF_DELT_MASK (0x3F << BIT_GYRO_AAF_DELT_POS)
1311
1312 /*
1313 * MPUREG_GYRO_CONFIG_STATIC4_B1
1314 * Register Name: GYRO_CONFIG_STATIC4
1315 */
1316
1317 /* GYRO_AAF_DELTSQR */
1318 #define BIT_GYRO_AAF_DELTSQR_POS_LO 0
1319 #define BIT_GYRO_AAF_DELTSQR_MASK_LO (0xFF << BIT_GYRO_AAF_DELTSQR_POS_LO)
1320
1321 /*
1322 * MPUREG_GYRO_CONFIG_STATIC5_B1
1323 * Register Name: GYRO_CONFIG_STATIC5
1324 */
1325
1326 #define BIT_GYRO_AAF_DELTSQR_POS_HI 0
1327 #define BIT_GYRO_AAF_DELTSQR_MASK_HI (0x0F << BIT_GYRO_AAF_DELTSQR_POS_HI)
1328
1329 /* GYRO_AAF_BITSHIFT */
1330 #define BIT_GYRO_AAF_BITSHIFT_POS 4
1331 #define BIT_GYRO_AAF_BITSHIFT_MASK (0x0F << BIT_GYRO_AAF_BITSHIFT_POS)
1332
1333 /*
1334 * MPUREG_INTF_CONFIG4_B1
1335 * Register Name: INTF_CONFIG4
1336 */
1337
1338 /* SPI_AP_4WIRE */
1339 #define BIT_INTF_CONFIG4_AP_SPI_POS 1
1340 #define BIT_INTF_CONFIG4_AP_SPI_MASK (0x1 << BIT_INTF_CONFIG4_AP_SPI_POS)
1341
1342 typedef enum {
1343 ICM426XX_INTF_CONFIG4_AP_SPI4W = (0x1 << BIT_INTF_CONFIG4_AP_SPI_POS),
1344 ICM426XX_INTF_CONFIG4_AP_SPI3W = (0x0 << BIT_INTF_CONFIG4_AP_SPI_POS),
1345 } ICM426XX_INTF_CONFIG4_AP_SPI_t;
1346
1347 /* SPI_AUX1_4WIRE */
1348 #define BIT_INTF_CONFIG4_AUX1_SPI_POS 2
1349 #define BIT_INTF_CONFIG4_AUX1_SPI_MASK (0x1 << BIT_INTF_CONFIG4_AUX1_SPI_POS)
1350
1351 typedef enum {
1352 ICM426XX_INTF_CONFIG4_AUX1_SPI4W = (0x1 << BIT_INTF_CONFIG4_AUX1_SPI_POS),
1353 ICM426XX_INTF_CONFIG4_AUX1_SPI3W = (0x0 << BIT_INTF_CONFIG4_AUX1_SPI_POS),
1354 } ICM426XX_INTF_CONFIG4_AUX1_SPI_t;
1355
1356 /*
1357 * MPUREG_INTF_CONFIG5_B1
1358 * Register Name: INTF_CONFIG5
1359 */
1360
1361 /* GPIO_PAD_SEL */
1362 #define BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS 1
1363 #define BIT_INTF_CONFIG5_GPIO_PAD_SEL_MASK (0x3 << BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS)
1364
1365 /*
1366 * MPUREG_INTF_CONFIG6_B1
1367 * Register Name: INTF_CONFIG6
1368 */
1369
1370 /* I3C_DDR_EN */
1371 #define BIT_INTF_CONFIG6_I3C_DDR_EN_POS 1
1372 #define BIT_INTF_CONFIG6_I3C_DDR_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_DDR_EN_POS)
1373
1374 /* I3C_SDR_EN */
1375 #define BIT_INTF_CONFIG6_I3C_SDR_EN_POS 0
1376 #define BIT_INTF_CONFIG6_I3C_SDR_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_SDR_EN_POS)
1377
1378 /*
1379 * MPUREG_INTF_CONFIG6_B1
1380 * Register Name: INTF_CONFIG6
1381 */
1382
1383 /* I3C_IBI_BYTE_EN */
1384 #define BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS 3
1385 #define BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS)
1386
1387 /* I3C_IBI_EN */
1388 #define BIT_INTF_CONFIG6_I3C_IBI_EN_POS 2
1389 #define BIT_INTF_CONFIG6_I3C_IBI_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_IBI_EN_POS)
1390
1391 /* ----------------------------------------------------------------------------
1392 * Register bank 2
1393 * ---------------------------------------------------------------------------- */
1394
1395 /*
1396 * MPUREG_ACCEL_CONFIG_STATIC2_B2
1397 * Register Name: ACCEL_CONFIG_STATIC2
1398 */
1399
1400 /* ACCEL_AAF_DIS */
1401 #define BIT_ACCEL_AAF_DIS_POS 0
1402 #define BIT_ACCEL_AAF_DIS_MASK (0x01 << BIT_ACCEL_AAF_DIS_POS)
1403
1404 typedef enum {
1405 ICM426XX_ACCEL_AAF_EN = (0x0 << BIT_ACCEL_AAF_DIS_POS),
1406 ICM426XX_ACCEL_AAF_DIS = (0x1 << BIT_ACCEL_AAF_DIS_POS),
1407 } ICM426XX_ACCEL_AAF_DIS_t;
1408
1409 /* ACCEL_AAF_DELT */
1410 #define BIT_ACCEL_AAF_DELT_POS 1
1411 #define BIT_ACCEL_AAF_DELT_MASK (0x3F << BIT_ACCEL_AAF_DELT_POS)
1412
1413 /*
1414 * MPUREG_ACCEL_CONFIG_STATIC3_B2
1415 * Register Name: ACCEL_CONFIG_STATIC3
1416 */
1417
1418 /* ACCEL_AAF_DELTSQR */
1419 #define BIT_ACCEL_AAF_DELTSQR_POS_LO 0
1420 #define BIT_ACCEL_AAF_DELTSQR_MASK_LO (0xFF << BIT_ACCEL_AAF_DELTSQR_POS_LO)
1421
1422 /*
1423 * MPUREG_ACCEL_CONFIG_STATIC4_B2
1424 * Register Name: ACCEL_CONFIG_STATIC4
1425 */
1426
1427 /* ACCEL_AAF_DELTSQR */
1428 #define BIT_ACCEL_AAF_DELTSQR_POS_HI 0
1429 #define BIT_ACCEL_AAF_DELTSQR_MASK_HI (0x0F << BIT_ACCEL_AAF_DELTSQR_POS_HI)
1430
1431 /* ACCEL_AAF_BITSHIFT */
1432 #define BIT_ACCEL_AAF_BITSHIFT_POS 4
1433 #define BIT_ACCEL_AAF_BITSHIFT_MASK (0x0F << BIT_ACCEL_AAF_BITSHIFT_POS)
1434
1435 /*
1436 * MPUREG_OIS1_CONFIG1_B2
1437 * Register Name: OIS1_CONFIG1
1438 */
1439
1440 /* OIS1_ACCEL_LP_CLK_SEL */
1441 #define BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS 5
1442 #define BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_MASK (0x1 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS)
1443
1444 typedef enum {
1445 ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC = (0x0 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS),
1446 ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC = (0x1 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS),
1447 } ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_t;
1448
1449 /* OIS1_DEC */
1450 #define BIT_OIS1_CONFIG1_DEC_POS 2
1451 #define BIT_OIS1_CONFIG1_DEC_MASK (0x7 << BIT_OIS1_CONFIG1_DEC_POS)
1452
1455 typedef enum {
1456 ICM426XX_OIS1_CONFIG1_DEC_1 = (0x0 << BIT_OIS1_CONFIG1_DEC_POS),
1457 ICM426XX_OIS1_CONFIG1_DEC_2 = (0x1 << BIT_OIS1_CONFIG1_DEC_POS),
1458 ICM426XX_OIS1_CONFIG1_DEC_4 = (0x2 << BIT_OIS1_CONFIG1_DEC_POS),
1459 ICM426XX_OIS1_CONFIG1_DEC_8 = (0x3 << BIT_OIS1_CONFIG1_DEC_POS),
1460 ICM426XX_OIS1_CONFIG1_DEC_16 = (0x4 << BIT_OIS1_CONFIG1_DEC_POS),
1461 ICM426XX_OIS1_CONFIG1_DEC_32 = (0x5 << BIT_OIS1_CONFIG1_DEC_POS),
1462 } ICM426XX_OIS1_CONFIG1_DEC_t;
1463
1464 /* GYRO_OIS1_EN */
1465 #define BIT_OIS1_CONFIG1_GYRO_EN_POS 1
1466 #define BIT_OIS1_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS1_CONFIG1_GYRO_EN_POS)
1467
1468 typedef enum {
1469 ICM426XX_OIS1_CONFIG1_GYRO_EN = (0x1 << BIT_OIS1_CONFIG1_GYRO_EN_POS),
1470 ICM426XX_OIS1_CONFIG1_GYRO_DIS = (0x0 << BIT_OIS1_CONFIG1_GYRO_EN_POS),
1471 } ICM426XX_OIS1_CONFIG1_GYRO_EN_t;
1472
1473 /* ACCEL_OIS1_EN */
1474 #define BIT_OIS1_CONFIG1_ACCEL_EN_POS 0
1475 #define BIT_OIS1_CONFIG1_ACCEL_EN_MASK (0x1 << BIT_OIS1_CONFIG1_ACCEL_EN_POS)
1476
1477 typedef enum {
1478 ICM426XX_OIS1_CONFIG1_ACCEL_EN = (0x1 << BIT_OIS1_CONFIG1_ACCEL_EN_POS),
1479 ICM426XX_OIS1_CONFIG1_ACCEL_DIS = (0x0 << BIT_OIS1_CONFIG1_ACCEL_EN_POS),
1480 } ICM426XX_OIS1_CONFIG1_ACCEL_EN_t;
1481
1482 /*
1483 * MPUREG_OIS1_CONFIG2_B2
1484 * Register Name: OIS1_CONFIG2
1485 */
1486
1487 /* GYRO_OIS1_FS_SEL */
1488 #define BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS 3
1489 #define BIT_OIS1_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS)
1490
1493 typedef enum {
1494 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_16dps =
1495 (0x7 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1496 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_31dps =
1497 (0x6 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1498 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_62dps =
1499 (0x5 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1500 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_125dps =
1501 (0x4 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1502 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_250dps =
1503 (0x3 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1504 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_500dps =
1505 (0x2 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1506 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_1000dps =
1507 (0x1 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1508 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_2000dps =
1509 (0x0 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1510 } ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_t;
1511
1512 /* ACCEL_OIS1_FS_SEL */
1513 #define BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS 0
1514 #define BIT_OIS1_CONFIG2_ACCEL_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS)
1515
1518 typedef enum {
1519 ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_RESERVED = (0x4 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1520 ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_2g = (0x3 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1521 ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_4g = (0x2 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1522 ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_8g = (0x1 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1523 ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_16g = (0x0 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1524 } ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_t;
1525
1526 /*
1527 * MPUREG_INT_STATUS_OIS1_B2
1528 * Register Name: INT_STATUS_OIS1
1529 */
1530 #define BIT_INT_STATUS_OIS1_FSYNC 0x04
1531 #define BIT_INT_STATUS_OIS1_DRDY 0x02
1532 #define BIT_INT_STATUS_OIS1_AGC_RDY 0x01
1533
1534 /*
1535 * MPUREG_OIS2_CONFIG1_B2
1536 * Register Name: OIS2_CONFIG1
1537 */
1538
1539 /* OIS2_ACCEL_LP_CLK_SEL */
1540 #define BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS 5
1541 #define BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_MASK (0x1 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS)
1542
1543 typedef enum {
1544 ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC = (0x0 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS),
1545 ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC = (0x1 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS),
1546 } ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_t;
1547
1548 /* OIS2_DEC */
1549 #define BIT_OIS2_CONFIG1_DEC_POS 2
1550 #define BIT_OIS2_CONFIG1_DEC_MASK (0x7 << BIT_OIS2_CONFIG1_DEC_POS)
1551
1554 typedef enum {
1555 ICM426XX_OIS2_CONFIG1_DEC_1 = (0x0 << BIT_OIS2_CONFIG1_DEC_POS),
1556 ICM426XX_OIS2_CONFIG1_DEC_2 = (0x1 << BIT_OIS2_CONFIG1_DEC_POS),
1557 ICM426XX_OIS2_CONFIG1_DEC_4 = (0x2 << BIT_OIS2_CONFIG1_DEC_POS),
1558 ICM426XX_OIS2_CONFIG1_DEC_8 = (0x3 << BIT_OIS2_CONFIG1_DEC_POS),
1559 ICM426XX_OIS2_CONFIG1_DEC_16 = (0x4 << BIT_OIS2_CONFIG1_DEC_POS),
1560 ICM426XX_OIS2_CONFIG1_DEC_32 = (0x5 << BIT_OIS2_CONFIG1_DEC_POS),
1561 } ICM426XX_OIS2_CONFIG1_DEC_t;
1562
1563 /* GYRO_OIS2_EN */
1564 #define BIT_OIS2_CONFIG1_GYRO_EN_POS 1
1565 #define BIT_OIS2_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS2_CONFIG1_GYRO_EN_POS)
1566
1567 typedef enum {
1568 ICM426XX_OIS2_CONFIG1_GYRO_EN = (0x1 << BIT_OIS2_CONFIG1_GYRO_EN_POS),
1569 ICM426XX_OIS2_CONFIG1_GYRO_DIS = (0x0 << BIT_OIS2_CONFIG1_GYRO_EN_POS),
1570 } ICM426XX_OIS2_CONFIG1_GYRO_EN_t;
1571
1572 /* ACCEL_OIS2_EN */
1573 #define BIT_OIS2_CONFIG1_ACCEL_EN_POS 0
1574 #define BIT_OIS2_CONFIG1_ACCEL_EN_MASK (0x1 << BIT_OIS2_CONFIG1_ACCEL_EN_POS)
1575
1576 typedef enum {
1577 ICM426XX_OIS2_CONFIG1_ACCEL_EN = (0x1 << BIT_OIS2_CONFIG1_ACCEL_EN_POS),
1578 ICM426XX_OIS2_CONFIG1_ACCEL_DIS = (0x0 << BIT_OIS2_CONFIG1_ACCEL_EN_POS),
1579 } ICM426XX_OIS2_CONFIG1_ACCEL_EN_t;
1580
1581 /*
1582 * MPUREG_OIS2_CONFIG2_B2
1583 * Register Name: OIS2_CONFIG2
1584 */
1585
1586 /* GYRO_OIS2_FS_SEL */
1587 #define BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS 3
1588 #define BIT_OIS2_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS)
1589
1592 typedef enum {
1593 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_16dps =
1594 (0x7 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1595 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_31dps =
1596 (0x6 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1597 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_62dps =
1598 (0x5 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1599 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_125dps =
1600 (0x4 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1601 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_250dps =
1602 (0x3 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1603 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_500dps =
1604 (0x2 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1605 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_1000dps =
1606 (0x1 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1607 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_2000dps =
1608 (0x0 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1609 } ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_t;
1610
1611 /* ACCEL_OIS2_FS_SEL */
1612 #define BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS 0
1613 #define BIT_OIS2_CONFIG2_ACCEL_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS)
1614
1617 typedef enum {
1618 ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_RESERVED = (0x4 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1619 ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_2g = (0x3 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1620 ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_4g = (0x2 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1621 ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_8g = (0x1 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1622 ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_16g = (0x0 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1623 } ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_t;
1624
1625 /*
1626 * MPUREG_INT_STATUS_OIS2_B2
1627 * Register Name: INT_STATUS_OIS2
1628 */
1629 #define BIT_INT_STATUS_OIS2_FSYNC 0x04
1630 #define BIT_INT_STATUS_OIS2_DRDY 0x02
1631 #define BIT_INT_STATUS_OIS2_AGC_RDY 0x01
1632
1633 /* ----------------------------------------------------------------------------
1634 * Register bank 4
1635 * ---------------------------------------------------------------------------- */
1636
1637 /*
1638 * MPUREG_FDR_CONFIG_B4
1639 * Register Name: FDR_CONFIG
1640 */
1641
1642 /* FDR_SEL */
1643
1644 #define BIT_FDR_CONFIG_FDR_SEL_POS 0
1645 #define BIT_FDR_CONFIG_FDR_SEL_MASK 0x7F
1646
1647 /*
1648 * MPUREG_APEX_CONFIG1_B4
1649 * Register Name: APEX_CONFIG1
1650 */
1651
1652 /* DMP_POWER_SAVE_TIME_SEL */
1653
1654 #define BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_POS 0
1655 #define BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_MASK 0x0F
1656
1657 typedef enum {
1658 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_0S = 0x0,
1659 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_4S = 0x1,
1660 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_8S = 0x2,
1661 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_12S = 0x3,
1662 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_16S = 0x4,
1663 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_20S = 0x5,
1664 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_24S = 0x6,
1665 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_28S = 0x7,
1666 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_32S = 0x8,
1667 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_36S = 0x9,
1668 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_40S = 0xA,
1669 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_44S = 0xB,
1670 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_48S = 0xC,
1671 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_52S = 0xD,
1672 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_56S = 0xE,
1673 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_60S = 0xF
1674 } ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t;
1675
1676 /* LOW_ENERGY_AMP_TH_SEL */
1677
1678 #define BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS 4
1679 #define BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_MASK \
1680 (0x0F << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS)
1681
1682 typedef enum {
1683 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_30MG =
1684 (0 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1685 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_35MG =
1686 (1 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1687 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_40MG =
1688 (2 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1689 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_45MG =
1690 (3 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1691 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_50MG =
1692 (4 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1693 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_55MG =
1694 (5 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1695 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_60MG =
1696 (6 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1697 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_65MG =
1698 (7 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1699 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_70MG =
1700 (8 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1701 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_75MG =
1702 (9 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1703 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_80MG =
1704 (10 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1705 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_85MG =
1706 (11 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1707 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_90MG =
1708 (12 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1709 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_95MG =
1710 (13 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1711 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_100MG =
1712 (14 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1713 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_105MG =
1714 (15 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS)
1715 } ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t;
1716
1717 // Retro-compatibility
1718 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1006632MG \
1719 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_30MG
1720 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1174405MG \
1721 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_35MG
1722 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1342177MG \
1723 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_40MG
1724 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1509949MG \
1725 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_45MG
1726 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1677721MG \
1727 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_50MG
1728 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1845493MG \
1729 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_55MG
1730 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2013265MG \
1731 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_60MG
1732 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2181038MG \
1733 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_65MG
1734 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2348810MG \
1735 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_70MG
1736 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2516582MG \
1737 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_75MG
1738 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2684354MG \
1739 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_80MG
1740 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2852126MG \
1741 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_85MG
1742 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3019898MG \
1743 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_90MG
1744 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3187671MG \
1745 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_95MG
1746 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3355443MG \
1747 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_100MG
1748 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3523215MG \
1749 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_105MG
1750
1751 /*
1752 * MPUREG_APEX_CONFIG2_B4
1753 * Register Name: APEX_CONFIG2
1754 */
1755
1756 /* PEDO_AMP_TH_SEL */
1757
1758 #define BIT_APEX_CONFIG2_PEDO_AMP_TH_POS 4
1759 #define BIT_APEX_CONFIG2_PEDO_AMP_TH_MASK (0x0F << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS)
1760
1761 typedef enum {
1762 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_30MG = (0 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1763 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_34MG = (1 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1764 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_38MG = (2 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1765 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_42MG = (3 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1766 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_46MG = (4 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1767 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_50MG = (5 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1768 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_54MG = (6 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1769 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_58MG = (7 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1770 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_62MG = (8 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1771 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_66MG = (9 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1772 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_70MG = (10 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1773 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_74MG = (11 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1774 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_78MG = (12 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1775 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_82MG = (13 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1776 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_86MG = (14 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1777 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_90MG = (15 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS)
1778 } ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_t;
1779
1780 // Retro-compatibility
1781 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1006632_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_30MG
1782 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1140850_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_34MG
1783 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1275068_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_38MG
1784 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1409286_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_42MG
1785 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1543503_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_46MG
1786 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1677721_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_50MG
1787 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1811939_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_54MG
1788 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1946157_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_58MG
1789 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2080374_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_62MG
1790 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2214592_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_66MG
1791 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2348810_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_70MG
1792 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2483027_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_74MG
1793 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2617245_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_78MG
1794 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2751463_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_82MG
1795 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2885681_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_86MG
1796 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_3019898_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_90MG
1797
1798 /* PEDO_STEP_CNT_TH_SEL */
1799
1800 #define BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_POS 0
1801 #define BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_MASK 0x0F
1802
1803 /*
1804 * MPUREG_APEX_CONFIG3_B4
1805 * Register Name: APEX_CONFIG3
1806 */
1807
1808 /* PEDO_STEP_DET_TH_SEL */
1809
1810 #define BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS 5
1811 #define BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_MASK (0x07 << BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS)
1812
1813 /* PEDO_SB_TIMER_TH_SEL */
1814
1815 #define BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS 2
1816 #define BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_MASK (0x07 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS)
1817
1818 typedef enum {
1819 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_50_SAMPLES =
1820 (0 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1821 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_75_SAMPLES =
1822 (1 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1823 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_100_SAMPLES =
1824 (2 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1825 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_125_SAMPLES =
1826 (3 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1827 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_150_SAMPLES =
1828 (4 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1829 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_175_SAMPLES =
1830 (5 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1831 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_200_SAMPLES =
1832 (6 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1833 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_225_SAMPLES =
1834 (7 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS)
1835 } ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t;
1836
1837 /* PEDO_HI_ENRGY_TH_SEL */
1838
1839 #define BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_POS 0
1840 #define BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_MASK 0x03
1841
1842 typedef enum {
1843 ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_90 = 0x0,
1844 ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_107 = 0x1,
1845 ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_136 = 0x2,
1846 ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_159 = 0x3
1847 } ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t;
1848
1849 /*
1850 * MPUREG_APEX_CONFIG4_B4
1851 * Register Name: APEX_CONFIG4
1852 */
1853
1854 /* TILT_WAIT_TIME_SEL */
1855
1856 #define BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS 6
1857 #define BIT_APEX_CONFIG4_TILT_WAIT_TIME_MASK (0x03 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS)
1858
1859 typedef enum {
1860 ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_0S = (0 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS),
1861 ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_2S = (1 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS),
1862 ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_4S = (2 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS),
1863 ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_6S = (3 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS)
1864 } ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_t;
1865
1866 #if defined(ICM_FAMILY_BPLUS)
1867 /* R2W_SLEEP_TIME_OUT */
1868
1869 #define BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS 3
1870 #define BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_MASK (0x07 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS)
1871
1872 typedef enum {
1873 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_1_28S = (0 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1874 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_2_56S = (1 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1875 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_3_84S = (2 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1876 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_5_12S = (3 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1877 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_6_4S = (4 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1878 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_7_68S = (5 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1879 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_8_96S = (6 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1880 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_10_24S = (7 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS)
1881 } ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t;
1882
1883 /*
1884 * MPUREG_APEX_CONFIG5_B4
1885 * Register Name: APEX_CONFIG5
1886 */
1887
1888 /* R2W_MOUNTING_MATRIX */
1889
1890 #define BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS 0
1891 #define BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_MASK (0x07 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS)
1892
1893 typedef enum {
1894 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_0 = (0 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1895 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_1 = (1 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1896 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_2 = (2 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1897 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_3 = (3 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1898 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_4 = (4 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1899 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_5 = (5 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1900 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_6 = (6 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1901 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_7 = (7 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS)
1902 } ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t;
1903
1904 /*
1905 * MPUREG_APEX_CONFIG6_B4
1906 * Register Name: APEX_CONFIG6
1907 */
1908
1909 /* R2W_SLEEP_GEST_DELAY */
1910
1911 #define BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS 0
1912 #define BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_MASK \
1913 (0x07 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS)
1914
1915 typedef enum {
1916 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_32S =
1917 (0 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1918 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_64S =
1919 (1 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1920 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_96S =
1921 (2 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1922 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_28S =
1923 (3 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1924 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_6S =
1925 (4 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1926 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_92S =
1927 (5 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1928 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_24S =
1929 (6 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1930 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_56S =
1931 (7 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS)
1932 } ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t;
1933
1934 #elif defined(ICM_FAMILY_CPLUS)
1935
1936 /* LOWG_PEAK_TH_HYST */
1937
1938 #define BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS 3
1939 #define BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_MASK (0x07 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS)
1940
1941 typedef enum {
1942 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_31MG = (0 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS),
1943 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_63MG = (1 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS),
1944 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_94MG = (2 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS),
1945 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_125MG = (3 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS),
1946 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_156MG = (4 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS),
1947 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_188MG = (5 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS),
1948 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_219MG = (6 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS),
1949 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_250MG = (7 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS)
1950 } ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_t;
1951
1952 /* HIGHG_PEAK_TH_HYST */
1953
1954 #define BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS 0
1955 #define BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_MASK (0x07 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS)
1956
1957 typedef enum {
1958 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_31MG = (0 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS),
1959 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_63MG = (1 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS),
1960 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_94MG = (2 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS),
1961 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_125MG = (3 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS),
1962 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_156MG = (4 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS),
1963 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_188MG = (5 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS),
1964 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_219MG = (6 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS),
1965 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_250MG = (7 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS)
1966 } ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_t;
1967
1968 /*
1969 * MPUREG_APEX_CONFIG5_B4
1970 * Register Name: APEX_CONFIG5
1971 */
1972
1973 /* LOWG_PEAK_TH */
1974
1975 #define BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS 3
1976 #define BIT_APEX_CONFIG5_LOWG_PEAK_TH_MASK (0x1f << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS)
1977
1978 typedef enum {
1979 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_31MG = (0x00 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1980 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_63MG = (0x01 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1981 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_94MG = (0x02 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1982 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_125MG = (0x03 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1983 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_156MG = (0x04 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1984 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_188MG = (0x05 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1985 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_219MG = (0x06 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1986 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_250MG = (0x07 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1987 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_281MG = (0x08 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1988 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_313MG = (0x09 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1989 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_344MG = (0x0A << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1990 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_375MG = (0x0B << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1991 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_406MG = (0x0C << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1992 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_438MG = (0x0D << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1993 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_469MG = (0x0E << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1994 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_500MG = (0x0F << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1995 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_531MG = (0x10 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1996 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_563MG = (0x11 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1997 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_594MG = (0x12 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1998 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_625MG = (0x13 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
1999 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_656MG = (0x14 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2000 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_688MG = (0x15 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2001 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_719MG = (0x16 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2002 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_750MG = (0x17 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2003 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_781MG = (0x18 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2004 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_813MG = (0x19 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2005 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_844MG = (0x1A << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2006 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_875MG = (0x1B << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2007 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_906MG = (0x1C << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2008 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_938MG = (0x1D << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2009 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_969MG = (0x1E << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2010 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_1000MG = (0x1F << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS)
2011 } ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_t;
2012
2013 /* LOWG_TIME_TH */
2014
2015 #define BIT_APEX_CONFIG5_LOWG_TIME_TH_POS 0
2016 #define BIT_APEX_CONFIG5_LOWG_TIME_TH_MASK (0x07 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS)
2017
2018 typedef enum {
2019 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_1_SAMPLE = (0x00 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS),
2020 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_2_SAMPLES = (0x01 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS),
2021 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_3_SAMPLES = (0x02 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS),
2022 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_4_SAMPLES = (0x03 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS),
2023 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_5_SAMPLES = (0x04 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS),
2024 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_6_SAMPLES = (0x05 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS),
2025 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_7_SAMPLES = (0x06 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS),
2026 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_8_SAMPLES = (0x07 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS)
2027 } ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_SAMPLES_t;
2028
2029 /*
2030 * MPUREG_APEX_CONFIG6_B4
2031 * Register Name: APEX_CONFIG6
2032 */
2033 /* HIGHG_PEAK_TH */
2034
2035 #define BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS 3
2036 #define BIT_APEX_CONFIG6_HIGHG_PEAK_TH_MASK (0x1f << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS)
2037
2038 typedef enum {
2039 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_250MG = (0x00 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2040 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_500MG = (0x01 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2041 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_750MG = (0x02 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2042 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_1000MG = (0x03 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2043 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_1250MG = (0x04 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2044 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_1500MG = (0x05 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2045 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_1750MG = (0x06 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2046 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_2000MG = (0x07 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2047 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_2250MG = (0x08 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2048 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_2500MG = (0x09 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2049 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_2750MG = (0x0A << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2050 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_3000MG = (0x0B << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2051 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_3250MG = (0x0C << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2052 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_3500MG = (0x0D << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2053 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_3750MG = (0x0E << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2054 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_4000MG = (0x0F << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2055 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_4250MG = (0x10 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2056 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_4500MG = (0x11 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2057 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_4750MG = (0x12 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2058 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_5000MG = (0x13 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2059 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_5250MG = (0x14 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2060 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_5500MG = (0x15 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2061 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_5750MG = (0x16 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2062 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_6000MG = (0x17 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2063 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_6250MG = (0x18 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2064 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_6500MG = (0x19 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2065 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_6750MG = (0x1A << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2066 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_7000MG = (0x1B << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2067 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_7250MG = (0x1C << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2068 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_7500MG = (0x1D << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2069 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_7750MG = (0x1E << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2070 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_8000MG = (0x1F << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS)
2071 } ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_t;
2072
2073 /* HIGHG_TIME_TH */
2074
2075 #define BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS 0
2076 #define BIT_APEX_CONFIG6_HIGHG_TIME_TH_MASK (0x07 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS)
2077
2078 typedef enum {
2079 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_1_SAMPLE = (0x00 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS),
2080 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_2_SAMPLES = (0x01 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS),
2081 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_3_SAMPLES = (0x02 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS),
2082 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_4_SAMPLES = (0x03 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS),
2083 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_5_SAMPLES = (0x04 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS),
2084 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_6_SAMPLES = (0x05 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS),
2085 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_7_SAMPLES = (0x06 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS),
2086 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_8_SAMPLES = (0x07 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS)
2087 } ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_SAMPLES_t;
2088
2089 #endif
2090
2091 /*
2092 * MPUREG_APEX_CONFIG7_B4
2093 * Register Name: APEX_CONFIG7
2094 */
2095
2096 /* TAP_MIN_JERK_THR */
2097 #define BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS 2
2098 #define BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_MASK (0x3F << BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS)
2099
2100 #define ICM426XX_APEX_CONFIG7_TAP_MIN_JERK_THR_281MG_DEFAULT 0x11
2101
2102 /* TAP_MAX_PEAK_TOL */
2103 #define BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_POS 0
2104 #define BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_MASK 0x3
2105
2106 typedef enum {
2107 ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_12 = 0x0,
2108 ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_25 = 0x1,
2109 ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_37 = 0x2,
2110 ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_50 = 0x3
2111 } ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t;
2112
2113 /*
2114 * MPUREG_APEX_CONFIG8_B4
2115 * Register Name: APEX_CONFIG8
2116 */
2117
2118 /* TAP_TMAX */
2119 #define BIT_APEX_CONFIG8_TAP_TMAX_POS 5
2120 #define BIT_APEX_CONFIG8_TAP_TMAX_MASK (0x03 << BIT_APEX_CONFIG8_TAP_TMAX_POS)
2121
2122 typedef enum {
2123 ICM426XX_APEX_CONFIG8_TAP_TMAX_250MS = (0 << BIT_APEX_CONFIG8_TAP_TMAX_POS),
2124 ICM426XX_APEX_CONFIG8_TAP_TMAX_375MS = (1 << BIT_APEX_CONFIG8_TAP_TMAX_POS),
2125 ICM426XX_APEX_CONFIG8_TAP_TMAX_500MS = (2 << BIT_APEX_CONFIG8_TAP_TMAX_POS),
2126 ICM426XX_APEX_CONFIG8_TAP_TMAX_625MS = (3 << BIT_APEX_CONFIG8_TAP_TMAX_POS)
2127 } ICM426XX_APEX_CONFIG8_TAP_TMAX_t;
2128
2129 /* TAP_TAVG */
2130 #define BIT_APEX_CONFIG8_TAP_TAVG_POS 3
2131 #define BIT_APEX_CONFIG8_TAP_TAVG_MASK (0x03 << BIT_APEX_CONFIG8_TAP_TAVG_POS)
2132
2133 typedef enum {
2134 ICM426XX_APEX_CONFIG8_TAP_TAVG_1SAMPLE = (0 << BIT_APEX_CONFIG8_TAP_TAVG_POS),
2135 ICM426XX_APEX_CONFIG8_TAP_TAVG_2SAMPLE = (1 << BIT_APEX_CONFIG8_TAP_TAVG_POS),
2136 ICM426XX_APEX_CONFIG8_TAP_TAVG_4SAMPLE = (2 << BIT_APEX_CONFIG8_TAP_TAVG_POS),
2137 ICM426XX_APEX_CONFIG8_TAP_TAVG_8SAMPLE = (3 << BIT_APEX_CONFIG8_TAP_TAVG_POS)
2138 } ICM426XX_APEX_CONFIG8_TAP_TAVG_t;
2139
2140 /* TAP_TMIN */
2141 #define BIT_APEX_CONFIG8_TAP_TMIN_POS 0
2142 #define BIT_APEX_CONFIG8_TAP_TMIN_MASK 0x07
2143
2144 typedef enum {
2145 ICM426XX_APEX_CONFIG8_TAP_TMIN_125MS = 0x0,
2146 ICM426XX_APEX_CONFIG8_TAP_TMIN_140MS = 0x1,
2147 ICM426XX_APEX_CONFIG8_TAP_TMIN_156MS = 0x2,
2148 ICM426XX_APEX_CONFIG8_TAP_TMIN_171MS = 0x3,
2149 ICM426XX_APEX_CONFIG8_TAP_TMIN_187MS = 0x4,
2150 ICM426XX_APEX_CONFIG8_TAP_TMIN_203MS = 0x5,
2151 ICM426XX_APEX_CONFIG8_TAP_TMIN_218MS = 0x6,
2152 ICM426XX_APEX_CONFIG8_TAP_TMIN_234MS = 0x7
2153 } ICM426XX_APEX_CONFIG8_TAP_TMIN_t;
2154
2155 /*
2156 * MPUREG_APEX_CONFIG9_B4
2157 * Register Name: APEX_CONFIG9
2158 */
2159 #define BIT_APEX_CONFIG9_SENSITIVITY_MODE_POS 0
2160 #define BIT_APEX_CONFIG9_SENSITIVITY_MODE_MASK 0x01
2161 typedef enum {
2162 ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_NORMAL = 0x00,
2163 ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_RESERVED = 0x01
2164 } ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_t;
2165
2166 #if defined(ICM_FAMILY_CPLUS)
2167
2168 /*
2169 * MPUREG_APEX_CONFIG10_B4
2170 * Register Name: APEX_CONFIG10
2171 */
2172
2173 /* FF_DEBOUNCE_DURATION */
2174 #define BIT_APEX_CONFIG10_FF_DEBOUNCE_DURATION_POS 0
2175 #define BIT_APEX_CONFIG10_FF_DEBOUNCE_DURATION_MASK \
2176 (0x03 << BIT_APEX_CONFIG10_FF_DEBOUNCE_DURATION_POS)
2177
2178 typedef enum {
2179 ICM426XX_APEX_CONFIG10_FF_DEBOUNCE_DURATION_0_MS =
2180 (0 << BIT_APEX_CONFIG10_FF_DEBOUNCE_DURATION_POS),
2181 ICM426XX_APEX_CONFIG10_FF_DEBOUNCE_DURATION_1000_MS =
2182 (1 << BIT_APEX_CONFIG10_FF_DEBOUNCE_DURATION_POS),
2183 ICM426XX_APEX_CONFIG10_FF_DEBOUNCE_DURATION_2000_MS =
2184 (2 << BIT_APEX_CONFIG10_FF_DEBOUNCE_DURATION_POS),
2185 ICM426XX_APEX_CONFIG10_FF_DEBOUNCE_DURATION_3000_MS =
2186 (3 << BIT_APEX_CONFIG10_FF_DEBOUNCE_DURATION_POS)
2187 } ICM426XX_APEX_CONFIG10_FF_DEBOUNCE_DURATION_t;
2188
2189 /* FF_MAX_DURATION */
2190 #define BIT_APEX_CONFIG10_FF_MAX_DURATION_POS 2
2191 #define BIT_APEX_CONFIG10_FF_MAX_DURATION_MASK (0x07 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS)
2192
2193 typedef enum {
2194 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_113_CM = (0 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS),
2195 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_154_CM = (1 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS),
2196 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_201_CM = (2 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS),
2197 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_255_CM = (3 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS),
2198 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_314_CM = (4 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS),
2199 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_380_CM = (5 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS),
2200 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_452_CM = (6 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS),
2201 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_531_CM = (7 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS)
2202 } ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_t;
2203
2204 /* FF_MIN_DURATION */
2205 #define BIT_APEX_CONFIG10_FF_MIN_DURATION_POS 5
2206 #define BIT_APEX_CONFIG10_FF_MIN_DURATION_MASK (0x07 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS)
2207
2208 typedef enum {
2209 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_13_CM = (0 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS),
2210 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_19_CM = (1 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS),
2211 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_28_CM = (2 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS),
2212 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_38_CM = (3 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS),
2213 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_50_CM = (4 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS),
2214 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_64_CM = (5 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS),
2215 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_78_CM = (6 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS),
2216 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_95_CM = (7 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS)
2217 } ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_t;
2218
2219 #endif
2220
2221 /*
2222 * MPUREG_INT_SOURCE6_B4
2223 * Register Name: INT_SOURCE6
2224 */
2225 #define BIT_INT_STEP_DET_INT_EN_POS 5
2226 #define BIT_INT_STEP_CNT_OVFL_INT_EN_POS 4
2227 #define BIT_INT_TILT_DET_INT_EN_POS 3
2228 #if defined(ICM_FAMILY_BPLUS)
2229 #define BIT_INT_WAKE_DET_INT_EN_POS 2
2230 #define BIT_INT_SLEEP_DET_INT_EN_POS 1
2231 #elif defined(ICM_FAMILY_CPLUS)
2232 #define BIT_INT_LOWG_DET_INT_EN_POS 2
2233 #define BIT_INT_FF_DET_INT_EN_POS 1
2234 #endif
2235 #define BIT_INT_TAP_DET_INT_EN_POS 0
2236
2237 #define BIT_INT_SOURCE6_STEP_DET_INT1_EN 0x20
2238 #define BIT_INT_SOURCE6_STEP_CNT_OVFL_INT1_EN 0x10
2239 #define BIT_INT_SOURCE6_TILT_DET_INT1_EN 0x8
2240 #if defined(ICM_FAMILY_BPLUS)
2241 #define BIT_INT_SOURCE6_WAKE_DET_INT1_EN 0x4
2242 #define BIT_INT_SOURCE6_SLEEP_DET_INT1_EN 0x2
2243 #elif defined(ICM_FAMILY_CPLUS)
2244 #define BIT_INT_SOURCE6_LOWG_DET_INT1_EN 0x4
2245 #define BIT_INT_SOURCE6_FF_DET_INT1_EN 0x2
2246 #endif
2247 #define BIT_INT_SOURCE6_TAP_DET_INT1_EN 0x1
2248
2249 /*
2250 * MPUREG_INT_SOURCE7_B4
2251 * Register Name: INT_SOURCE7
2252 */
2253 #define BIT_INT_SOURCE7_STEP_DET_INT2_EN 0x20
2254 #define BIT_INT_SOURCE7_STEP_CNT_OVFL_INT2_EN 0x10
2255 #define BIT_INT_SOURCE7_TILT_DET_INT2_EN 0x8
2256 #if defined(ICM_FAMILY_BPLUS)
2257 #define BIT_INT_SOURCE7_WAKE_DET_INT2_EN 0x4
2258 #define BIT_INT_SOURCE7_SLEEP_DET_INT2_EN 0x2
2259 #elif defined(ICM_FAMILY_CPLUS)
2260 #define BIT_INT_SOURCE7_LOWG_DET_INT2_EN 0x4
2261 #define BIT_INT_SOURCE7_FF_DET_INT2_EN 0x2
2262 #endif
2263 #define BIT_INT_SOURCE7_TAP_DET_INT2_EN 0x1
2264
2265 /*
2266 * MPUREG_INT_SOURCE8_B4
2267 * Register Name: INT_SOURCE8
2268 */
2269 #define BIT_INT_OIS1_DRDY_IBI_EN_POS 6
2270 #define BIT_INT_UI_FSYNC_IBI_EN_POS 5
2271 #define BIT_INT_PLL_RDY_IBI_EN_POS 4
2272 #define BIT_INT_UI_DRDY_IBI_EN_POS 3
2273 #define BIT_INT_FIFO_THS_IBI_EN_POS 2
2274 #define BIT_INT_FIFO_FULL_IBI_EN_POS 1
2275 #define BIT_INT_UI_AGC_RDY_IBI_EN_POS 0
2276
2277 #define BIT_INT_SOURCE8_OIS1_DRDY_IBI_EN 0x40
2278 #define BIT_INT_SOURCE8_UI_FSYNC_IBI_EN 0x20
2279 #define BIT_INT_SOURCE8_PLL_RDY_IBI_EN 0x10
2280 #define BIT_INT_SOURCE8_UI_DRDY_IBI_EN 0x08
2281 #define BIT_INT_SOURCE8_FIFO_THS_IBI_EN 0x04
2282 #define BIT_INT_SOURCE8_FIFO_FULL_IBI_EN 0x02
2283 #define BIT_INT_SOURCE8_UI_AGC_RDY_IBI_EN 0x01
2284
2285 /*
2286 * MPUREG_INT_SOURCE9_B4
2287 * Register Name: INT_SOURCE9
2288 */
2289 #define BIT_INT_SMD_IBI_EN_POS 4
2290 #define BIT_INT_WOM_Z_IBI_EN_POS 3
2291 #define BIT_INT_WOM_Y_IBI_EN_POS 2
2292 #define BIT_INT_WOM_X_IBI_EN_POS 1
2293
2294 #define BIT_INT_SOURCE9_SMD_IBI_EN 0x10
2295 #define BIT_INT_SOURCE9_WOM_Z_IBI_EN 0x08
2296 #define BIT_INT_SOURCE9_WOM_Y_IBI_EN 0x04
2297 #define BIT_INT_SOURCE9_WOM_X_IBI_EN 0x02
2298
2299 /*
2300 * MPUREG_INT_SOURCE10_B4
2301 * Register Name: INT_SOURCE10
2302 */
2303 #define BIT_INT_STEP_DET_IBI_EN_POS 5
2304 #define BIT_INT_STEP_CNT_OVFL_IBI_EN_POS 4
2305 #define BIT_INT_TILT_DET_IBI_EN_POS 3
2306 #if defined(ICM_FAMILY_BPLUS)
2307 #define BIT_INT_WAKE_DET_IBI_EN_POS 2
2308 #define BIT_INT_SLEEP_DET_IBI_EN_POS 1
2309 #elif defined(ICM_FAMILY_CPLUS)
2310 #define BIT_INT_LOWG_DET_IBI_EN_POS 2
2311 #define BIT_INT_FF_DET_IBI_EN_POS 1
2312 #endif
2313 #define BIT_INT_TAP_DET_IBI_EN_POS 0
2314
2315 #define BIT_INT_SOURCE10_STEP_DET_IBI_EN 0x20
2316 #define BIT_INT_SOURCE10_STEP_CNT_OVFL_IBI_EN 0x10
2317 #define BIT_INT_SOURCE10_TILT_DET_IBI_EN 0x08
2318 #if defined(ICM_FAMILY_BPLUS)
2319 #define BIT_INT_SOURCE10_WAKE_DET_IBI_EN 0x04
2320 #define BIT_INT_SOURCE10_SLEEP_DET_IBI_EN 0x02
2321 #elif defined(ICM_FAMILY_CPLUS)
2322 #define BIT_INT_SOURCE10_LOWG_DET_IBI_EN 0x04
2323 #define BIT_INT_SOURCE10_FF_DET_IBI_EN 0x02
2324 #endif
2325 #define BIT_INT_SOURCE10_TAP_DET_IBI_EN 0x01
2326
2327 /*
2328 * MPUREG_OFFSET_USER_0_B4
2329 * Register Name: OFFSET_USER0
2330 */
2331
2332 /* GYRO_X_OFFUSER */
2333 #define BIT_GYRO_X_OFFUSER_POS_LO 0
2334 #define BIT_GYRO_X_OFFUSER_MASK_LO (0xFF << BIT_GYRO_X_OFFUSER_POS_LO)
2335
2336 /*
2337 * MPUREG_OFFSET_USER_1_B4
2338 * Register Name: OFFSET_USER1
2339 */
2340
2341 #define BIT_GYRO_X_OFFUSER_POS_HI 0
2342 #define BIT_GYRO_X_OFFUSER_MASK_HI (0x0F << BIT_GYRO_X_OFFUSER_POS_HI)
2343
2344 /* GYRO_Y_OFFUSER */
2345 #define BIT_GYRO_Y_OFFUSER_POS_HI 4
2346 #define BIT_GYRO_Y_OFFUSER_MASK_HI (0x0F << BIT_GYRO_Y_OFFUSER_POS_HI)
2347
2348 /*
2349 * MPUREG_OFFSET_USER_2_B4
2350 * Register Name: OFFSET_USER2
2351 */
2352
2353 #define BIT_GYRO_Y_OFFUSER_POS_LO 0
2354 #define BIT_GYRO_Y_OFFUSER_MASK_LO (0xFF << BIT_GYRO_Y_OFFUSER_POS_LO)
2355
2356 /*
2357 * MPUREG_OFFSET_USER_3_B4
2358 * Register Name: OFFSET_USER3
2359 */
2360
2361 /* GYRO_Z_OFFUSER */
2362 #define BIT_GYRO_Z_OFFUSER_POS_LO 0
2363 #define BIT_GYRO_Z_OFFUSER_MASK_LO (0xFF << BIT_GYRO_Z_OFFUSER_POS_LO)
2364
2365 /*
2366 * MPUREG_OFFSET_USER_4_B4
2367 * Register Name: OFFSET_USER4
2368 */
2369
2370 #define BIT_GYRO_Z_OFFUSER_POS_HI 0
2371 #define BIT_GYRO_Z_OFFUSER_MASK_HI (0x0F << BIT_GYRO_Z_OFFUSER_POS_HI)
2372
2373 /* ACCEL_X_OFFUSER */
2374 #define BIT_ACCEL_X_OFFUSER_POS_HI 4
2375 #define BIT_ACCEL_X_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_X_OFFUSER_POS_HI)
2376
2377 /*
2378 * MPUREG_OFFSET_USER_5_B4
2379 * Register Name: OFFSET_USER5
2380 */
2381
2382 #define BIT_ACCEL_X_OFFUSER_POS_LO 0
2383 #define BIT_ACCEL_X_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_X_OFFUSER_POS_LO)
2384
2385 /*
2386 * MPUREG_OFFSET_USER_6_B4
2387 * Register Name: OFFSET_USER_6
2388 */
2389
2390 /* ACCEL_Y_OFFUSER */
2391 #define BIT_ACCEL_Y_OFFUSER_POS_LO 0
2392 #define BIT_ACCEL_Y_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_Y_OFFUSER_POS_LO)
2393
2394 /*
2395 * MPUREG_OFFSET_USER_7_B4
2396 * Register Name: OFFSET_USER_7
2397 */
2398
2399 #define BIT_ACCEL_Y_OFFUSER_POS_HI 0
2400 #define BIT_ACCEL_Y_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_Y_OFFUSER_POS_HI)
2401
2402 /* ACCEL_Z_OFFUSER */
2403 #define BIT_ACCEL_Z_OFFUSER_POS_HI 4
2404 #define BIT_ACCEL_Z_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_Z_OFFUSER_POS_HI)
2405
2406 /*
2407 * MPUREG_OFFSET_USER_8_B4
2408 * Register Name: OFFSET_USER_8
2409 */
2410
2411 /* ACCEL_Z_OFFUSER_L */
2412 #define BIT_ACCEL_Z_OFFUSER_POS_LO 0
2413 #define BIT_ACCEL_Z_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_Z_OFFUSER_POS_LO)
2414
2415 #ifdef __cplusplus
2416 }
2417 #endif
2418
2419 #endif /* #ifndef _INV_ICM426XX_DEFS_H_ */
BIT_OIS1_CONFIG1_DEC_POS
#define BIT_OIS1_CONFIG1_DEC_POS
Definition: Icm426xxDefs.h:1450
BIT_SENSOR_CONFIG2_OIS_MODE_POS
#define BIT_SENSOR_CONFIG2_OIS_MODE_POS
Definition: Icm426xxDefs.h:1272
ICM426XX_INT_CONFIG_INT2_POLARITY_t
ICM426XX_INT_CONFIG_INT2_POLARITY_t
Definition: Icm426xxDefs.h:381
ICM426XX_INT_CONFIG_INT2_POLARITY_HIGH
@ ICM426XX_INT_CONFIG_INT2_POLARITY_HIGH
Definition: Icm426xxDefs.h:382
ICM426XX_INT_CONFIG_INT2_POLARITY_LOW
@ ICM426XX_INT_CONFIG_INT2_POLARITY_LOW
Definition: Icm426xxDefs.h:383
BIT_CHIP_CONFIG_SPI_MODE_POS
#define BIT_CHIP_CONFIG_SPI_MODE_POS
Definition: Icm426xxDefs.h:335
ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t
ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t
Definition: Icm426xxDefs.h:1842
ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_159
@ ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_159
Definition: Icm426xxDefs.h:1846
ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_136
@ ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_136
Definition: Icm426xxDefs.h:1845
ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_107
@ ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_107
Definition: Icm426xxDefs.h:1844
ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_90
@ ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_90
Definition: Icm426xxDefs.h:1843
ICM426XX_INT_CONFIG1_ASY_RST_t
ICM426XX_INT_CONFIG1_ASY_RST_t
Definition: Icm426xxDefs.h:1165
ICM426XX_INT_CONFIG1_ASY_RST_DISABLED
@ ICM426XX_INT_CONFIG1_ASY_RST_DISABLED
Definition: Icm426xxDefs.h:1166
ICM426XX_INT_CONFIG1_ASY_RST_ENABLED
@ ICM426XX_INT_CONFIG1_ASY_RST_ENABLED
Definition: Icm426xxDefs.h:1167
BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS
#define BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS
Definition: Icm426xxDefs.h:940
BIT_APEX_CONFIG0_TILT_EN_POS
#define BIT_APEX_CONFIG0_TILT_EN_POS
Definition: Icm426xxDefs.h:1000
BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS
#define BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS
Definition: Icm426xxDefs.h:1869
ICM426XX_TMST_CONFIG_TMST_TO_REGS_EN_t
ICM426XX_TMST_CONFIG_TMST_TO_REGS_EN_t
Definition: Icm426xxDefs.h:902
ICM426XX_TMST_CONFIG_TMST_TO_REGS_DIS
@ ICM426XX_TMST_CONFIG_TMST_TO_REGS_DIS
Definition: Icm426xxDefs.h:904
ICM426XX_TMST_CONFIG_TMST_TO_REGS_EN
@ ICM426XX_TMST_CONFIG_TMST_TO_REGS_EN
Definition: Icm426xxDefs.h:903
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t
Definition: Icm426xxDefs.h:840
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_40
@ ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_40
Definition: Icm426xxDefs.h:841
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_2
@ ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_2
Definition: Icm426xxDefs.h:848
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_8
@ ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_8
Definition: Icm426xxDefs.h:845
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_4
@ ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_4
Definition: Icm426xxDefs.h:847
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_5
@ ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_5
Definition: Icm426xxDefs.h:846
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_20
@ ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_20
Definition: Icm426xxDefs.h:842
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_10
@ ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_10
Definition: Icm426xxDefs.h:844
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_16
@ ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_16
Definition: Icm426xxDefs.h:843
BIT_GYRO_AAF_DIS_POS
#define BIT_GYRO_AAF_DIS_POS
Definition: Icm426xxDefs.h:1287
ICM426XX_APEX_CONFIG8_TAP_TMIN_t
ICM426XX_APEX_CONFIG8_TAP_TMIN_t
Definition: Icm426xxDefs.h:2144
ICM426XX_APEX_CONFIG8_TAP_TMIN_171MS
@ ICM426XX_APEX_CONFIG8_TAP_TMIN_171MS
Definition: Icm426xxDefs.h:2148
ICM426XX_APEX_CONFIG8_TAP_TMIN_218MS
@ ICM426XX_APEX_CONFIG8_TAP_TMIN_218MS
Definition: Icm426xxDefs.h:2151
ICM426XX_APEX_CONFIG8_TAP_TMIN_156MS
@ ICM426XX_APEX_CONFIG8_TAP_TMIN_156MS
Definition: Icm426xxDefs.h:2147
ICM426XX_APEX_CONFIG8_TAP_TMIN_234MS
@ ICM426XX_APEX_CONFIG8_TAP_TMIN_234MS
Definition: Icm426xxDefs.h:2152
ICM426XX_APEX_CONFIG8_TAP_TMIN_187MS
@ ICM426XX_APEX_CONFIG8_TAP_TMIN_187MS
Definition: Icm426xxDefs.h:2149
ICM426XX_APEX_CONFIG8_TAP_TMIN_140MS
@ ICM426XX_APEX_CONFIG8_TAP_TMIN_140MS
Definition: Icm426xxDefs.h:2146
ICM426XX_APEX_CONFIG8_TAP_TMIN_125MS
@ ICM426XX_APEX_CONFIG8_TAP_TMIN_125MS
Definition: Icm426xxDefs.h:2145
ICM426XX_APEX_CONFIG8_TAP_TMIN_203MS
@ ICM426XX_APEX_CONFIG8_TAP_TMIN_203MS
Definition: Icm426xxDefs.h:2150
BIT_APEX_DATA4_TAP_DIR_POS
#define BIT_APEX_DATA4_TAP_DIR_POS
Definition: Icm426xxDefs.h:492
ICM426XX_CHIP_CONFIG_RESET_t
ICM426XX_CHIP_CONFIG_RESET_t
Definition: Icm426xxDefs.h:358
ICM426XX_CHIP_CONFIG_RESET_NONE
@ ICM426XX_CHIP_CONFIG_RESET_NONE
Definition: Icm426xxDefs.h:360
ICM426XX_CHIP_CONFIG_RESET_EN
@ ICM426XX_CHIP_CONFIG_RESET_EN
Definition: Icm426xxDefs.h:359
ICM426XX_OIS1_CONFIG1_ACCEL_EN_t
ICM426XX_OIS1_CONFIG1_ACCEL_EN_t
Definition: Icm426xxDefs.h:1477
ICM426XX_OIS1_CONFIG1_ACCEL_EN
@ ICM426XX_OIS1_CONFIG1_ACCEL_EN
Definition: Icm426xxDefs.h:1478
ICM426XX_OIS1_CONFIG1_ACCEL_DIS
@ ICM426XX_OIS1_CONFIG1_ACCEL_DIS
Definition: Icm426xxDefs.h:1479
BIT_ACCEL_CONFIG0_FS_SEL_POS
#define BIT_ACCEL_CONFIG0_FS_SEL_POS
Definition: Icm426xxDefs.h:760
BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS
#define BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS
Definition: Icm426xxDefs.h:837
ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_t
ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_t
Definition: Icm426xxDefs.h:1444
ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC
@ ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC
Definition: Icm426xxDefs.h:1446
ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC
@ ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC
Definition: Icm426xxDefs.h:1445
ICM426XX_PWR_MGMT_0_ACCEL_MODE_t
ICM426XX_PWR_MGMT_0_ACCEL_MODE_t
Definition: Icm426xxDefs.h:694
ICM426XX_PWR_MGMT_0_ACCEL_MODE_OFF
@ ICM426XX_PWR_MGMT_0_ACCEL_MODE_OFF
Definition: Icm426xxDefs.h:697
ICM426XX_PWR_MGMT_0_ACCEL_MODE_LP
@ ICM426XX_PWR_MGMT_0_ACCEL_MODE_LP
Definition: Icm426xxDefs.h:696
ICM426XX_PWR_MGMT_0_ACCEL_MODE_LN
@ ICM426XX_PWR_MGMT_0_ACCEL_MODE_LN
Definition: Icm426xxDefs.h:695
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_t
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_t
OIS1 gyroscope FSR selection.
Definition: Icm426xxDefs.h:1493
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_31dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_31dps
31.25 dps
Definition: Icm426xxDefs.h:1496
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_250dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_250dps
250 dps
Definition: Icm426xxDefs.h:1502
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_2000dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_2000dps
2000 dps
Definition: Icm426xxDefs.h:1508
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_125dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_125dps
125 dps
Definition: Icm426xxDefs.h:1500
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_62dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_62dps
62.5 dps
Definition: Icm426xxDefs.h:1498
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_1000dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_1000dps
1000 dps
Definition: Icm426xxDefs.h:1506
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_500dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_500dps
500 dps
Definition: Icm426xxDefs.h:1504
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_16dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_16dps
15.625 dps
Definition: Icm426xxDefs.h:1494
BIT_SIGNAL_PATH_RESET_DMP_INIT_POS
#define BIT_SIGNAL_PATH_RESET_DMP_INIT_POS
Definition: Icm426xxDefs.h:539
BIT_SMD_CONFIG_WOM_MODE_POS
#define BIT_SMD_CONFIG_WOM_MODE_POS
Definition: Icm426xxDefs.h:1038
ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_t
ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_t
Definition: Icm426xxDefs.h:818
ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_2ND_ORDER
@ ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_2ND_ORDER
Definition: Icm426xxDefs.h:821
ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_3RD_ORDER
@ ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_3RD_ORDER
Definition: Icm426xxDefs.h:823
ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_1ST_ORDER
@ ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_1ST_ORDER
Definition: Icm426xxDefs.h:819
BIT_RTC_MODE_POS
#define BIT_RTC_MODE_POS
Definition: Icm426xxDefs.h:649
ICM426XX_APEX_DATA3_ACTIVITY_CLASS_t
ICM426XX_APEX_DATA3_ACTIVITY_CLASS_t
Definition: Icm426xxDefs.h:448
ICM426XX_APEX_DATA3_ACTIVITY_CLASS_OTHER
@ ICM426XX_APEX_DATA3_ACTIVITY_CLASS_OTHER
Definition: Icm426xxDefs.h:449
ICM426XX_APEX_DATA3_ACTIVITY_CLASS_WALK
@ ICM426XX_APEX_DATA3_ACTIVITY_CLASS_WALK
Definition: Icm426xxDefs.h:450
ICM426XX_APEX_DATA3_ACTIVITY_CLASS_RUN
@ ICM426XX_APEX_DATA3_ACTIVITY_CLASS_RUN
Definition: Icm426xxDefs.h:451
BIT_OIS2_CONFIG1_ACCEL_EN_POS
#define BIT_OIS2_CONFIG1_ACCEL_EN_POS
Definition: Icm426xxDefs.h:1573
ICM426XX_APEX_DATA4_TAP_NUM_t
ICM426XX_APEX_DATA4_TAP_NUM_t
Definition: Icm426xxDefs.h:477
ICM426XX_APEX_DATA4_TAP_NUM_SINGLE
@ ICM426XX_APEX_DATA4_TAP_NUM_SINGLE
Definition: Icm426xxDefs.h:479
ICM426XX_APEX_DATA4_TAP_NUM_DOUBLE
@ ICM426XX_APEX_DATA4_TAP_NUM_DOUBLE
Definition: Icm426xxDefs.h:478
BIT_SPI_MODE_OIS1_POS
#define BIT_SPI_MODE_OIS1_POS
Definition: Icm426xxDefs.h:626
ICM426XX_PWR_MGMT_0_TEMP_t
ICM426XX_PWR_MGMT_0_TEMP_t
Definition: Icm426xxDefs.h:666
ICM426XX_PWR_MGMT_0_TEMP_EN
@ ICM426XX_PWR_MGMT_0_TEMP_EN
Definition: Icm426xxDefs.h:668
ICM426XX_PWR_MGMT_0_TEMP_DIS
@ ICM426XX_PWR_MGMT_0_TEMP_DIS
Definition: Icm426xxDefs.h:667
ICM426XX_FSYNC_CONFIG_UI_SEL_t
ICM426XX_FSYNC_CONFIG_UI_SEL_t
Definition: Icm426xxDefs.h:1127
ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_X
@ ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_X
Definition: Icm426xxDefs.h:1133
ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_X
@ ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_X
Definition: Icm426xxDefs.h:1130
ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_Z
@ ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_Z
Definition: Icm426xxDefs.h:1132
ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_Z
@ ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_Z
Definition: Icm426xxDefs.h:1135
ICM426XX_FSYNC_CONFIG_UI_SEL_NO
@ ICM426XX_FSYNC_CONFIG_UI_SEL_NO
Definition: Icm426xxDefs.h:1128
ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_Y
@ ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_Y
Definition: Icm426xxDefs.h:1131
ICM426XX_FSYNC_CONFIG_UI_SEL_TEMP
@ ICM426XX_FSYNC_CONFIG_UI_SEL_TEMP
Definition: Icm426xxDefs.h:1129
ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_Y
@ ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_Y
Definition: Icm426xxDefs.h:1134
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_t
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_t
OIS2 accelerometer FSR selection.
Definition: Icm426xxDefs.h:1617
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_2g
@ ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_2g
2g
Definition: Icm426xxDefs.h:1619
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_8g
@ ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_8g
8g
Definition: Icm426xxDefs.h:1621
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_RESERVED
@ ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_RESERVED
Definition: Icm426xxDefs.h:1618
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_16g
@ ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_16g
16g
Definition: Icm426xxDefs.h:1622
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_4g
@ ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_4g
4g
Definition: Icm426xxDefs.h:1620
BIT_PWR_MGMT_0_TEMP_POS
#define BIT_PWR_MGMT_0_TEMP_POS
Definition: Icm426xxDefs.h:663
ICM426XX_APEX_CONFIG8_TAP_TAVG_t
ICM426XX_APEX_CONFIG8_TAP_TAVG_t
Definition: Icm426xxDefs.h:2133
ICM426XX_APEX_CONFIG8_TAP_TAVG_4SAMPLE
@ ICM426XX_APEX_CONFIG8_TAP_TAVG_4SAMPLE
Definition: Icm426xxDefs.h:2136
ICM426XX_APEX_CONFIG8_TAP_TAVG_2SAMPLE
@ ICM426XX_APEX_CONFIG8_TAP_TAVG_2SAMPLE
Definition: Icm426xxDefs.h:2135
ICM426XX_APEX_CONFIG8_TAP_TAVG_1SAMPLE
@ ICM426XX_APEX_CONFIG8_TAP_TAVG_1SAMPLE
Definition: Icm426xxDefs.h:2134
ICM426XX_APEX_CONFIG8_TAP_TAVG_8SAMPLE
@ ICM426XX_APEX_CONFIG8_TAP_TAVG_8SAMPLE
Definition: Icm426xxDefs.h:2137
BIT_APEX_CONFIG0_TAP_ENABLE_POS
#define BIT_APEX_CONFIG0_TAP_ENABLE_POS
Definition: Icm426xxDefs.h:949
BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS
#define BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS
Definition: Icm426xxDefs.h:1911
ICM426XX_APEX_CONFIG0_R2W_EN_t
ICM426XX_APEX_CONFIG0_R2W_EN_t
Definition: Icm426xxDefs.h:972
ICM426XX_APEX_CONFIG0_R2W_EN_EN
@ ICM426XX_APEX_CONFIG0_R2W_EN_EN
Definition: Icm426xxDefs.h:973
ICM426XX_APEX_CONFIG0_R2W_EN_DIS
@ ICM426XX_APEX_CONFIG0_R2W_EN_DIS
Definition: Icm426xxDefs.h:974
ICM426XX_APEX_DATA4_TAP_AXIS_t
ICM426XX_APEX_DATA4_TAP_AXIS_t
Definition: Icm426xxDefs.h:485
ICM426XX_APEX_DATA4_TAP_AXIS_X
@ ICM426XX_APEX_DATA4_TAP_AXIS_X
Definition: Icm426xxDefs.h:488
ICM426XX_APEX_DATA4_TAP_AXIS_Y
@ ICM426XX_APEX_DATA4_TAP_AXIS_Y
Definition: Icm426xxDefs.h:487
ICM426XX_APEX_DATA4_TAP_AXIS_Z
@ ICM426XX_APEX_DATA4_TAP_AXIS_Z
Definition: Icm426xxDefs.h:486
ICM426XX_APEX_CONFIG0_PEDO_EN_t
ICM426XX_APEX_CONFIG0_PEDO_EN_t
Definition: Icm426xxDefs.h:961
ICM426XX_APEX_CONFIG0_PEDO_EN_DIS
@ ICM426XX_APEX_CONFIG0_PEDO_EN_DIS
Definition: Icm426xxDefs.h:963
ICM426XX_APEX_CONFIG0_PEDO_EN_EN
@ ICM426XX_APEX_CONFIG0_PEDO_EN_EN
Definition: Icm426xxDefs.h:962
BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS
#define BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS
Definition: Icm426xxDefs.h:1612
ICM426XX_OIS1_CONFIG1_DEC_t
ICM426XX_OIS1_CONFIG1_DEC_t
OIS1 rate selection (base clock fixed by OTP divided by decimator value)
Definition: Icm426xxDefs.h:1455
ICM426XX_OIS1_CONFIG1_DEC_16
@ ICM426XX_OIS1_CONFIG1_DEC_16
OTP_OIS_clock / 16.
Definition: Icm426xxDefs.h:1460
ICM426XX_OIS1_CONFIG1_DEC_32
@ ICM426XX_OIS1_CONFIG1_DEC_32
OTP_OIS_clock / 32.
Definition: Icm426xxDefs.h:1461
ICM426XX_OIS1_CONFIG1_DEC_4
@ ICM426XX_OIS1_CONFIG1_DEC_4
OTP_OIS_clock / 4.
Definition: Icm426xxDefs.h:1458
ICM426XX_OIS1_CONFIG1_DEC_8
@ ICM426XX_OIS1_CONFIG1_DEC_8
OTP_OIS_clock / 8.
Definition: Icm426xxDefs.h:1459
ICM426XX_OIS1_CONFIG1_DEC_1
@ ICM426XX_OIS1_CONFIG1_DEC_1
OTP_OIS_clock / 1.
Definition: Icm426xxDefs.h:1456
ICM426XX_OIS1_CONFIG1_DEC_2
@ ICM426XX_OIS1_CONFIG1_DEC_2
OTP_OIS_clock / 2.
Definition: Icm426xxDefs.h:1457
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t
Definition: Icm426xxDefs.h:860
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_8
@ ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_8
Definition: Icm426xxDefs.h:865
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_20
@ ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_20
Definition: Icm426xxDefs.h:862
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_16
@ ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_16
Definition: Icm426xxDefs.h:863
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_40
@ ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_40
Definition: Icm426xxDefs.h:861
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_5
@ ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_5
Definition: Icm426xxDefs.h:866
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_2
@ ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_2
Definition: Icm426xxDefs.h:868
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_4
@ ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_4
Definition: Icm426xxDefs.h:867
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_10
@ ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_10
Definition: Icm426xxDefs.h:864
ICM426XX_APEX_CONFIG0_TAP_ENABLE_t
ICM426XX_APEX_CONFIG0_TAP_ENABLE_t
Definition: Icm426xxDefs.h:952
ICM426XX_APEX_CONFIG0_TAP_ENABLE_EN
@ ICM426XX_APEX_CONFIG0_TAP_ENABLE_EN
Definition: Icm426xxDefs.h:953
ICM426XX_APEX_CONFIG0_TAP_ENABLE_DIS
@ ICM426XX_APEX_CONFIG0_TAP_ENABLE_DIS
Definition: Icm426xxDefs.h:954
BIT_FSYNC_CONFIG_UI_SEL_POS
#define BIT_FSYNC_CONFIG_UI_SEL_POS
Definition: Icm426xxDefs.h:1124
BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS
#define BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS
Definition: Icm426xxDefs.h:369
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t
Definition: Icm426xxDefs.h:851
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_16
@ ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_16
Definition: Icm426xxDefs.h:852
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_1
@ ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_1
Definition: Icm426xxDefs.h:853
ICM426XX_SMD_CONFIG_WOM_INT_MODE_t
ICM426XX_SMD_CONFIG_WOM_INT_MODE_t
Definition: Icm426xxDefs.h:1032
ICM426XX_SMD_CONFIG_WOM_INT_MODE_ORED
@ ICM426XX_SMD_CONFIG_WOM_INT_MODE_ORED
Definition: Icm426xxDefs.h:1034
ICM426XX_SMD_CONFIG_WOM_INT_MODE_ANDED
@ ICM426XX_SMD_CONFIG_WOM_INT_MODE_ANDED
Definition: Icm426xxDefs.h:1033
BIT_FIFO_COUNT_ENDIAN_POS
#define BIT_FIFO_COUNT_ENDIAN_POS
Definition: Icm426xxDefs.h:599
ICM426XX_SENSOR_CONFIG2_OIS_MODE_t
ICM426XX_SENSOR_CONFIG2_OIS_MODE_t
Definition: Icm426xxDefs.h:1275
ICM426XX_SENSOR_CONFIG2_OIS_MODE_DIS
@ ICM426XX_SENSOR_CONFIG2_OIS_MODE_DIS
Definition: Icm426xxDefs.h:1278
ICM426XX_SENSOR_CONFIG2_OIS_MODE_8KHZ
@ ICM426XX_SENSOR_CONFIG2_OIS_MODE_8KHZ
Definition: Icm426xxDefs.h:1277
ICM426XX_SENSOR_CONFIG2_OIS_MODE_32KHZ
@ ICM426XX_SENSOR_CONFIG2_OIS_MODE_32KHZ
Definition: Icm426xxDefs.h:1276
BIT_PWR_MGMT_0_IDLE_POS
#define BIT_PWR_MGMT_0_IDLE_POS
Definition: Icm426xxDefs.h:672
BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS
#define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS
Definition: Icm426xxDefs.h:567
BIT_FIFO_CONFIG1_WM_GT_TH_POS
#define BIT_FIFO_CONFIG1_WM_GT_TH_POS
Definition: Icm426xxDefs.h:1065
ICM426XX_TMST_CONFIG_TMST_EN_t
ICM426XX_TMST_CONFIG_TMST_EN_t
Definition: Icm426xxDefs.h:929
ICM426XX_TMST_CONFIG_TMST_DIS
@ ICM426XX_TMST_CONFIG_TMST_DIS
Definition: Icm426xxDefs.h:931
ICM426XX_TMST_CONFIG_TMST_EN
@ ICM426XX_TMST_CONFIG_TMST_EN
Definition: Icm426xxDefs.h:930
BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS
#define BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS
Definition: Icm426xxDefs.h:1815
BIT_SMD_CONFIG_WOM_INT_MODE_POS
#define BIT_SMD_CONFIG_WOM_INT_MODE_POS
Definition: Icm426xxDefs.h:1029
BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS
#define BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS
Definition: Icm426xxDefs.h:1513
ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_t
ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_t
Definition: Icm426xxDefs.h:943
ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_EN
@ ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_EN
Definition: Icm426xxDefs.h:944
ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_DIS
@ ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_DIS
Definition: Icm426xxDefs.h:945
BIT_DATA_ENDIAN_POS
#define BIT_DATA_ENDIAN_POS
Definition: Icm426xxDefs.h:608
ICM426XX_OIS2_CONFIG1_ACCEL_EN_t
ICM426XX_OIS2_CONFIG1_ACCEL_EN_t
Definition: Icm426xxDefs.h:1576
ICM426XX_OIS2_CONFIG1_ACCEL_DIS
@ ICM426XX_OIS2_CONFIG1_ACCEL_DIS
Definition: Icm426xxDefs.h:1578
ICM426XX_OIS2_CONFIG1_ACCEL_EN
@ ICM426XX_OIS2_CONFIG1_ACCEL_EN
Definition: Icm426xxDefs.h:1577
BIT_SPI_MODE_OIS2_POS
#define BIT_SPI_MODE_OIS2_POS
Definition: Icm426xxDefs.h:617
ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t
ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t
Definition: Icm426xxDefs.h:390
ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_PP
@ ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_PP
Definition: Icm426xxDefs.h:391
ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_OD
@ ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_OD
Definition: Icm426xxDefs.h:392
BIT_FIFO_CONFIG1_TEMP_POS
#define BIT_FIFO_CONFIG1_TEMP_POS
Definition: Icm426xxDefs.h:1092
ICM426XX_APEX_DATA4_TAP_DIR_t
ICM426XX_APEX_DATA4_TAP_DIR_t
Definition: Icm426xxDefs.h:494
ICM426XX_APEX_DATA4_TAP_DIR_NEGATIVE
@ ICM426XX_APEX_DATA4_TAP_DIR_NEGATIVE
Definition: Icm426xxDefs.h:496
ICM426XX_APEX_DATA4_TAP_DIR_POSITIVE
@ ICM426XX_APEX_DATA4_TAP_DIR_POSITIVE
Definition: Icm426xxDefs.h:495
ICM426XX_FIFO_CONFIG1_TMST_FSYNC_t
ICM426XX_FIFO_CONFIG1_TMST_FSYNC_t
Definition: Icm426xxDefs.h:1086
ICM426XX_FIFO_CONFIG1_TMST_FSYNC_DIS
@ ICM426XX_FIFO_CONFIG1_TMST_FSYNC_DIS
Definition: Icm426xxDefs.h:1088
ICM426XX_FIFO_CONFIG1_TMST_FSYNC_EN
@ ICM426XX_FIFO_CONFIG1_TMST_FSYNC_EN
Definition: Icm426xxDefs.h:1087
ICM426XX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t
ICM426XX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t
Definition: Icm426xxDefs.h:602
ICM426XX_INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN
@ ICM426XX_INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN
Definition: Icm426xxDefs.h:604
ICM426XX_INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN
@ ICM426XX_INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN
Definition: Icm426xxDefs.h:603
ICM426XX_PWR_MGMT_0_IDLE_t
ICM426XX_PWR_MGMT_0_IDLE_t
Definition: Icm426xxDefs.h:675
ICM426XX_PWR_MGMT_0_IDLE_DIS
@ ICM426XX_PWR_MGMT_0_IDLE_DIS
Definition: Icm426xxDefs.h:676
ICM426XX_PWR_MGMT_0_IDLE_EN
@ ICM426XX_PWR_MGMT_0_IDLE_EN
Definition: Icm426xxDefs.h:677
ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_t
ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_t
Definition: Icm426xxDefs.h:880
ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_1ST_ORDER
@ ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_1ST_ORDER
Definition: Icm426xxDefs.h:881
ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_2ND_ORDER
@ ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_2ND_ORDER
Definition: Icm426xxDefs.h:883
ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_3RD_ORDER
@ ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_3RD_ORDER
Definition: Icm426xxDefs.h:885
BIT_ACCEL_LP_CLK_SEL_POS
#define BIT_ACCEL_LP_CLK_SEL_POS
Definition: Icm426xxDefs.h:640
ICM426XX_SMD_CONFIG_SMD_MODE_t
ICM426XX_SMD_CONFIG_SMD_MODE_t
Definition: Icm426xxDefs.h:1050
ICM426XX_SMD_CONFIG_SMD_MODE_WOM
@ ICM426XX_SMD_CONFIG_SMD_MODE_WOM
Definition: Icm426xxDefs.h:1053
ICM426XX_SMD_CONFIG_SMD_MODE_DISABLED
@ ICM426XX_SMD_CONFIG_SMD_MODE_DISABLED
Definition: Icm426xxDefs.h:1054
ICM426XX_SMD_CONFIG_SMD_MODE_LONG
@ ICM426XX_SMD_CONFIG_SMD_MODE_LONG
Definition: Icm426xxDefs.h:1051
ICM426XX_SMD_CONFIG_SMD_MODE_SHORT
@ ICM426XX_SMD_CONFIG_SMD_MODE_SHORT
Definition: Icm426xxDefs.h:1052
ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_t
ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_t
Definition: Icm426xxDefs.h:561
ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_DIS
@ ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_DIS
Definition: Icm426xxDefs.h:563
ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_EN
@ ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_EN
Definition: Icm426xxDefs.h:562
BIT_FIFO_CONFIG1_HIRES_POS
#define BIT_FIFO_CONFIG1_HIRES_POS
Definition: Icm426xxDefs.h:1074
BIT_APEX_CONFIG0_PEDO_EN_POS
#define BIT_APEX_CONFIG0_PEDO_EN_POS
Definition: Icm426xxDefs.h:958
BIT_INT_TPULSE_DURATION_POS
#define BIT_INT_TPULSE_DURATION_POS
Definition: Icm426xxDefs.h:1144
ICM426XX_SMD_CONFIG_WOM_MODE_t
ICM426XX_SMD_CONFIG_WOM_MODE_t
Definition: Icm426xxDefs.h:1041
ICM426XX_SMD_CONFIG_WOM_MODE_CMP_INIT
@ ICM426XX_SMD_CONFIG_WOM_MODE_CMP_INIT
Definition: Icm426xxDefs.h:1043
ICM426XX_SMD_CONFIG_WOM_MODE_CMP_PREV
@ ICM426XX_SMD_CONFIG_WOM_MODE_CMP_PREV
Definition: Icm426xxDefs.h:1042
ICM426XX_INTF_CONFIG4_AUX1_SPI_t
ICM426XX_INTF_CONFIG4_AUX1_SPI_t
Definition: Icm426xxDefs.h:1351
ICM426XX_INTF_CONFIG4_AUX1_SPI4W
@ ICM426XX_INTF_CONFIG4_AUX1_SPI4W
Definition: Icm426xxDefs.h:1352
ICM426XX_INTF_CONFIG4_AUX1_SPI3W
@ ICM426XX_INTF_CONFIG4_AUX1_SPI3W
Definition: Icm426xxDefs.h:1353
ICM426XX_PWR_MGMT_0_GYRO_MODE_t
ICM426XX_PWR_MGMT_0_GYRO_MODE_t
Definition: Icm426xxDefs.h:684
ICM426XX_PWR_MGMT_0_GYRO_MODE_STANDBY
@ ICM426XX_PWR_MGMT_0_GYRO_MODE_STANDBY
Definition: Icm426xxDefs.h:686
ICM426XX_PWR_MGMT_0_GYRO_MODE_OFF
@ ICM426XX_PWR_MGMT_0_GYRO_MODE_OFF
Definition: Icm426xxDefs.h:687
ICM426XX_PWR_MGMT_0_GYRO_MODE_LN
@ ICM426XX_PWR_MGMT_0_GYRO_MODE_LN
Definition: Icm426xxDefs.h:685
BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS
#define BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS
Definition: Icm426xxDefs.h:899
BIT_DEVICE_CONFIG_SPI_MODE_POS
#define BIT_DEVICE_CONFIG_SPI_MODE_POS
Definition: Icm426xxDefs.h:332
BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS
#define BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS
Definition: Icm426xxDefs.h:815
ICM426XX_INT_TDEASSERT_t
ICM426XX_INT_TDEASSERT_t
Definition: Icm426xxDefs.h:1156
ICM426XX_INT_TDEASSERT_DISABLED
@ ICM426XX_INT_TDEASSERT_DISABLED
Definition: Icm426xxDefs.h:1157
ICM426XX_INT_TDEASSERT_ENABLED
@ ICM426XX_INT_TDEASSERT_ENABLED
Definition: Icm426xxDefs.h:1158
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_t
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_t
Definition: Icm426xxDefs.h:1761
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_34MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_34MG
Definition: Icm426xxDefs.h:1763
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_54MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_54MG
Definition: Icm426xxDefs.h:1768
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_90MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_90MG
Definition: Icm426xxDefs.h:1777
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_30MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_30MG
Definition: Icm426xxDefs.h:1762
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_62MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_62MG
Definition: Icm426xxDefs.h:1770
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_74MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_74MG
Definition: Icm426xxDefs.h:1773
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_42MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_42MG
Definition: Icm426xxDefs.h:1765
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_70MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_70MG
Definition: Icm426xxDefs.h:1772
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_38MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_38MG
Definition: Icm426xxDefs.h:1764
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_78MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_78MG
Definition: Icm426xxDefs.h:1774
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_50MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_50MG
Definition: Icm426xxDefs.h:1767
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_66MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_66MG
Definition: Icm426xxDefs.h:1771
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_46MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_46MG
Definition: Icm426xxDefs.h:1766
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_82MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_82MG
Definition: Icm426xxDefs.h:1775
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_86MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_86MG
Definition: Icm426xxDefs.h:1776
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_58MG
@ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_58MG
Definition: Icm426xxDefs.h:1769
BIT_PWR_MGMT_0_GYRO_MODE_POS
#define BIT_PWR_MGMT_0_GYRO_MODE_POS
Definition: Icm426xxDefs.h:681
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t
Definition: Icm426xxDefs.h:1915
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_24S
@ ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_24S
Definition: Icm426xxDefs.h:1928
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_6S
@ ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_6S
Definition: Icm426xxDefs.h:1924
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_96S
@ ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_96S
Definition: Icm426xxDefs.h:1920
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_92S
@ ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_92S
Definition: Icm426xxDefs.h:1926
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_56S
@ ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_56S
Definition: Icm426xxDefs.h:1930
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_64S
@ ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_64S
Definition: Icm426xxDefs.h:1918
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_28S
@ ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_28S
Definition: Icm426xxDefs.h:1922
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_32S
@ ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_32S
Definition: Icm426xxDefs.h:1916
BIT_APEX_CONFIG8_TAP_TMAX_POS
#define BIT_APEX_CONFIG8_TAP_TMAX_POS
Definition: Icm426xxDefs.h:2119
BIT_INT_CONFIG_INT2_POLARITY_POS
#define BIT_INT_CONFIG_INT2_POLARITY_POS
Definition: Icm426xxDefs.h:378
BIT_INT_CONFIG1_ASY_RST_POS
#define BIT_INT_CONFIG1_ASY_RST_POS
Definition: Icm426xxDefs.h:1162
ICM426XX_TMST_CONFIG_TMST_FSYNC_EN_t
ICM426XX_TMST_CONFIG_TMST_FSYNC_EN_t
Definition: Icm426xxDefs.h:920
ICM426XX_TMST_CONFIG_TMST_FSYNC_EN
@ ICM426XX_TMST_CONFIG_TMST_FSYNC_EN
Definition: Icm426xxDefs.h:921
ICM426XX_TMST_CONFIG_TMST_FSYNC_DIS
@ ICM426XX_TMST_CONFIG_TMST_FSYNC_DIS
Definition: Icm426xxDefs.h:922
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t
Definition: Icm426xxDefs.h:1657
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_12S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_12S
Definition: Icm426xxDefs.h:1661
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_48S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_48S
Definition: Icm426xxDefs.h:1670
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_36S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_36S
Definition: Icm426xxDefs.h:1667
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_8S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_8S
Definition: Icm426xxDefs.h:1660
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_28S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_28S
Definition: Icm426xxDefs.h:1665
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_24S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_24S
Definition: Icm426xxDefs.h:1664
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_20S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_20S
Definition: Icm426xxDefs.h:1663
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_4S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_4S
Definition: Icm426xxDefs.h:1659
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_16S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_16S
Definition: Icm426xxDefs.h:1662
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_60S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_60S
Definition: Icm426xxDefs.h:1673
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_32S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_32S
Definition: Icm426xxDefs.h:1666
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_44S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_44S
Definition: Icm426xxDefs.h:1669
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_52S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_52S
Definition: Icm426xxDefs.h:1671
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_0S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_0S
Definition: Icm426xxDefs.h:1658
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_56S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_56S
Definition: Icm426xxDefs.h:1672
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_40S
@ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_40S
Definition: Icm426xxDefs.h:1668
ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_t
ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_t
Definition: Icm426xxDefs.h:620
ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_1_2
@ ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_1_2
Definition: Icm426xxDefs.h:621
ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_0_3
@ ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_0_3
Definition: Icm426xxDefs.h:622
ICM426XX_GYRO_CONFIG0_ODR_t
ICM426XX_GYRO_CONFIG0_ODR_t
Gyroscope ODR selection.
Definition: Icm426xxDefs.h:739
ICM426XX_GYRO_CONFIG0_ODR_25_HZ
@ ICM426XX_GYRO_CONFIG0_ODR_25_HZ
25 Hz (40 ms)
Definition: Icm426xxDefs.h:742
ICM426XX_GYRO_CONFIG0_ODR_50_HZ
@ ICM426XX_GYRO_CONFIG0_ODR_50_HZ
50 Hz (20 ms)
Definition: Icm426xxDefs.h:743
ICM426XX_GYRO_CONFIG0_ODR_16_KHZ
@ ICM426XX_GYRO_CONFIG0_ODR_16_KHZ
16 KHz (62.5 us)
Definition: Icm426xxDefs.h:750
ICM426XX_GYRO_CONFIG0_ODR_100_HZ
@ ICM426XX_GYRO_CONFIG0_ODR_100_HZ
100 Hz (10 ms)
Definition: Icm426xxDefs.h:744
ICM426XX_GYRO_CONFIG0_ODR_1_KHZ
@ ICM426XX_GYRO_CONFIG0_ODR_1_KHZ
1 KHz (1 ms)
Definition: Icm426xxDefs.h:746
ICM426XX_GYRO_CONFIG0_ODR_32_KHZ
@ ICM426XX_GYRO_CONFIG0_ODR_32_KHZ
32 KHz (31.25 us)
Definition: Icm426xxDefs.h:751
ICM426XX_GYRO_CONFIG0_ODR_2_KHZ
@ ICM426XX_GYRO_CONFIG0_ODR_2_KHZ
2 KHz (500 us)
Definition: Icm426xxDefs.h:747
ICM426XX_GYRO_CONFIG0_ODR_12_5_HZ
@ ICM426XX_GYRO_CONFIG0_ODR_12_5_HZ
12.5 Hz (80 ms)
Definition: Icm426xxDefs.h:741
ICM426XX_GYRO_CONFIG0_ODR_500_HZ
@ ICM426XX_GYRO_CONFIG0_ODR_500_HZ
500 Hz (2 ms)
Definition: Icm426xxDefs.h:740
ICM426XX_GYRO_CONFIG0_ODR_200_HZ
@ ICM426XX_GYRO_CONFIG0_ODR_200_HZ
200 Hz (5 ms)
Definition: Icm426xxDefs.h:745
ICM426XX_GYRO_CONFIG0_ODR_8_KHZ
@ ICM426XX_GYRO_CONFIG0_ODR_8_KHZ
8 KHz (125 us)
Definition: Icm426xxDefs.h:749
ICM426XX_GYRO_CONFIG0_ODR_4_KHZ
@ ICM426XX_GYRO_CONFIG0_ODR_4_KHZ
4 KHz (250 us)
Definition: Icm426xxDefs.h:748
BIT_APEX_CONFIG0_DMP_ODR_POS
#define BIT_APEX_CONFIG0_DMP_ODR_POS
Definition: Icm426xxDefs.h:1009
BIT_FIFO_CONFIG1_GYRO_POS
#define BIT_FIFO_CONFIG1_GYRO_POS
Definition: Icm426xxDefs.h:1101
ICM426XX_FIFO_CONFIG_MODE_t
ICM426XX_FIFO_CONFIG_MODE_t
Definition: Icm426xxDefs.h:413
ICM426XX_FIFO_CONFIG_MODE_STREAM
@ ICM426XX_FIFO_CONFIG_MODE_STREAM
Definition: Icm426xxDefs.h:415
ICM426XX_FIFO_CONFIG_MODE_BYPASS
@ ICM426XX_FIFO_CONFIG_MODE_BYPASS
Definition: Icm426xxDefs.h:416
ICM426XX_FIFO_CONFIG_MODE_STOP_ON_FULL
@ ICM426XX_FIFO_CONFIG_MODE_STOP_ON_FULL
Definition: Icm426xxDefs.h:414
BIT_GYRO_CONFIG0_FS_SEL_POS
#define BIT_GYRO_CONFIG0_FS_SEL_POS
Definition: Icm426xxDefs.h:706
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t
Definition: Icm426xxDefs.h:1682
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_45MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_45MG
Definition: Icm426xxDefs.h:1689
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_40MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_40MG
Definition: Icm426xxDefs.h:1687
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_75MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_75MG
Definition: Icm426xxDefs.h:1701
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_55MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_55MG
Definition: Icm426xxDefs.h:1693
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_65MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_65MG
Definition: Icm426xxDefs.h:1697
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_80MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_80MG
Definition: Icm426xxDefs.h:1703
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_30MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_30MG
Definition: Icm426xxDefs.h:1683
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_35MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_35MG
Definition: Icm426xxDefs.h:1685
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_60MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_60MG
Definition: Icm426xxDefs.h:1695
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_50MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_50MG
Definition: Icm426xxDefs.h:1691
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_105MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_105MG
Definition: Icm426xxDefs.h:1713
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_95MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_95MG
Definition: Icm426xxDefs.h:1709
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_100MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_100MG
Definition: Icm426xxDefs.h:1711
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_85MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_85MG
Definition: Icm426xxDefs.h:1705
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_90MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_90MG
Definition: Icm426xxDefs.h:1707
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_70MG
@ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_70MG
Definition: Icm426xxDefs.h:1699
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_t
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_t
OIS1 accelerometer FSR selection.
Definition: Icm426xxDefs.h:1518
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_4g
@ ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_4g
4g
Definition: Icm426xxDefs.h:1521
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_8g
@ ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_8g
8g
Definition: Icm426xxDefs.h:1522
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_16g
@ ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_16g
16g
Definition: Icm426xxDefs.h:1523
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_RESERVED
@ ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_RESERVED
Definition: Icm426xxDefs.h:1519
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_2g
@ ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_2g
2g
Definition: Icm426xxDefs.h:1520
BIT_APEX_CONFIG8_TAP_TAVG_POS
#define BIT_APEX_CONFIG8_TAP_TAVG_POS
Definition: Icm426xxDefs.h:2130
ICM426XX_INT_TPULSE_DURATION_t
ICM426XX_INT_TPULSE_DURATION_t
Definition: Icm426xxDefs.h:1147
ICM426XX_INT_TPULSE_DURATION_8_US
@ ICM426XX_INT_TPULSE_DURATION_8_US
Definition: Icm426xxDefs.h:1148
ICM426XX_INT_TPULSE_DURATION_100_US
@ ICM426XX_INT_TPULSE_DURATION_100_US
Definition: Icm426xxDefs.h:1149
BIT_INT_TDEASSERT_POS
#define BIT_INT_TDEASSERT_POS
Definition: Icm426xxDefs.h:1153
BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS
#define BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS
Definition: Icm426xxDefs.h:1488
ICM426XX_ACCEL_CONFIG0_FS_SEL_t
ICM426XX_ACCEL_CONFIG0_FS_SEL_t
Accelerometer FSR selection.
Definition: Icm426xxDefs.h:765
ICM426XX_ACCEL_CONFIG0_FS_SEL_16g
@ ICM426XX_ACCEL_CONFIG0_FS_SEL_16g
16g
Definition: Icm426xxDefs.h:777
ICM426XX_ACCEL_CONFIG0_FS_SEL_2g
@ ICM426XX_ACCEL_CONFIG0_FS_SEL_2g
2g
Definition: Icm426xxDefs.h:774
ICM426XX_ACCEL_CONFIG0_FS_SEL_RESERVED
@ ICM426XX_ACCEL_CONFIG0_FS_SEL_RESERVED
Definition: Icm426xxDefs.h:773
ICM426XX_ACCEL_CONFIG0_FS_SEL_8g
@ ICM426XX_ACCEL_CONFIG0_FS_SEL_8g
8g
Definition: Icm426xxDefs.h:776
ICM426XX_ACCEL_CONFIG0_FS_SEL_4g
@ ICM426XX_ACCEL_CONFIG0_FS_SEL_4g
4g
Definition: Icm426xxDefs.h:775
ICM426XX_FIFO_CONFIG1_ACCEL_t
ICM426XX_FIFO_CONFIG1_ACCEL_t
Definition: Icm426xxDefs.h:1113
ICM426XX_FIFO_CONFIG1_ACCEL_EN
@ ICM426XX_FIFO_CONFIG1_ACCEL_EN
Definition: Icm426xxDefs.h:1114
ICM426XX_FIFO_CONFIG1_ACCEL_DIS
@ ICM426XX_FIFO_CONFIG1_ACCEL_DIS
Definition: Icm426xxDefs.h:1115
ICM426XX_DEVICE_CONFIG_SPI_MODE_t
ICM426XX_DEVICE_CONFIG_SPI_MODE_t
Definition: Icm426xxDefs.h:337
ICM426XX_DEVICE_CONFIG_SPI_MODE_0_3
@ ICM426XX_DEVICE_CONFIG_SPI_MODE_0_3
Definition: Icm426xxDefs.h:339
ICM426XX_DEVICE_CONFIG_SPI_MODE_1_2
@ ICM426XX_DEVICE_CONFIG_SPI_MODE_1_2
Definition: Icm426xxDefs.h:338
BIT_OIS1_CONFIG1_GYRO_EN_POS
#define BIT_OIS1_CONFIG1_GYRO_EN_POS
Definition: Icm426xxDefs.h:1465
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t
Definition: Icm426xxDefs.h:1818
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_225_SAMPLES
@ ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_225_SAMPLES
Definition: Icm426xxDefs.h:1833
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_50_SAMPLES
@ ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_50_SAMPLES
Definition: Icm426xxDefs.h:1819
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_200_SAMPLES
@ ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_200_SAMPLES
Definition: Icm426xxDefs.h:1831
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_150_SAMPLES
@ ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_150_SAMPLES
Definition: Icm426xxDefs.h:1827
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_125_SAMPLES
@ ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_125_SAMPLES
Definition: Icm426xxDefs.h:1825
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_175_SAMPLES
@ ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_175_SAMPLES
Definition: Icm426xxDefs.h:1829
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_75_SAMPLES
@ ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_75_SAMPLES
Definition: Icm426xxDefs.h:1821
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_100_SAMPLES
@ ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_100_SAMPLES
Definition: Icm426xxDefs.h:1823
ICM426XX_INTF_CONFIG0_DATA_ENDIAN_t
ICM426XX_INTF_CONFIG0_DATA_ENDIAN_t
Definition: Icm426xxDefs.h:611
ICM426XX_INTF_CONFIG0_DATA_BIG_ENDIAN
@ ICM426XX_INTF_CONFIG0_DATA_BIG_ENDIAN
Definition: Icm426xxDefs.h:612
ICM426XX_INTF_CONFIG0_DATA_LITTLE_ENDIAN
@ ICM426XX_INTF_CONFIG0_DATA_LITTLE_ENDIAN
Definition: Icm426xxDefs.h:613
BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS
#define BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS
Definition: Icm426xxDefs.h:387
ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_t
ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_t
Definition: Icm426xxDefs.h:551
ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_DIS
@ ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_DIS
Definition: Icm426xxDefs.h:553
ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN
@ ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN
Definition: Icm426xxDefs.h:552
BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS
#define BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS
Definition: Icm426xxDefs.h:558
ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_t
ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_t
Definition: Icm426xxDefs.h:1543
ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC
@ ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC
Definition: Icm426xxDefs.h:1544
ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC
@ ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC
Definition: Icm426xxDefs.h:1545
BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS
#define BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS
Definition: Icm426xxDefs.h:548
ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t
ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t
Definition: Icm426xxDefs.h:584
ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_EN
@ ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_EN
Definition: Icm426xxDefs.h:586
ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_DIS
@ ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_DIS
Definition: Icm426xxDefs.h:585
ICM426XX_ACCEL_AAF_DIS_t
ICM426XX_ACCEL_AAF_DIS_t
Definition: Icm426xxDefs.h:1404
ICM426XX_ACCEL_AAF_DIS
@ ICM426XX_ACCEL_AAF_DIS
Definition: Icm426xxDefs.h:1406
ICM426XX_ACCEL_AAF_EN
@ ICM426XX_ACCEL_AAF_EN
Definition: Icm426xxDefs.h:1405
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t
Definition: Icm426xxDefs.h:1893
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_5
@ ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_5
Definition: Icm426xxDefs.h:1899
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_4
@ ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_4
Definition: Icm426xxDefs.h:1898
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_0
@ ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_0
Definition: Icm426xxDefs.h:1894
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_7
@ ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_7
Definition: Icm426xxDefs.h:1901
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_3
@ ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_3
Definition: Icm426xxDefs.h:1897
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_1
@ ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_1
Definition: Icm426xxDefs.h:1895
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_6
@ ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_6
Definition: Icm426xxDefs.h:1900
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_2
@ ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_2
Definition: Icm426xxDefs.h:1896
BIT_APEX_DATA4_TAP_NUM_POS
#define BIT_APEX_DATA4_TAP_NUM_POS
TAP status flags: non-zero value - tap detected bit0 - positive or negative edge bit1 and 2 - axis de...
Definition: Icm426xxDefs.h:475
BIT_APEX_CONFIG0_R2W_EN_POS
#define BIT_APEX_CONFIG0_R2W_EN_POS
Definition: Icm426xxDefs.h:969
BIT_TMST_CONFIG_TMST_FSYNC_POS
#define BIT_TMST_CONFIG_TMST_FSYNC_POS
Definition: Icm426xxDefs.h:917
ICM426XX_FIFO_CONFIG1_WM_GT_t
ICM426XX_FIFO_CONFIG1_WM_GT_t
Definition: Icm426xxDefs.h:1068
ICM426XX_FIFO_CONFIG1_WM_GT_TH_DIS
@ ICM426XX_FIFO_CONFIG1_WM_GT_TH_DIS
Definition: Icm426xxDefs.h:1070
ICM426XX_FIFO_CONFIG1_WM_GT_TH_EN
@ ICM426XX_FIFO_CONFIG1_WM_GT_TH_EN
Definition: Icm426xxDefs.h:1069
ICM426XX_OIS2_CONFIG1_GYRO_EN_t
ICM426XX_OIS2_CONFIG1_GYRO_EN_t
Definition: Icm426xxDefs.h:1567
ICM426XX_OIS2_CONFIG1_GYRO_DIS
@ ICM426XX_OIS2_CONFIG1_GYRO_DIS
Definition: Icm426xxDefs.h:1569
ICM426XX_OIS2_CONFIG1_GYRO_EN
@ ICM426XX_OIS2_CONFIG1_GYRO_EN
Definition: Icm426xxDefs.h:1568
BIT_TMST_CONFIG_RESOL_POS
#define BIT_TMST_CONFIG_RESOL_POS
Definition: Icm426xxDefs.h:908
BIT_FIFO_CONFIG_MODE_POS
#define BIT_FIFO_CONFIG_MODE_POS
Definition: Icm426xxDefs.h:410
ICM426XX_DEVICE_CONFIG_RESET_t
ICM426XX_DEVICE_CONFIG_RESET_t
Definition: Icm426xxDefs.h:353
ICM426XX_DEVICE_CONFIG_RESET_NONE
@ ICM426XX_DEVICE_CONFIG_RESET_NONE
Definition: Icm426xxDefs.h:355
ICM426XX_DEVICE_CONFIG_RESET_EN
@ ICM426XX_DEVICE_CONFIG_RESET_EN
Definition: Icm426xxDefs.h:354
ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_t
ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_t
Definition: Icm426xxDefs.h:1859
ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_0S
@ ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_0S
Definition: Icm426xxDefs.h:1860
ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_2S
@ ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_2S
Definition: Icm426xxDefs.h:1861
ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_6S
@ ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_6S
Definition: Icm426xxDefs.h:1863
ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_4S
@ ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_4S
Definition: Icm426xxDefs.h:1862
BIT_ACCEL_AAF_DIS_POS
#define BIT_ACCEL_AAF_DIS_POS
Definition: Icm426xxDefs.h:1401
ICM426XX_OIS2_CONFIG1_DEC_t
ICM426XX_OIS2_CONFIG1_DEC_t
OIS2 rate selection (base clock fixed by OTP divided by decimator value)
Definition: Icm426xxDefs.h:1554
ICM426XX_OIS2_CONFIG1_DEC_4
@ ICM426XX_OIS2_CONFIG1_DEC_4
OTP_OIS_clock / 4.
Definition: Icm426xxDefs.h:1557
ICM426XX_OIS2_CONFIG1_DEC_16
@ ICM426XX_OIS2_CONFIG1_DEC_16
OTP_OIS_clock / 16.
Definition: Icm426xxDefs.h:1559
ICM426XX_OIS2_CONFIG1_DEC_8
@ ICM426XX_OIS2_CONFIG1_DEC_8
OTP_OIS_clock / 8.
Definition: Icm426xxDefs.h:1558
ICM426XX_OIS2_CONFIG1_DEC_2
@ ICM426XX_OIS2_CONFIG1_DEC_2
OTP_OIS_clock / 2.
Definition: Icm426xxDefs.h:1556
ICM426XX_OIS2_CONFIG1_DEC_32
@ ICM426XX_OIS2_CONFIG1_DEC_32
OTP_OIS_clock / 32.
Definition: Icm426xxDefs.h:1560
ICM426XX_OIS2_CONFIG1_DEC_1
@ ICM426XX_OIS2_CONFIG1_DEC_1
OTP_OIS_clock / 1.
Definition: Icm426xxDefs.h:1555
ICM426XX_GYRO_CONFIG0_FS_SEL_t
ICM426XX_GYRO_CONFIG0_FS_SEL_t
Gyroscope FSR selection.
Definition: Icm426xxDefs.h:711
ICM426XX_GYRO_CONFIG0_FS_SEL_2000dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_2000dps
2000dps
Definition: Icm426xxDefs.h:729
ICM426XX_GYRO_CONFIG0_FS_SEL_125dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_125dps
125dps
Definition: Icm426xxDefs.h:725
ICM426XX_GYRO_CONFIG0_FS_SEL_500dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_500dps
500dps
Definition: Icm426xxDefs.h:727
ICM426XX_GYRO_CONFIG0_FS_SEL_16dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_16dps
16dps
Definition: Icm426xxDefs.h:722
ICM426XX_GYRO_CONFIG0_FS_SEL_62dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_62dps
62dps
Definition: Icm426xxDefs.h:724
ICM426XX_GYRO_CONFIG0_FS_SEL_250dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_250dps
250dps
Definition: Icm426xxDefs.h:726
ICM426XX_GYRO_CONFIG0_FS_SEL_1000dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_1000dps
1000dps
Definition: Icm426xxDefs.h:728
ICM426XX_GYRO_CONFIG0_FS_SEL_31dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_31dps
31dps
Definition: Icm426xxDefs.h:723
BIT_FIFO_CONFIG1_TMST_FSYNC_POS
#define BIT_FIFO_CONFIG1_TMST_FSYNC_POS
Definition: Icm426xxDefs.h:1083
ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_t
ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_t
Definition: Icm426xxDefs.h:570
ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_DIS
@ ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_DIS
Definition: Icm426xxDefs.h:572
ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_EN
@ ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_EN
Definition: Icm426xxDefs.h:571
ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_t
ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_t
Definition: Icm426xxDefs.h:2161
ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_NORMAL
@ ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_NORMAL
Definition: Icm426xxDefs.h:2162
ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_RESERVED
@ ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_RESERVED
Definition: Icm426xxDefs.h:2163
BIT_INTF_CONFIG4_AUX1_SPI_POS
#define BIT_INTF_CONFIG4_AUX1_SPI_POS
Definition: Icm426xxDefs.h:1348
BIT_APEX_DATA3_DMP_IDLE_POS
#define BIT_APEX_DATA3_DMP_IDLE_POS
Definition: Icm426xxDefs.h:455
BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS
#define BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS
Definition: Icm426xxDefs.h:1678
BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS
#define BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS
Definition: Icm426xxDefs.h:1540
BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS
#define BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS
Definition: Icm426xxDefs.h:1856
ICM426XX_INTF_CONFIG4_AP_SPI_t
ICM426XX_INTF_CONFIG4_AP_SPI_t
Definition: Icm426xxDefs.h:1342
ICM426XX_INTF_CONFIG4_AP_SPI4W
@ ICM426XX_INTF_CONFIG4_AP_SPI4W
Definition: Icm426xxDefs.h:1343
ICM426XX_INTF_CONFIG4_AP_SPI3W
@ ICM426XX_INTF_CONFIG4_AP_SPI3W
Definition: Icm426xxDefs.h:1344
ICM426XX_GYRO_AAF_DIS_t
ICM426XX_GYRO_AAF_DIS_t
Definition: Icm426xxDefs.h:1290
ICM426XX_GYRO_AAF_DIS
@ ICM426XX_GYRO_AAF_DIS
Definition: Icm426xxDefs.h:1292
ICM426XX_GYRO_AAF_EN
@ ICM426XX_GYRO_AAF_EN
Definition: Icm426xxDefs.h:1291
ICM426XX_INT_CONFIG_INT1_POLARITY_t
ICM426XX_INT_CONFIG_INT1_POLARITY_t
Definition: Icm426xxDefs.h:399
ICM426XX_INT_CONFIG_INT1_POLARITY_LOW
@ ICM426XX_INT_CONFIG_INT1_POLARITY_LOW
Definition: Icm426xxDefs.h:401
ICM426XX_INT_CONFIG_INT1_POLARITY_HIGH
@ ICM426XX_INT_CONFIG_INT1_POLARITY_HIGH
Definition: Icm426xxDefs.h:400
BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS
#define BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS
Definition: Icm426xxDefs.h:1441
BIT_OIS1_CONFIG1_ACCEL_EN_POS
#define BIT_OIS1_CONFIG1_ACCEL_EN_POS
Definition: Icm426xxDefs.h:1474
ICM426XX_INTF_CONFIG1_RTC_MODE_t
ICM426XX_INTF_CONFIG1_RTC_MODE_t
Definition: Icm426xxDefs.h:652
ICM426XX_INTF_CONFIG1_RTC_MODE_EN
@ ICM426XX_INTF_CONFIG1_RTC_MODE_EN
Definition: Icm426xxDefs.h:654
ICM426XX_INTF_CONFIG1_RTC_MODE_DIS
@ ICM426XX_INTF_CONFIG1_RTC_MODE_DIS
Definition: Icm426xxDefs.h:653
BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS
#define BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS
Definition: Icm426xxDefs.h:877
ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t
ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t
Definition: Icm426xxDefs.h:2106
ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_25
@ ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_25
Definition: Icm426xxDefs.h:2108
ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_50
@ ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_50
Definition: Icm426xxDefs.h:2110
ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_12
@ ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_12
Definition: Icm426xxDefs.h:2107
ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_37
@ ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_37
Definition: Icm426xxDefs.h:2109
ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_t
ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_t
Definition: Icm426xxDefs.h:372
ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_PP
@ ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_PP
Definition: Icm426xxDefs.h:373
ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_OD
@ ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_OD
Definition: Icm426xxDefs.h:374
ICM426XX_APEX_DATA3_DMP_IDLE_OFF_t
ICM426XX_APEX_DATA3_DMP_IDLE_OFF_t
Definition: Icm426xxDefs.h:458
ICM426XX_APEX_DATA3_DMP_IDLE_ON
@ ICM426XX_APEX_DATA3_DMP_IDLE_ON
Definition: Icm426xxDefs.h:459
ICM426XX_APEX_DATA3_DMP_IDLE_OFF
@ ICM426XX_APEX_DATA3_DMP_IDLE_OFF
Definition: Icm426xxDefs.h:460
BIT_FIFO_COUNT_REC_POS
#define BIT_FIFO_COUNT_REC_POS
Definition: Icm426xxDefs.h:590
ICM426XX_APEX_CONFIG8_TAP_TMAX_t
ICM426XX_APEX_CONFIG8_TAP_TMAX_t
Definition: Icm426xxDefs.h:2122
ICM426XX_APEX_CONFIG8_TAP_TMAX_625MS
@ ICM426XX_APEX_CONFIG8_TAP_TMAX_625MS
Definition: Icm426xxDefs.h:2126
ICM426XX_APEX_CONFIG8_TAP_TMAX_375MS
@ ICM426XX_APEX_CONFIG8_TAP_TMAX_375MS
Definition: Icm426xxDefs.h:2124
ICM426XX_APEX_CONFIG8_TAP_TMAX_250MS
@ ICM426XX_APEX_CONFIG8_TAP_TMAX_250MS
Definition: Icm426xxDefs.h:2123
ICM426XX_APEX_CONFIG8_TAP_TMAX_500MS
@ ICM426XX_APEX_CONFIG8_TAP_TMAX_500MS
Definition: Icm426xxDefs.h:2125
ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_t
ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_t
Definition: Icm426xxDefs.h:629
ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_0_3
@ ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_0_3
Definition: Icm426xxDefs.h:631
ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_1_2
@ ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_1_2
Definition: Icm426xxDefs.h:630
ICM426XX_APEX_CONFIG0_DMP_ODR_t
ICM426XX_APEX_CONFIG0_DMP_ODR_t
DMP ODR selection.
Definition: Icm426xxDefs.h:1014
ICM426XX_APEX_CONFIG0_DMP_ODR_50Hz
@ ICM426XX_APEX_CONFIG0_DMP_ODR_50Hz
50Hz (20ms)
Definition: Icm426xxDefs.h:1016
ICM426XX_APEX_CONFIG0_DMP_ODR_25Hz
@ ICM426XX_APEX_CONFIG0_DMP_ODR_25Hz
25Hz (40ms)
Definition: Icm426xxDefs.h:1015
ICM426XX_APEX_CONFIG0_DMP_ODR_500Hz
@ ICM426XX_APEX_CONFIG0_DMP_ODR_500Hz
500Hz (40ms)
Definition: Icm426xxDefs.h:1019
ICM426XX_APEX_CONFIG0_DMP_ODR_100Hz
@ ICM426XX_APEX_CONFIG0_DMP_ODR_100Hz
100Hz (10ms)
Definition: Icm426xxDefs.h:1017
BIT_OIS2_CONFIG1_GYRO_EN_POS
#define BIT_OIS2_CONFIG1_GYRO_EN_POS
Definition: Icm426xxDefs.h:1564
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t
Definition: Icm426xxDefs.h:1872
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_5_12S
@ ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_5_12S
Definition: Icm426xxDefs.h:1876
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_1_28S
@ ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_1_28S
Definition: Icm426xxDefs.h:1873
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_2_56S
@ ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_2_56S
Definition: Icm426xxDefs.h:1874
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_10_24S
@ ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_10_24S
Definition: Icm426xxDefs.h:1880
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_8_96S
@ ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_8_96S
Definition: Icm426xxDefs.h:1879
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_3_84S
@ ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_3_84S
Definition: Icm426xxDefs.h:1875
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_6_4S
@ ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_6_4S
Definition: Icm426xxDefs.h:1877
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_7_68S
@ ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_7_68S
Definition: Icm426xxDefs.h:1878
BIT_OIS2_CONFIG1_DEC_POS
#define BIT_OIS2_CONFIG1_DEC_POS
Definition: Icm426xxDefs.h:1549
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_t
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_t
OIS2 gyroscope FSR selection.
Definition: Icm426xxDefs.h:1592
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_1000dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_1000dps
1000 dps
Definition: Icm426xxDefs.h:1605
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_31dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_31dps
31.25 dps
Definition: Icm426xxDefs.h:1595
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_500dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_500dps
500 dps
Definition: Icm426xxDefs.h:1603
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_16dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_16dps
15.625 dps
Definition: Icm426xxDefs.h:1593
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_250dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_250dps
250 dps
Definition: Icm426xxDefs.h:1601
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_2000dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_2000dps
2000 dps
Definition: Icm426xxDefs.h:1607
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_62dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_62dps
62.5 dps
Definition: Icm426xxDefs.h:1597
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_125dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_125dps
125 dps
Definition: Icm426xxDefs.h:1599
ICM426XX_FIFO_CONFIG1_TEMP_t
ICM426XX_FIFO_CONFIG1_TEMP_t
Definition: Icm426xxDefs.h:1095
ICM426XX_FIFO_CONFIG1_TEMP_EN
@ ICM426XX_FIFO_CONFIG1_TEMP_EN
Definition: Icm426xxDefs.h:1096
ICM426XX_FIFO_CONFIG1_TEMP_DIS
@ ICM426XX_FIFO_CONFIG1_TEMP_DIS
Definition: Icm426xxDefs.h:1097
ICM426XX_FIFO_CONFIG1_GYRO_t
ICM426XX_FIFO_CONFIG1_GYRO_t
Definition: Icm426xxDefs.h:1104
ICM426XX_FIFO_CONFIG1_GYRO_DIS
@ ICM426XX_FIFO_CONFIG1_GYRO_DIS
Definition: Icm426xxDefs.h:1106
ICM426XX_FIFO_CONFIG1_GYRO_EN
@ ICM426XX_FIFO_CONFIG1_GYRO_EN
Definition: Icm426xxDefs.h:1105
ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_t
ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_t
Definition: Icm426xxDefs.h:643
ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_WUOSC
@ ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_WUOSC
Definition: Icm426xxDefs.h:644
ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_RCOSC
@ ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_RCOSC
Definition: Icm426xxDefs.h:645
ICM426XX_ACCEL_CONFIG0_ODR_t
ICM426XX_ACCEL_CONFIG0_ODR_t
Accelerometer ODR selection.
Definition: Icm426xxDefs.h:787
ICM426XX_ACCEL_CONFIG0_ODR_1_KHZ
@ ICM426XX_ACCEL_CONFIG0_ODR_1_KHZ
1 KHz (1 ms)
Definition: Icm426xxDefs.h:797
ICM426XX_ACCEL_CONFIG0_ODR_2_KHZ
@ ICM426XX_ACCEL_CONFIG0_ODR_2_KHZ
2 KHz (500 us)
Definition: Icm426xxDefs.h:798
ICM426XX_ACCEL_CONFIG0_ODR_8_KHZ
@ ICM426XX_ACCEL_CONFIG0_ODR_8_KHZ
8 KHz (125 us)
Definition: Icm426xxDefs.h:800
ICM426XX_ACCEL_CONFIG0_ODR_1_5625_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_1_5625_HZ
1.5625 Hz (640 ms)
Definition: Icm426xxDefs.h:789
ICM426XX_ACCEL_CONFIG0_ODR_50_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_50_HZ
50 Hz (20 ms)
Definition: Icm426xxDefs.h:794
ICM426XX_ACCEL_CONFIG0_ODR_12_5_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_12_5_HZ
12.5 Hz (80 ms)
Definition: Icm426xxDefs.h:792
ICM426XX_ACCEL_CONFIG0_ODR_200_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_200_HZ
200 Hz (5 ms)
Definition: Icm426xxDefs.h:796
ICM426XX_ACCEL_CONFIG0_ODR_6_25_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_6_25_HZ
6.25 Hz (160 ms)
Definition: Icm426xxDefs.h:791
ICM426XX_ACCEL_CONFIG0_ODR_32_KHZ
@ ICM426XX_ACCEL_CONFIG0_ODR_32_KHZ
32 KHz (31.25 us)
Definition: Icm426xxDefs.h:802
ICM426XX_ACCEL_CONFIG0_ODR_500_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_500_HZ
500 Hz (2 ms)
Definition: Icm426xxDefs.h:788
ICM426XX_ACCEL_CONFIG0_ODR_25_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_25_HZ
25 Hz (40 ms)
Definition: Icm426xxDefs.h:793
ICM426XX_ACCEL_CONFIG0_ODR_100_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_100_HZ
100 Hz (10 ms)
Definition: Icm426xxDefs.h:795
ICM426XX_ACCEL_CONFIG0_ODR_3_125_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_3_125_HZ
3.125 Hz (320 ms)
Definition: Icm426xxDefs.h:790
ICM426XX_ACCEL_CONFIG0_ODR_4_KHZ
@ ICM426XX_ACCEL_CONFIG0_ODR_4_KHZ
4 KHz (250 us)
Definition: Icm426xxDefs.h:799
ICM426XX_ACCEL_CONFIG0_ODR_16_KHZ
@ ICM426XX_ACCEL_CONFIG0_ODR_16_KHZ
16 KHz (62.5 us)
Definition: Icm426xxDefs.h:801
ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_t
ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_t
Definition: Icm426xxDefs.h:593
ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_BYTE
@ ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_BYTE
Definition: Icm426xxDefs.h:595
ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_RECORD
@ ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_RECORD
Definition: Icm426xxDefs.h:594
ICM426XX_TMST_CONFIG_RESOL_t
ICM426XX_TMST_CONFIG_RESOL_t
Definition: Icm426xxDefs.h:911
ICM426XX_TMST_CONFIG_RESOL_16us
@ ICM426XX_TMST_CONFIG_RESOL_16us
Definition: Icm426xxDefs.h:912
ICM426XX_TMST_CONFIG_RESOL_1us
@ ICM426XX_TMST_CONFIG_RESOL_1us
Definition: Icm426xxDefs.h:913
ICM426XX_OIS1_CONFIG1_GYRO_EN_t
ICM426XX_OIS1_CONFIG1_GYRO_EN_t
Definition: Icm426xxDefs.h:1468
ICM426XX_OIS1_CONFIG1_GYRO_DIS
@ ICM426XX_OIS1_CONFIG1_GYRO_DIS
Definition: Icm426xxDefs.h:1470
ICM426XX_OIS1_CONFIG1_GYRO_EN
@ ICM426XX_OIS1_CONFIG1_GYRO_EN
Definition: Icm426xxDefs.h:1469
BIT_FIFO_SREG_INVALID_IND_POS
#define BIT_FIFO_SREG_INVALID_IND_POS
Definition: Icm426xxDefs.h:581
ICM426XX_FIFO_CONFIG1_HIRES_t
ICM426XX_FIFO_CONFIG1_HIRES_t
Definition: Icm426xxDefs.h:1077
ICM426XX_FIFO_CONFIG1_HIRES_DIS
@ ICM426XX_FIFO_CONFIG1_HIRES_DIS
Definition: Icm426xxDefs.h:1079
ICM426XX_FIFO_CONFIG1_HIRES_EN
@ ICM426XX_FIFO_CONFIG1_HIRES_EN
Definition: Icm426xxDefs.h:1078
ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_t
ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_t
Definition: Icm426xxDefs.h:542
ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_DIS
@ ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_DIS
Definition: Icm426xxDefs.h:544
ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_EN
@ ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_EN
Definition: Icm426xxDefs.h:543
BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS
#define BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS
Definition: Icm426xxDefs.h:1890
BIT_INTF_CONFIG4_AP_SPI_POS
#define BIT_INTF_CONFIG4_AP_SPI_POS
Definition: Icm426xxDefs.h:1339
BIT_APEX_DATA4_TAP_AXIS_POS
#define BIT_APEX_DATA4_TAP_AXIS_POS
Definition: Icm426xxDefs.h:483
BIT_APEX_CONFIG2_PEDO_AMP_TH_POS
#define BIT_APEX_CONFIG2_PEDO_AMP_TH_POS
Definition: Icm426xxDefs.h:1758
BIT_GYRO_NF_DIS_POS
#define BIT_GYRO_NF_DIS_POS
Definition: Icm426xxDefs.h:1296
ICM426XX_CHIP_CONFIG_SPI_MODE_t
ICM426XX_CHIP_CONFIG_SPI_MODE_t
Definition: Icm426xxDefs.h:342
ICM426XX_CHIP_CONFIG_SPI_MODE_1_2
@ ICM426XX_CHIP_CONFIG_SPI_MODE_1_2
Definition: Icm426xxDefs.h:343
ICM426XX_CHIP_CONFIG_SPI_MODE_0_3
@ ICM426XX_CHIP_CONFIG_SPI_MODE_0_3
Definition: Icm426xxDefs.h:344
BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS
#define BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS
Definition: Icm426xxDefs.h:1587
ICM426XX_APEX_CONFIG0_TILT_EN_t
ICM426XX_APEX_CONFIG0_TILT_EN_t
Definition: Icm426xxDefs.h:1003
ICM426XX_APEX_CONFIG0_TILT_EN_EN
@ ICM426XX_APEX_CONFIG0_TILT_EN_EN
Definition: Icm426xxDefs.h:1004
ICM426XX_APEX_CONFIG0_TILT_EN_DIS
@ ICM426XX_APEX_CONFIG0_TILT_EN_DIS
Definition: Icm426xxDefs.h:1005
ICM426XX_GYRO_NF_DIS_t
ICM426XX_GYRO_NF_DIS_t
Definition: Icm426xxDefs.h:1298
ICM426XX_GYRO_NF_DIS
@ ICM426XX_GYRO_NF_DIS
Definition: Icm426xxDefs.h:1300
ICM426XX_GYRO_NF_EN
@ ICM426XX_GYRO_NF_EN
Definition: Icm426xxDefs.h:1299
fifo_header_t
Describe the content of the FIFO header.
Definition: Icm426xxDefs.h:287
fifo_header_t::accel_odr_different
unsigned char accel_odr_different
Definition: Icm426xxDefs.h:291
fifo_header_t::msg_bit
unsigned char msg_bit
Definition: Icm426xxDefs.h:297
fifo_header_t::fsync_bit
unsigned char fsync_bit
Definition: Icm426xxDefs.h:292
fifo_header_t::Byte
unsigned char Byte
Definition: Icm426xxDefs.h:288
fifo_header_t::gyro_odr_different
unsigned char gyro_odr_different
Definition: Icm426xxDefs.h:290
fifo_header_t::accel_bit
unsigned char accel_bit
Definition: Icm426xxDefs.h:296
fifo_header_t::gyro_bit
unsigned char gyro_bit
Definition: Icm426xxDefs.h:295
fifo_header_t::twentybits_bit
unsigned char twentybits_bit
Definition: Icm426xxDefs.h:294
fifo_header_t::timestamp_bit
unsigned char timestamp_bit
Definition: Icm426xxDefs.h:293