| ICM40609D eMD Driver 2.0.0 Documentation of the eMD Driver API

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Icm406xx driver unit functions

Unit functions to access Icm406xx device registers. More...

## Functions
int | inv_icm406xx_wr_device_config_spi_mode (struct inv_icm406xx *s, ICM406XX_DEVICE_CONFIG_SPI_MODE_t new_value)
| Set DEVICE_CONFIG register SPI_MODE bits. More...
int | inv_icm406xx_wr_device_config_reset (struct inv_icm406xx *s, ICM406XX_DEVICE_CONFIG_RESET_t new_value)
| Set DEVICE_CONFIG register SOFT_RESET_CONFIG bit. More...
int | inv_icm406xx_wr_int_cfg_int1_drive_circuit (struct inv_icm406xx *s, ICM406XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t new_value)
| Set INT_CONFIG register INT1_DRIVE_CIRCUIT bit. More...
int | inv_icm406xx_wr_int_cfg_int1_polarity (struct inv_icm406xx *s, ICM406XX_INT_CONFIG_INT1_POLARITY_t new_value)
| Set INT_CONFIG register INT1_POLARITY bit. More...
int | inv_icm406xx_wr_fifo_config_mode (struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG_MODE_t new_value)
| Set FIFO_CONFIG register FIFO_MODE bit. More...
int | inv_icm406xx_rd_fifo_config_mode (struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG_MODE_t *value)
| Read FIFO_CONFIG register FIFO_MODE bit. More...
int | inv_icm406xx_rd_int_status (struct inv_icm406xx *s, uint8_t *value)
| Get INT_STATUS register value. More...
int | inv_icm406xx_rd_fifo_count (struct inv_icm406xx *s, uint8_t value[2])
| Get FIFO count from FIFO_COUNTL and FIFO_COUNTH registers. More...
int | inv_icm406xx_rd_fifo (struct inv_icm406xx *s, int len, uint8_t *value)
| Read FIFO_DATA_REG. More...
int | inv_icm406xx_wr_signal_path_rst_tmst_strobe (struct inv_icm406xx *s, ICM406XX_SIGNAL_PATH_RESET_TMST_STROBE_t new_value)
| Set SIGNAL_PATH_RESET register TMST_STROBE bit. More...
int | inv_icm406xx_wr_signal_path_rst_fifo_flush (struct inv_icm406xx *s, ICM406XX_SIGNAL_PATH_RESET_FIFO_FLUSH_t new_value)
| Set SIGNAL_PATH_RESET register FIFO_FLUSH bit. More...
int | inv_icm406xx_wr_intf_config0_fifo_sreg_invalid_ind (struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t new_value)
| Set INTF_CONFIG0 register FIFO_SREG_INVALID_IND bit. More...
int | inv_icm406xx_wr_intf_config0_fifo_count_rec (struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_FIFO_COUNT_REC_t new_value)
| Set INTF_CONFIG0 register FIFO_COUNT_REC bit. More...
int | inv_icm406xx_wr_intf_config0_fifo_count_endian (struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t new_value)
| Set INTF_CONFIG0 register FIFO_COUNT_ENDIAN bit. More...
int | inv_icm406xx_wr_intf_config0_data_endian (struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_DATA_COUNT_ENDIAN_t new_value)
| Set INTF_CONFIG0 register DATA_ENDIAN bit. More...
int | inv_icm406xx_rd_intf_config0_data_endian (struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_DATA_COUNT_ENDIAN_t *value)
| Get INTF_CONFIG0 register DATA_ENDIAN bit. More...
int | inv_icm406xx_wr_intf_config0_spi_mode_ois2 (struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_SPI_MODE_OIS2_t new_value)
| Set INTF_CONFIG0 register SPI_MODE_AUX2 bit. More...
int | inv_icm406xx_wr_intf_config0_spi_mode_ois1 (struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_SPI_MODE_OIS1_t new_value)
| Set INTF_CONFIG0 register SPI_MODE_OIS1 bit. More...
int | inv_icm406xx_wr_intf_config1_accel_lp_clk_sel (struct inv_icm406xx *s, ICM406XX_INTF_CONFIG1_ACCEL_LP_CLK_SEL_t new_value)
| Set INTF_CONFIG1 register ACCEL_LP_CLK_SEL bit. More...
int | inv_icm406xx_wr_pwr_mgmt0_temp_en (struct inv_icm406xx *s, ICM406XX_PWR_MGMT_0_TEMP_t new_value)
| Set PWR_MGMT_0 register TEMP_DIS bit. More...
int | inv_icm406xx_rd_pwr_mgmt0_temp_en (struct inv_icm406xx *s, ICM406XX_PWR_MGMT_0_TEMP_t *value)
| Read PWR_MGMT_0 register TEMP_DIS bit. More...
int | inv_icm406xx_wr_pwr_mgmt0_gyro_mode (struct inv_icm406xx *s, ICM406XX_PWR_MGMT_0_GYRO_MODE_t new_value)
| Set PWR_MGMT_0 register GYRO_MODE bit. More...
int | inv_icm406xx_rd_pwr_mgmt0_gyro_mode (struct inv_icm406xx *s, ICM406XX_PWR_MGMT_0_GYRO_MODE_t *value)
| Read PWR_MGMT_0 register GYRO_MODE bit. More...
int | inv_icm406xx_wr_pwr_mgmt0_accel_mode (struct inv_icm406xx *s, ICM406XX_PWR_MGMT_0_ACCEL_MODE_t new_value)
| Set PWR_MGMT_0 register ACCEL_MODE bit. More...
int | inv_icm406xx_rd_pwr_mgmt0_accel_mode (struct inv_icm406xx *s, ICM406XX_PWR_MGMT_0_ACCEL_MODE_t *value)
| Read PWR_MGMT_0 register ACCEL_MODE bit. More...
int | inv_icm406xx_wr_gyro_config0_fs_sel (struct inv_icm406xx *s, ICM406XX_GYRO_CONFIG0_FS_SEL_t new_value)
| Set GYRO_CONFIG0 register GYRO_FS_SEL bits. More...
int | inv_icm406xx_rd_gyro_config0_fs_sel (struct inv_icm406xx *s, ICM406XX_GYRO_CONFIG0_FS_SEL_t *value)
| Get GYRO_CONFIG0 register GYRO_FS_SEL bits. More...
int | inv_icm406xx_wr_gyro_config0_odr (struct inv_icm406xx *s, ICM406XX_GYRO_CONFIG0_ODR_t new_value)
| Set GYRO_CONFIG0 register GYRO_ODR bits. More...
int | inv_icm406xx_rd_gyro_config0_odr (struct inv_icm406xx *s, ICM406XX_GYRO_CONFIG0_ODR_t *value)
| Get GYRO_CONFIG0 register GYRO_ODR bits. More...
int | inv_icm406xx_wr_accel_config0_fs_sel (struct inv_icm406xx *s, ICM406XX_ACCEL_CONFIG0_FS_SEL_t new_value)
| Set ACCEL_CONFIG0 register ACCEL_FS_SEL bits. More...
int | inv_icm406xx_rd_accel_config0_fs_sel (struct inv_icm406xx *s, ICM406XX_ACCEL_CONFIG0_FS_SEL_t *value)
| Get ACCEL_CONFIG0 register ACCEL_FS_SEL bits. More...
int | inv_icm406xx_wr_accel_config0_odr (struct inv_icm406xx *s, ICM406XX_ACCEL_CONFIG0_ODR_t new_value)
| Set ACCEL_CONFIG0 register ACCEL_ODR bits. More...
int | inv_icm406xx_rd_accel_config0_odr (struct inv_icm406xx *s, ICM406XX_ACCEL_CONFIG0_ODR_t *value)
| Read ACCEL_CONFIG0 register ACCEL_ODR bits. More...
int | inv_icm406xx_wr_gyro_config1_avg_filt_rate (struct inv_icm406xx *s, ICM406XX_GYRO_CONFIG1_AVG_FILT_RATE_t new_value)
| Set GYRO_CONFIG1 register AVG_FILT_RATE bit. More...
int | inv_icm406xx_wr_gyro_accel_config0_accel_filt_bw (struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t new_value)
| Set GYRO_ACCEL_CONFIG0 register ACCEL_FILT bit. More...
int | inv_icm406xx_rd_gyro_accel_config0_accel_filt_bw (struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t *value)
| Get GYRO_ACCEL_CONFIG0 register ACCEL_FILT bit. More...
int | inv_icm406xx_wr_gyro_accel_config0_accel_filt_avg (struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t new_value)
| Set GYRO_ACCEL_CONFIG0 register ACCEL_FILT bit. More...
int | inv_icm406xx_rd_gyro_accel_config0_accel_filt_avg (struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t *value)
| Get GYRO_ACCEL_CONFIG0 register ACCEL_FILT bit. More...
int | inv_icm406xx_wr_gyro_accel_config0_gyro_filt_bw (struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t new_value)
| Set GYRO_ACCEL_CONFIG0 register GYRO_FILT_BW bit. More...
int | inv_icm406xx_rd_gyro_accel_config0_gyro_filt_bw (struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t *value)
| Get GYRO_ACCEL_CONFIG0 register GYRO_FILT_BW bit. More...
int | inv_icm406xx_wr_gyro_accel_config0_gyro_filt_avg (struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_t new_value)
| Set GYRO_ACCEL_CONFIG0 register GYRO_FILT_AVG bit. More...
int | inv_icm406xx_wr_accel_config1_avg_filt_rate (struct inv_icm406xx *s, ICM406XX_ACCEL_CONFIG1_AVG_FILT_RATE_t new_value)
| Set ACCEL_CONFIG1 register AVG_FILT_RATE bit. More...
int | inv_icm406xx_rd_accel_config1_avg_filt_rate (struct inv_icm406xx *s, ICM406XX_ACCEL_CONFIG1_AVG_FILT_RATE_t *value)
| Get ACCEL_CONFIG1 register AVG_FILT_RATE bit. More...
int | inv_icm406xx_wr_accel_wom_x_thr (struct inv_icm406xx *s, uint8_t new_value)
| Set ACCEL_WOM_X_THR register WOM_X_TH bits. More...
int | inv_icm406xx_wr_accel_wom_y_thr (struct inv_icm406xx *s, uint8_t new_value)
| Set ACCEL_WOM_Y_THR register WOM_Y_TH bits. More...
int | inv_icm406xx_wr_accel_wom_z_thr (struct inv_icm406xx *s, uint8_t new_value)
| Set ACCEL_WOM_Z_THR register WOM_Z_TH bits. More...
int | inv_icm406xx_wr_smd_config_wom_int_mode (struct inv_icm406xx *s, ICM406XX_SMD_CONFIG_WOM_INT_MODE_t new_value)
| Set MPUREG_SMD_CONFIG register WOM_INT_MODE bit. More...
int | inv_icm406xx_rd_smd_config_wom_int_mode (struct inv_icm406xx *s, ICM406XX_SMD_CONFIG_WOM_INT_MODE_t *value)
| Get MPUREG_SMD_CONFIG register WOM_INT_MODE bit. More...
int | inv_icm406xx_wr_smd_config_wom_mode (struct inv_icm406xx *s, ICM406XX_SMD_CONFIG_WOM_MODE_t new_value)
| Set MPUREG_SMD_CONFIG register WOM_MODE bit. More...
int | inv_icm406xx_rd_smd_config_wom_mode (struct inv_icm406xx *s, ICM406XX_SMD_CONFIG_WOM_MODE_t *value)
| Get MPUREG_SMD_CONFIG register WOM_MODE bit. More...
int | inv_icm406xx_wr_smd_config_smd_mode (struct inv_icm406xx *s, ICM406XX_SMD_CONFIG_SMD_MODE_t new_value)
| Set MPUREG_SMD_CONFIG register SMD_MODE bit. More...
int | inv_icm406xx_rd_smd_config_smd_mode (struct inv_icm406xx *s, ICM406XX_SMD_CONFIG_SMD_MODE_t *value)
| Get MPUREG_SMD_CONFIG register SMD_MODE bit. More...
int | inv_icm406xx_rd_int_status2 (struct inv_icm406xx *s, uint8_t *value)
| Get INT_STATUS2 register value. More...
int | inv_icm406xx_wr_tmst_config_tmst_to_reg (struct inv_icm406xx *s, ICM406XX_TMST_CONFIG_TMST_TO_REGS_EN_t new_value)
| Set TMST_CONFIG register TMST_TO_REGS_EN bit. More...
int | inv_icm406xx_wr_tmst_config_resolution (struct inv_icm406xx *s, ICM406XX_TMST_CONFIG_RESOL_t new_value)
| Set TMST_CONFIG register TMST_RES bit. More...
int | inv_icm406xx_wr_tmst_config_fsync_en (struct inv_icm406xx *s, ICM406XX_TMST_CONFIG_TMST_FSYNC_EN_t new_value)
| Set TMST_CONFIG register TMST_FSYNC bit. More...
int | inv_icm406xx_rd_tmst_config_fsync_en (struct inv_icm406xx *s, ICM406XX_TMST_CONFIG_TMST_FSYNC_EN_t *value)
| Read TMST_CONFIG register TMST_FSYNC bit. More...
int | inv_icm406xx_wr_tmst_config_en (struct inv_icm406xx *s, ICM406XX_TMST_CONFIG_TMST_EN_t new_value)
| Set TMST_CONFIG register ICM406XX_TMST_CONFIG_EN bit. More...
int | inv_icm406xx_wr_fifo_config1_wm_gt_th (struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG1_WM_GT_t new_value)
| Set FIFO_CONFIG1 register FIFO_WM_GT_TH bit. More...
int | inv_icm406xx_wr_fifo_config1_hires (struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG1_HIRES_t new_value)
| Set FIFO_CONFIG1 register FIFO_HIRES_EN bit. More...
int | inv_icm406xx_wr_fifo_config1_tmst_fsync (struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG1_TMST_FSYNC_t new_value)
| Set FIFO_CONFIG1 register FIFO_TMST_FSYNC_EN bit. More...
int | inv_icm406xx_wr_fifo_config1_temp_en (struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG1_TEMP_t new_value)
| Set FIFO_CONFIG1 register FIFO_TEMP_EN bit. More...
int | inv_icm406xx_wr_fifo_config1_gyro_en (struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG1_GYRO_t new_value)
| Set FIFO_CONFIG1 register FIFO_GYRO_EN bit. More...
int | inv_icm406xx_wr_fifo_config1_accel_en (struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG1_ACCEL_t new_value)
| Set FIFO_CONFIG1 register FIFO_ACCEL_EN bit. More...
int | inv_icm406xx_wr_fifo_config2 (struct inv_icm406xx *s, uint8_t new_value)
| Set FIFO_CONFIG2 register value. More...
int | inv_icm406xx_fsync_config_ui_sel (struct inv_icm406xx *s, ICM406XX_FSYNC_CONFIG_UI_SEL_t new_value)
| Set FSYNC_CONFIG register FSYNC_UI_SEL bit. More...
int | inv_icm406xx_wr_int_config1_asy_rst_dis (struct inv_icm406xx *s, ICM406XX_INT_CONFIG1_ASY_RST_t new_value)
| Set INT_CONFIG1 register ASY_RESET_DISABLE bit. More...
int | inv_icm406xx_wr_int_source0 (struct inv_icm406xx *s, uint8_t new_value)
| Set INT_SOURCE0 register value. More...
int | inv_icm406xx_rd_int_source0 (struct inv_icm406xx *s, uint8_t *value)
| Get INT_SOURCE0 register value. More...
int | inv_icm406xx_wr_int_source1 (struct inv_icm406xx *s, uint8_t new_value)
| Set INT_SOURCE1 register value. More...
int | inv_icm406xx_rd_int_source1 (struct inv_icm406xx *s, uint8_t *value)
| Get INT_SOURCE1 register value. More...
int | inv_icm406xx_rd_who_am_i (struct inv_icm406xx *s, uint8_t *value)
| Get WHO_AM_I register value. More...
int | inv_icm406xx_wr_reg_bank_sel (struct inv_icm406xx *s, uint8_t new_value)
| Set REG_BANK_SEL register value. More...
int | inv_icm406xx_rd_tmst_val (struct inv_icm406xx *s, uint8_t value[3])
| Get TMST_VAL from TMST_VAL0_B1, TMST_VAL1_B1 and TMST_VAL2_B1 registers. More...
int | inv_icm406xx_wr_intf_config4_aux_spi (struct inv_icm406xx *s, ICM406XX_INTF_CONFIG4_AUX_SPI_t new_value)
| Set INTF_CONFIG4_B1 register SPI_AUX1_4WIRE bit. More...
int | inv_icm406xx_rd_intf_config4_aux_spi (struct inv_icm406xx *s, ICM406XX_INTF_CONFIG4_AUX_SPI_t *value)
| Get INTF_CONFIG4_B1 register SPI_AUX1_4WIRE bit. More...
int | inv_icm406xx_wr_intf_config4_ap_spi (struct inv_icm406xx *s, ICM406XX_INTF_CONFIG4_AP_SPI_t new_value)
| Set INTF_CONFIG4_B1 register SPI_AP_4WIRE bit. More...
int | inv_icm406xx_rd_intf_config4_ap_spi (struct inv_icm406xx *s, ICM406XX_INTF_CONFIG4_AP_SPI_t *value)
| Get INTF_CONFIG4_B1 register SPI_AP_4WIRE bit. More...
int | inv_icm406xx_wr_ois1_config1_dec (struct inv_icm406xx *s, ICM406XX_OIS1_CONFIG1_DEC_t new_value)
| Set AUX1_CONFIG1 register AUX1_DEC bit. More...
int | inv_icm406xx_wr_ois1_config1_gyro_en (struct inv_icm406xx *s, ICM406XX_OIS1_CONFIG1_GYRO_EN_t new_value)
| Set AUX1_CONFIG1 register GYRO_AUX1_EN bit. More...
int | inv_icm406xx_wr_ois1_config2_gyro_fs_sel (struct inv_icm406xx *s, ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_t new_value)
| Set AUX1_CONFIG2 register GYRO_AUX1_FS_SEL bit. More...
int | inv_icm406xx_rd_ois1_config2_gyro_fs_sel (struct inv_icm406xx *s, ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_t *value)
| Get AUX1_CONFIG2 register GYRO_AUX1_FS_SEL bit. More...
int | inv_icm406xx_rd_gyro_data_ois1 (struct inv_icm406xx *s, uint8_t value[GYRO_DATA_SIZE])
| Get MPUREG_GYRO_DATA_X0_AUX1_B2. More...
int | inv_icm406xx_rd_int_status_aux1 (struct inv_icm406xx *s, uint8_t *value)
| Get INT_STATUS_AUX1 register value. More...
int | inv_icm406xx_wr_ois2_config1_dec (struct inv_icm406xx *s, ICM406XX_OIS2_CONFIG1_DEC_t new_value)
| Set AUX2_CONFIG1 register AUX2_DEC bit. More...
int | inv_icm406xx_wr_ois2_config1_gyro_en (struct inv_icm406xx *s, ICM406XX_OIS2_CONFIG1_GYRO_EN_t new_value)
| Set AUX2_CONFIG1 register GYRO_AUX2_EN bit. More...
int | inv_icm406xx_wr_ois2_config2_gyro_fs_sel (struct inv_icm406xx *s, ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_t new_value)
| Set AUX2_CONFIG2 register GYRO_AUX2_FS_SEL bit. More...
int | inv_icm406xx_rd_ois2_config2_gyro_fs_sel (struct inv_icm406xx *s, ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_t *value)
| Get AUX2_CONFIG2 register GYRO_AUX2_FS_SEL bit. More...
int | inv_icm406xx_rd_gyro_data_ois2 (struct inv_icm406xx *s, uint8_t value[GYRO_DATA_SIZE])
| Get MPUREG_GYRO_DATA_X0_AUX2_B2. More...

## Detailed Description

Unit functions to access Icm406xx device registers.

## Function Documentation

## ◆ inv_icm406xx_fsync_config_ui_sel()

int inv_icm406xx_fsync_config_ui_sel | ( | struct inv_icm406xx * | s,
|  | ICM406XX_FSYNC_CONFIG_UI_SEL_t | new_value
| ) |  |

Set FSYNC_CONFIG register FSYNC_UI_SEL bit.

     0 Do not tag Fsync flag
     1 Tag Fsync flag to TEMP_OUT’s LSB
     2 Tag Fsync flag to GYRO_XOUT’s LSB
     3 Tag Fsync flag to GYRO_YOUT’s LSB
     4 Tag Fsync flag to GYRO_ZOUT’s LSB
     5 Tag Fsync flag to ACCEL_XOUT’s LSB
     6 Tag Fsync flag to ACCEL_YOUT’s LSB
     7 Tag Fsync flag to ACCEL_ZOUT’s LSB

Parameters

  [in] | new_value | See enum ICM406XX_FSYNC_CONFIG_UI_SEL_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_accel_config0_fs_sel()

int inv_icm406xx_rd_accel_config0_fs_sel | ( | struct inv_icm406xx * | s,
|  | ICM406XX_ACCEL_CONFIG0_FS_SEL_t * | value
| ) |  |

Get ACCEL_CONFIG0 register ACCEL_FS_SEL bits.

Accel Full Scale Select:
000 = ±16g
001 = ±8g
010 = ±4g
011 = ±2g
100 = ±1g

Parameters

  [out] | value | See enum ICM406XX_ACCEL_CONFIG0_FS_SEL_t.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_accel_config0_odr()

int inv_icm406xx_rd_accel_config0_odr | ( | struct inv_icm406xx * | s,
|  | ICM406XX_ACCEL_CONFIG0_ODR_t * | value
| ) |  |

Read ACCEL_CONFIG0 register ACCEL_ODR bits.

Accel odr Select:
0 - 64K
1 - 32K
2 - 16K
3 - 8k
4 - 4k
5 - 2k
6 - 1k : 1ms
7 - 200 (default) : 5 ms
8 - 100 : 10 ms
9 - 50 : 20 ms
10 - 25 : 40 ms
11 - 12.5 : 80 ms
12 - 6.25 : 160 ms

Parameters

  [out] | value | See enum ICM406XX_ACCEL_CONFIG0_ODR_t.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_accel_config1_avg_filt_rate()

int inv_icm406xx_rd_accel_config1_avg_filt_rate | ( | struct inv_icm406xx * | s,
|  | ICM406XX_ACCEL_CONFIG1_AVG_FILT_RATE_t * | value
| ) |  |

Get ACCEL_CONFIG1 register AVG_FILT_RATE bit.

     1 in LPM Average filter runs 8KHz
     0 in LPM Average filter runs 1KHz

Parameters

  [out] | new_value | See enum ICM406XX_ACCEL_CONFIG1_AVG_FILT_RATE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_fifo()

int inv_icm406xx_rd_fifo | ( | struct inv_icm406xx * | s,
|  | int | len,
|  | uint8_t * | value
| ) |  |

Read FIFO_DATA_REG.

Parameters

  [in] | len | Length of data to read, in bytes.
  [out] | value | FIFO data.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_fifo_config_mode()

int inv_icm406xx_rd_fifo_config_mode | ( | struct inv_icm406xx * | s,
|  | ICM406XX_FIFO_CONFIG_MODE_t * | value
| ) |  |

Read FIFO_CONFIG register FIFO_MODE bit.

Parameters

  [out] | value | See enum ICM406XX_FIFO_CONFIG_MODE_t ‘2’, when the FIFO is full, additional writes will not be written to FIFO. ‘1’, when the FIFO is full, additional writes will be written to the FIFO, replacing the oldest data. ‘0’, Disable the fifo.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_fifo_count()

int inv_icm406xx_rd_fifo_count | ( | struct inv_icm406xx * | s,
|  | uint8_t | value[2]
| ) |  |

Get FIFO count from FIFO_COUNTL and FIFO_COUNTH registers.

Parameters

  [out] | value | 16-bit FIFO count.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_gyro_accel_config0_accel_filt_avg()

int inv_icm406xx_rd_gyro_accel_config0_accel_filt_avg | ( | struct inv_icm406xx * | s,
|  | ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t * | value
| ) |  |

Get GYRO_ACCEL_CONFIG0 register ACCEL_FILT bit.

     1 AVG=1 AVG filt at 1kHz/8kHz
     2 AVG=2 AVG filt at 1kHz/8kHz
     3 AVG=3 AVG filt at 1kHz/8kHz
     4 AVG=4 AVG filt at 1kHz/8kHz
     5 AVG=8 AVG filt at 1kHz/8kHz
     6 AVG=16 AVG filt at 1kHz/8kHz
     7 AVG=32 AVG filt at 1kHz/8kHz
     8 AVG=64 AVG filt at 1kHz/8kHz
     9 AVG=128 AVG filt at 1kHz/8kHz

Parameters

  [out] | new_value | See enum ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_gyro_accel_config0_accel_filt_bw()

int inv_icm406xx_rd_gyro_accel_config0_accel_filt_bw | ( | struct inv_icm406xx * | s,
|  | ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t * | value
| ) |  |

Get GYRO_ACCEL_CONFIG0 register ACCEL_FILT bit.

     0 BW=ODR/2 FIR at 8*ODR
     1 BW=ODR/4 IIR at max(400Hz, ODR)
     2 BW=ODR/5 IIR at max(400Hz, ODR)
     3 BW=ODR/8 IIR at max(400Hz, ODR)
     4 BW=ODR/10 IIR at max(400Hz, ODR)
     5 BW=ODR/16 IIR at max(400Hz, ODR)
     6 BW=ODR/20 IIR at max(400Hz, ODR)
     7 BW=ODR/40 IIR at max(400Hz, ODR)

Parameters

  [out] | new_value | See enum ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_gyro_accel_config0_gyro_filt_bw()

int inv_icm406xx_rd_gyro_accel_config0_gyro_filt_bw | ( | struct inv_icm406xx * | s,
|  | ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t * | value
| ) |  |

Get GYRO_ACCEL_CONFIG0 register GYRO_FILT_BW bit.

     0 BW=ODR/2 FIR at 8*ODR
     1 BW=ODR/4 IIR at max(400Hz, ODR)
     2 BW=ODR/5 IIR at max(400Hz, ODR)
     3 BW=ODR/8 IIR at max(400Hz, ODR)
     4 BW=ODR/10 IIR at max(400Hz, ODR)
     5 BW=ODR/16 IIR at max(400Hz, ODR)
     6 BW=ODR/20 IIR at max(400Hz, ODR)
     7 BW=ODR/40 IIR at max(400Hz, ODR)

Parameters

  [out] | new_value | See enum ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_gyro_config0_fs_sel()

int inv_icm406xx_rd_gyro_config0_fs_sel | ( | struct inv_icm406xx * | s,
|  | ICM406XX_GYRO_CONFIG0_FS_SEL_t * | value
| ) |  |

Get GYRO_CONFIG0 register GYRO_FS_SEL bits.

Gyro Full Scale Select:
000 = ±2000dps
001 = ±1000dps
010 = ±500dps
011 = ±250dps
100 = ±125dps
101 = ±62dps
110 = ±31dps
111 = ±16dps

Parameters

  [out] | value | See enum ICM406XX_GYRO_CONFIG0_FS_SEL_t.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_gyro_config0_odr()

int inv_icm406xx_rd_gyro_config0_odr | ( | struct inv_icm406xx * | s,
|  | ICM406XX_GYRO_CONFIG0_ODR_t * | value
| ) |  |

Get GYRO_CONFIG0 register GYRO_ODR bits.

Gyro odr Select:
0 - 64K
1 - 32K
2 - 16K
3 - 8k
4 - 4k
5 - 2k
6 - 1k : 1ms
7 - 200 (default) : 5 ms
8 - 100 : 10 ms
9 - 50 : 20 ms
10 - 25 : 40 ms
11 - 12.5 : 80 ms
12 - 6.25 : 160 ms

Parameters

  [in] | new_value | See enum ICM406XX_GYRO_CONFIG0_ODR_t.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_gyro_data_ois1()

int inv_icm406xx_rd_gyro_data_ois1 | ( | struct inv_icm406xx * | s,
|  | uint8_t | value[GYRO_DATA_SIZE]
| ) |  |

Get MPUREG_GYRO_DATA_X0_AUX1_B2.

Parameters

  [out] | value | 3*2 OIS bytes.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_gyro_data_ois2()

int inv_icm406xx_rd_gyro_data_ois2 | ( | struct inv_icm406xx * | s,
|  | uint8_t | value[GYRO_DATA_SIZE]
| ) |  |

Get MPUREG_GYRO_DATA_X0_AUX2_B2.

Parameters

  [out] | value | 3*2 OIS bytes.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_int_source0()

int inv_icm406xx_rd_int_source0 | ( | struct inv_icm406xx * | s,
|  | uint8_t * | value
| ) |  |

Get INT_SOURCE0 register value.

Parameters

  [out] | Interrupt | source

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_int_source1()

int inv_icm406xx_rd_int_source1 | ( | struct inv_icm406xx * | s,
|  | uint8_t * | value
| ) |  |

Get INT_SOURCE1 register value.

Parameters

  [out] | Interrupt | source

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_int_status()

int inv_icm406xx_rd_int_status | ( | struct inv_icm406xx * | s,
|  | uint8_t * | value
| ) |  |

Get INT_STATUS register value.

Parameters

  [out] | * | value Interrupt Status

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_int_status2()

int inv_icm406xx_rd_int_status2 | ( | struct inv_icm406xx * | s,
|  | uint8_t * | value
| ) |  |

Get INT_STATUS2 register value.

Parameters

  [out] | * | value INT_STATUS2 register value

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_int_status_aux1()

int inv_icm406xx_rd_int_status_aux1 | ( | struct inv_icm406xx * | s,
|  | uint8_t * | value
| ) |  |

Get INT_STATUS_AUX1 register value.

Parameters

  [out] | * | value INT_STATUS_AUX1 register value

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_intf_config0_data_endian()

int inv_icm406xx_rd_intf_config0_data_endian | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INTF_CONFIG0_DATA_COUNT_ENDIAN_t * | value
| ) |  |

Get INTF_CONFIG0 register DATA_ENDIAN bit.

Selects whether DATA_ENDIAN[1:0] indicates the endianess.
When set to ‘1’ report data in big endian.
When set to ‘0’ report data in little endian.

Parameters

  [in] | new_value | See enum ICM406XX_INTF_CONFIG0_DATA_COUNT_ENDIAN_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_intf_config4_ap_spi()

int inv_icm406xx_rd_intf_config4_ap_spi | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INTF_CONFIG4_AP_SPI_t * | value
| ) |  |

Get INTF_CONFIG4_B1 register SPI_AP_4WIRE bit.

When set to ‘1’, SPI AP is in 4 wire interface When set to ‘0’, SPI AP is in 3 wire interface

Parameters

  [in] | * | value See enum ICM406XX_INTF_CONFIG4_AP_SPI_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_intf_config4_aux_spi()

int inv_icm406xx_rd_intf_config4_aux_spi | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INTF_CONFIG4_AUX_SPI_t * | value
| ) |  |

Get INTF_CONFIG4_B1 register SPI_AUX1_4WIRE bit.

When set to ‘1’, SPI AUX is in 4 wire interface When set to ‘0’, SPI AUX is in 3 wire interface

Parameters

  [out] | * | value See enum ICM406XX_INTF_CONFIG4_AUX_SPI_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_ois1_config2_gyro_fs_sel()

int inv_icm406xx_rd_ois1_config2_gyro_fs_sel | ( | struct inv_icm406xx * | s,
|  | ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_t * | value
| ) |  |

Get AUX1_CONFIG2 register GYRO_AUX1_FS_SEL bit.

Gyro OIS Full Scale Select:
000 = ±2000dps
001 = ±1000dps
010 = ±500dps
011 = ±250dps
100 = ±125dps
101 = ±62dps
110 = ±31dps
111 = ±16dps

Parameters

  [in] | new_value | See enum ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_ois2_config2_gyro_fs_sel()

int inv_icm406xx_rd_ois2_config2_gyro_fs_sel | ( | struct inv_icm406xx * | s,
|  | ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_t * | value
| ) |  |

Get AUX2_CONFIG2 register GYRO_AUX2_FS_SEL bit.

Gyro OIS Full Scale Select:
000 = ±2000dps
001 = ±1000dps
010 = ±500dps
011 = ±250dps
100 = ±125dps
101 = ±62dps
110 = ±31dps
111 = ±16dps

Parameters

  [in] | new_value | See enum ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_pwr_mgmt0_accel_mode()

int inv_icm406xx_rd_pwr_mgmt0_accel_mode | ( | struct inv_icm406xx * | s,
|  | ICM406XX_PWR_MGMT_0_ACCEL_MODE_t * | value
| ) |  |

Read PWR_MGMT_0 register ACCEL_MODE bit.

     3 – accel low noise mode
     2 – accel low power mode
     0 – accel off

Parameters

  [out] | value | See enum ICM406XX_PWR_MGMT_0_ACCEL_MODE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_pwr_mgmt0_gyro_mode()

int inv_icm406xx_rd_pwr_mgmt0_gyro_mode | ( | struct inv_icm406xx * | s,
|  | ICM406XX_PWR_MGMT_0_GYRO_MODE_t * | value
| ) |  |

Read PWR_MGMT_0 register GYRO_MODE bit.

     3 – gyro low noise mode
     0 – gyro off

note : others modes are not supported for gyro on 406xx

Parameters

  [out] | value | See enum ICM406XX_PWR_MGMT_0_GYRO_MODE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_pwr_mgmt0_temp_en()

int inv_icm406xx_rd_pwr_mgmt0_temp_en | ( | struct inv_icm406xx * | s,
|  | ICM406XX_PWR_MGMT_0_TEMP_t * | value
| ) |  |

Read PWR_MGMT_0 register TEMP_DIS bit.

     1 – disable temperature sensor
     0 – enable temperature sensor

Parameters

  [out] | value | See enum ICM406XX_PWR_MGMT_0_TEMP_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_smd_config_smd_mode()

int inv_icm406xx_rd_smd_config_smd_mode | ( | struct inv_icm406xx * | s,
|  | ICM406XX_SMD_CONFIG_SMD_MODE_t * | value
| ) |  |

Get MPUREG_SMD_CONFIG register SMD_MODE bit.

     3 - SMD long (3 sec wait)
     2 - SMD short (1 sec wait)
     1 – WOM using old definition
     0 – Disabled

Parameters

  [in] | new_value | See enum ICM406XX_SMD_CONFIG_SMD_MODE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_smd_config_wom_int_mode()

int inv_icm406xx_rd_smd_config_wom_int_mode | ( | struct inv_icm406xx * | s,
|  | ICM406XX_SMD_CONFIG_WOM_INT_MODE_t * | value
| ) |  |

Get MPUREG_SMD_CONFIG register WOM_INT_MODE bit.

     1 – The WoM from 3 axis are ANDed to produce WoM signal
     0 – The WoM from 3 axis are ORed to produce WoM signal

Parameters

  [in] | new_value | See enum ICM406XX_SMD_CONFIG_WOM_INT_MODE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_smd_config_wom_mode()

int inv_icm406xx_rd_smd_config_wom_mode | ( | struct inv_icm406xx * | s,
|  | ICM406XX_SMD_CONFIG_WOM_MODE_t * | value
| ) |  |

Get MPUREG_SMD_CONFIG register WOM_MODE bit.

     1 – Compare current sample to previous sample
     0 – Initial sample is stored. Future samples are compared to initial

Parameters

  [in] | new_value | See enum ICM406XX_SMD_CONFIG_WOM_MODE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_tmst_config_fsync_en()

int inv_icm406xx_rd_tmst_config_fsync_en | ( | struct inv_icm406xx * | s,
|  | ICM406XX_TMST_CONFIG_TMST_FSYNC_EN_t * | value
| ) |  |

Read TMST_CONFIG register TMST_FSYNC bit.

Parameters

  [out] | value | pointer on read value (See enum ICM406XX_TMST_CONFIG_TMST_FSYNC_EN_t) ‘1’, Timestamp fsync enable. ‘0’, Timestamp fsync disable

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_tmst_val()

int inv_icm406xx_rd_tmst_val | ( | struct inv_icm406xx * | s,
|  | uint8_t | value[3]
| ) |  |

Get TMST_VAL from TMST_VAL0_B1, TMST_VAL1_B1 and TMST_VAL2_B1 registers.

Parameters

  [out] | value | 20-bit timestamp register.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_rd_who_am_i()

int inv_icm406xx_rd_who_am_i | ( | struct inv_icm406xx * | s,
|  | uint8_t * | value
| ) |  |

Get WHO_AM_I register value.

Register to indicate to user which device is being accessed.

Parameters

  [out] | value | The whoami of the device.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_accel_config0_fs_sel()

int inv_icm406xx_wr_accel_config0_fs_sel | ( | struct inv_icm406xx * | s,
|  | ICM406XX_ACCEL_CONFIG0_FS_SEL_t | new_value
| ) |  |

Set ACCEL_CONFIG0 register ACCEL_FS_SEL bits.

Accel Full Scale Select:
000 = ±16g
001 = ±8g
010 = ±4g
011 = ±2g
100 = ±1g

Parameters

  [in] | new_value | See enum ICM406XX_ACCEL_CONFIG0_FS_SEL_t.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_accel_config0_odr()

int inv_icm406xx_wr_accel_config0_odr | ( | struct inv_icm406xx * | s,
|  | ICM406XX_ACCEL_CONFIG0_ODR_t | new_value
| ) |  |

Set ACCEL_CONFIG0 register ACCEL_ODR bits.

Accel odr Select:
0 - 64K
1 - 32K
2 - 16K
3 - 8k
4 - 4k
5 - 2k
6 - 1k : 1ms
7 - 200 (default) : 5 ms
8 - 100 : 10 ms
9 - 50 : 20 ms
10 - 25 : 40 ms
11 - 12.5 : 80 ms
12 - 6.25 : 160 ms

Parameters

  [in] | new_value | See enum ICM406XX_ACCEL_CONFIG0_ODR_t.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_accel_config1_avg_filt_rate()

int inv_icm406xx_wr_accel_config1_avg_filt_rate | ( | struct inv_icm406xx * | s,
|  | ICM406XX_ACCEL_CONFIG1_AVG_FILT_RATE_t | new_value
| ) |  |

Set ACCEL_CONFIG1 register AVG_FILT_RATE bit.

     1 in LPM Average filter runs 8KHz
     0 in LPM Average filter runs 1KHz

Parameters

  [in] | new_value | See enum ICM406XX_ACCEL_CONFIG1_AVG_FILT_RATE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_accel_wom_x_thr()

int inv_icm406xx_wr_accel_wom_x_thr | ( | struct inv_icm406xx * | s,
|  | uint8_t | new_value
| ) |  |

Set ACCEL_WOM_X_THR register WOM_X_TH bits.

This register holds the threshold value for the Wake on Motion Interrupt for X-axis accelerometer.

Parameters

  [in] | new_value | accel wake on motion x-axis threshold

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_accel_wom_y_thr()

int inv_icm406xx_wr_accel_wom_y_thr | ( | struct inv_icm406xx * | s,
|  | uint8_t | new_value
| ) |  |

Set ACCEL_WOM_Y_THR register WOM_Y_TH bits.

This register holds the threshold value for the Wake on Motion Interrupt for Y-axis accelerometer.

Parameters

  [in] | new_value | accel wake on motion y-axis threshold

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_accel_wom_z_thr()

int inv_icm406xx_wr_accel_wom_z_thr | ( | struct inv_icm406xx * | s,
|  | uint8_t | new_value
| ) |  |

Set ACCEL_WOM_Z_THR register WOM_Z_TH bits.

This register holds the threshold value for the Wake on Motion Interrupt for Z-axis accelerometer.

Parameters

  [in] | new_value | accel wake on motion z-axis threshold

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_device_config_reset()

int inv_icm406xx_wr_device_config_reset | ( | struct inv_icm406xx * | s,
|  | ICM406XX_DEVICE_CONFIG_RESET_t | new_value
| ) |  |

Set DEVICE_CONFIG register SOFT_RESET_CONFIG bit.

When set to ‘1’ Enable reset.
When set to ‘0’ Normal.

Parameters

  [in] | new_value | See enum ICM406XX_DEVICE_CONFIG_RESET_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_device_config_spi_mode()

int inv_icm406xx_wr_device_config_spi_mode | ( | struct inv_icm406xx * | s,
|  | ICM406XX_DEVICE_CONFIG_SPI_MODE_t | new_value
| ) |  |

Set DEVICE_CONFIG register SPI_MODE bits.

Selects SPI_MODE[1:0]
When set to ‘1’ Mode1 and Mode2.
When set to ‘0’ Mode0 and Mode3.

Parameters

  [in] | new_value | See enum ICM406XX_DEVICE_CONFIG_SPI_MODE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_fifo_config1_accel_en()

int inv_icm406xx_wr_fifo_config1_accel_en | ( | struct inv_icm406xx * | s,
|  | ICM406XX_FIFO_CONFIG1_ACCEL_t | new_value
| ) |  |

Set FIFO_CONFIG1 register FIFO_ACCEL_EN bit.

    1 – write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L, ACCEL_ZOUT_H, ACCEL_ZOUT_L,
        to the FIFO at the sample rate;
    0 – function is disabled

Parameters

  [in] | new_value | See enum ICM406XX_FIFO_CONFIG1_ACCEL_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_fifo_config1_gyro_en()

int inv_icm406xx_wr_fifo_config1_gyro_en | ( | struct inv_icm406xx * | s,
|  | ICM406XX_FIFO_CONFIG1_GYRO_t | new_value
| ) |  |

Set FIFO_CONFIG1 register FIFO_GYRO_EN bit.

    1 – write GYRO_XOUT_H, GYRO_XOUT_L, GYRO_YOUT_H, GYRO_YOUT_L,
        GYRO_ZOUT_H, and GYRO_ZOUT_L to the FIFO at the sample rate; If enabled, buffering
        of data occurs even if data path is in standby.
    0 – function is disabled

Parameters

  [in] | new_value | See enum ICM406XX_FIFO_CONFIG1_GYRO_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_fifo_config1_hires()

int inv_icm406xx_wr_fifo_config1_hires | ( | struct inv_icm406xx * | s,
|  | ICM406XX_FIFO_CONFIG1_HIRES_t | new_value
| ) |  |

Set FIFO_CONFIG1 register FIFO_HIRES_EN bit.

When set to ‘1’ enable hires.
When set to ‘0’ disable .

Parameters

  [in] | new_value | See enum ICM406XX_FIFO_CONFIG1_HIRES_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_fifo_config1_temp_en()

int inv_icm406xx_wr_fifo_config1_temp_en | ( | struct inv_icm406xx * | s,
|  | ICM406XX_FIFO_CONFIG1_TEMP_t | new_value
| ) |  |

Set FIFO_CONFIG1 register FIFO_TEMP_EN bit.

    1 – write TEMP_OUT_H, TEMP_OUT_L, to the FIFO at the sample rate; If enabled, buffering
        of data occurs even if data path is in standby.
    0 – function is disabled

Note: Can not be enabled alone, request ACCEL or GYRO

Parameters

  [in] | new_value | See enum ICM406XX_FIFO_CONFIG1_TEMP_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_fifo_config1_tmst_fsync()

int inv_icm406xx_wr_fifo_config1_tmst_fsync | ( | struct inv_icm406xx * | s,
|  | ICM406XX_FIFO_CONFIG1_TMST_FSYNC_t | new_value
| ) |  |

Set FIFO_CONFIG1 register FIFO_TMST_FSYNC_EN bit.

When set to ‘1’ Allows the TMST in the FIFO to be replaced by the FSYNC timestamp.
When set to ‘0’ disable .

Parameters

  [in] | new_value | See enum ICM406XX_FIFO_CONFIG1_TMST_FSYNC_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_fifo_config1_wm_gt_th()

int inv_icm406xx_wr_fifo_config1_wm_gt_th | ( | struct inv_icm406xx * | s,
|  | ICM406XX_FIFO_CONFIG1_WM_GT_t | new_value
| ) |  |

Set FIFO_CONFIG1 register FIFO_WM_GT_TH bit.

When set to ‘1’ trigger FIFO-Watermark interrupt on every ODR(DMA Write) if FIFO_COUNT>=FIFO_WM_TH .
When set to ‘0’ disable .

Parameters

  [in] | new_value | See enum ICM406XX_FIFO_CONFIG1_WM_GT_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_fifo_config2()

int inv_icm406xx_wr_fifo_config2 | ( | struct inv_icm406xx * | s,
|  | uint8_t | new_value
| ) |  |

Set FIFO_CONFIG2 register value.

Parameters

  [in] | 8 | LSB of FIFO Watermark value

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_fifo_config_mode()

int inv_icm406xx_wr_fifo_config_mode | ( | struct inv_icm406xx * | s,
|  | ICM406XX_FIFO_CONFIG_MODE_t | new_value
| ) |  |

Set FIFO_CONFIG register FIFO_MODE bit.

When set to ‘2’, when the FIFO is full, additional writes will not be written to FIFO.
When set to ‘1’, when the FIFO is full, additional writes will be written to the FIFO, replacing the oldest data. When set to ‘0’, Disable the fifo.

Parameters

  [in] | new_value | See enum ICM406XX_FIFO_CONFIG_MODE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_gyro_accel_config0_accel_filt_avg()

int inv_icm406xx_wr_gyro_accel_config0_accel_filt_avg | ( | struct inv_icm406xx * | s,
|  | ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t | new_value
| ) |  |

Set GYRO_ACCEL_CONFIG0 register ACCEL_FILT bit.

     1 AVG=1 AVG filt at 1kHz/8kHz
     2 AVG=2 AVG filt at 1kHz/8kHz
     3 AVG=3 AVG filt at 1kHz/8kHz
     4 AVG=4 AVG filt at 1kHz/8kHz
     5 AVG=8 AVG filt at 1kHz/8kHz
     6 AVG=16 AVG filt at 1kHz/8kHz
     7 AVG=32 AVG filt at 1kHz/8kHz
     8 AVG=64 AVG filt at 1kHz/8kHz
     9 AVG=128 AVG filt at 1kHz/8kHz

Parameters

  [in] | new_value | See enum ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_gyro_accel_config0_accel_filt_bw()

int inv_icm406xx_wr_gyro_accel_config0_accel_filt_bw | ( | struct inv_icm406xx * | s,
|  | ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t | new_value
| ) |  |

Set GYRO_ACCEL_CONFIG0 register ACCEL_FILT bit.

     0 BW=ODR/2 FIR at 8*ODR
     1 BW=ODR/4 IIR at max(400Hz, ODR)
     2 BW=ODR/5 IIR at max(400Hz, ODR)
     3 BW=ODR/8 IIR at max(400Hz, ODR)
     4 BW=ODR/10 IIR at max(400Hz, ODR)
     5 BW=ODR/16 IIR at max(400Hz, ODR)
     6 BW=ODR/20 IIR at max(400Hz, ODR)
     7 BW=ODR/40 IIR at max(400Hz, ODR)

Parameters

  [in] | new_value | See enum ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_gyro_accel_config0_gyro_filt_avg()

int inv_icm406xx_wr_gyro_accel_config0_gyro_filt_avg | ( | struct inv_icm406xx * | s,
|  | ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_t | new_value
| ) |  |

Set GYRO_ACCEL_CONFIG0 register GYRO_FILT_AVG bit.

     1 AVG=1 AVG filt at 1kHz/8kHz
     2 AVG=2 AVG filt at 1kHz/8kHz
     3 AVG=3 AVG filt at 1kHz/8kHz
     4 AVG=4 AVG filt at 1kHz/8kHz
     5 AVG=8 AVG filt at 1kHz/8kHz
     6 AVG=16 AVG filt at 1kHz/8kHz
     7 AVG=32 AVG filt at 1kHz/8kHz
     8 AVG=64 AVG filt at 1kHz/8kHz
     9 AVG=128 AVG filt at 1kHz/8kHz

Parameters

  [in] | new_value | See enum ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_gyro_accel_config0_gyro_filt_bw()

int inv_icm406xx_wr_gyro_accel_config0_gyro_filt_bw | ( | struct inv_icm406xx * | s,
|  | ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t | new_value
| ) |  |

Set GYRO_ACCEL_CONFIG0 register GYRO_FILT_BW bit.

     0 BW=ODR/2 FIR at 8*ODR
     1 BW=ODR/4 IIR at max(400Hz, ODR)
     2 BW=ODR/5 IIR at max(400Hz, ODR)
     3 BW=ODR/8 IIR at max(400Hz, ODR)
     4 BW=ODR/10 IIR at max(400Hz, ODR)
     5 BW=ODR/16 IIR at max(400Hz, ODR)
     6 BW=ODR/20 IIR at max(400Hz, ODR)
     7 BW=ODR/40 IIR at max(400Hz, ODR)

Parameters

  [in] | new_value | See enum ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_gyro_config0_fs_sel()

int inv_icm406xx_wr_gyro_config0_fs_sel | ( | struct inv_icm406xx * | s,
|  | ICM406XX_GYRO_CONFIG0_FS_SEL_t | new_value
| ) |  |

Set GYRO_CONFIG0 register GYRO_FS_SEL bits.

Gyro Full Scale Select:
000 = ±2000dps
001 = ±1000dps
010 = ±500dps
011 = ±250dps
100 = ±125dps
101 = ±62dps
110 = ±31dps
111 = ±16dps

Parameters

  [in] | new_value | See enum ICM406XX_GYRO_CONFIG0_FS_SEL_t.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_gyro_config0_odr()

int inv_icm406xx_wr_gyro_config0_odr | ( | struct inv_icm406xx * | s,
|  | ICM406XX_GYRO_CONFIG0_ODR_t | new_value
| ) |  |

Set GYRO_CONFIG0 register GYRO_ODR bits.

Gyro odr Select:
0 - 64K
1 - 32K
2 - 16K
3 - 8k
4 - 4k
5 - 2k
6 - 1k : 1ms
7 - 200 (default) : 5 ms
8 - 100 : 10 ms
9 - 50 : 20 ms
10 - 25 : 40 ms
11 - 12.5 : 80 ms
12 - 6.25 : 160 ms

Parameters

  [in] | new_value | See enum ICM406XX_GYRO_CONFIG0_ODR_t.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_gyro_config1_avg_filt_rate()

int inv_icm406xx_wr_gyro_config1_avg_filt_rate | ( | struct inv_icm406xx * | s,
|  | ICM406XX_GYRO_CONFIG1_AVG_FILT_RATE_t | new_value
| ) |  |

Set GYRO_CONFIG1 register AVG_FILT_RATE bit.

     1 in LPM Average filter runs 8KHz
     0 in LPM Average filter runs 1KHz

Parameters

  [in] | new_value | See enum ICM406XX_GYRO_CONFIG1_AVG_FILT_RATE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_int_cfg_int1_drive_circuit()

int inv_icm406xx_wr_int_cfg_int1_drive_circuit | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t | new_value
| ) |  |

Set INT_CONFIG register INT1_DRIVE_CIRCUIT bit.

When set to ‘1’, Interrupt 1 is in push-pull. When set to ‘0’, Interrupt 1 is in open drain

Parameters

  [in] | new_value | See enum ICM406XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_int_cfg_int1_polarity()

int inv_icm406xx_wr_int_cfg_int1_polarity | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INT_CONFIG_INT1_POLARITY_t | new_value
| ) |  |

Set INT_CONFIG register INT1_POLARITY bit.

When set to ‘1’, Interrupt 1 is active high When set to ‘0’, Interrupt 1 is active low

Parameters

  [in] | new_value | See enum ICM406XX_INT_CONFIG_INT1_POLARITY_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_int_config1_asy_rst_dis()

int inv_icm406xx_wr_int_config1_asy_rst_dis | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INT_CONFIG1_ASY_RST_t | new_value
| ) |  |

Set INT_CONFIG1 register ASY_RESET_DISABLE bit.

Parameters

  [in] | This | bit is not usable in Havana A1. Please set value of 1 always. Further details are described in use notes. (Intended operation for future chips: Removes the asynchronous clear of the interrupt output when disabling or cleaning all the active interrupt sources, action which may causes a cut on the interrupt pulse length in pulsed mode.)

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_int_source0()

int inv_icm406xx_wr_int_source0 | ( | struct inv_icm406xx * | s,
|  | uint8_t | new_value
| ) |  |

Set INT_SOURCE0 register value.

Parameters

  [in] | Interrupt | source

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_int_source1()

int inv_icm406xx_wr_int_source1 | ( | struct inv_icm406xx * | s,
|  | uint8_t | new_value
| ) |  |

Set INT_SOURCE1 register value.

Parameters

  [in] | Interrupt | source

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_intf_config0_data_endian()

int inv_icm406xx_wr_intf_config0_data_endian | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INTF_CONFIG0_DATA_COUNT_ENDIAN_t | new_value
| ) |  |

Set INTF_CONFIG0 register DATA_ENDIAN bit.

Selects whether DATA_ENDIAN[1:0] indicates the endianess.
When set to ‘1’ report data in big endian.
When set to ‘0’ report data in little endian.

Parameters

  [in] | new_value | See enum ICM406XX_INTF_CONFIG0_DATA_COUNT_ENDIAN_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_intf_config0_fifo_count_endian()

int inv_icm406xx_wr_intf_config0_fifo_count_endian | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t | new_value
| ) |  |

Set INTF_CONFIG0 register FIFO_COUNT_ENDIAN bit.

Selects whether FIFO_COUNT_ENDIAN[1:0] indicates the endianess.
When set to ‘1’ report FIFO count in big endian.
When set to ‘0’ report FIFO count in little endian.

Parameters

  [in] | new_value | See enum ICM406XX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_intf_config0_fifo_count_rec()

int inv_icm406xx_wr_intf_config0_fifo_count_rec | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INTF_CONFIG0_FIFO_COUNT_REC_t | new_value
| ) |  |

Set INTF_CONFIG0 register FIFO_COUNT_REC bit.

Selects whether FIFO_COUNT[1:0] indicates the number of records or number of bytes.
When set to ‘1’ report FIFO count in terms of records.
When set to ‘0’ report FIFO count in terms of bytes.

Parameters

  [in] | new_value | See enum ICM406XX_CONFIG_FIFO_COUNT_REC_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_intf_config0_fifo_sreg_invalid_ind()

int inv_icm406xx_wr_intf_config0_fifo_sreg_invalid_ind | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t | new_value
| ) |  |

Set INTF_CONFIG0 register FIFO_SREG_INVALID_IND bit.

Selects whether INVALID_IND[1:0] if INVALID_IND_DIS == 1 In FIFO: the last Valid and New sample is held and written into the FIFO upon reception of cnt_sreg_update. If no Valid and New sample had been received since the reset, 0x0000 will be written in FIFO In Sensor Data Registers: the last Valid and New sample is held If no Valid and New sample had been received since the reset, the register default value is read back (that is 0x8000)

Parameters

  [in] | new_value | See enum ICM406XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_intf_config0_spi_mode_ois1()

int inv_icm406xx_wr_intf_config0_spi_mode_ois1 | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INTF_CONFIG0_SPI_MODE_OIS1_t | new_value
| ) |  |

Set INTF_CONFIG0 register SPI_MODE_OIS1 bit.

Selects whether SPI_MODE_AUX1[1:0] indicates the SPI mode.
When set to ‘1’ Mode1 and Mode2.
When set to ‘0’ Mode0 and Mode3.

Parameters

  [in] | new_value | See enum ICM406XX_INTF_CONFIG0_SPI_MODE_OIS1_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_intf_config0_spi_mode_ois2()

int inv_icm406xx_wr_intf_config0_spi_mode_ois2 | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INTF_CONFIG0_SPI_MODE_OIS2_t | new_value
| ) |  |

Set INTF_CONFIG0 register SPI_MODE_AUX2 bit.

Selects whether SPI_MODE_AUX2[1:0] indicates the SPI mode.
When set to ‘1’ Mode1 and Mode2.
When set to ‘0’ Mode0 and Mode3.

Parameters

  [in] | new_value | See enum ICM406XX_INTF_CONFIG0_SPI_MODE_OIS2_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_intf_config1_accel_lp_clk_sel()

int inv_icm406xx_wr_intf_config1_accel_lp_clk_sel | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INTF_CONFIG1_ACCEL_LP_CLK_SEL_t | new_value
| ) |  |

Set INTF_CONFIG1 register ACCEL_LP_CLK_SEL bit.

Selects whether ACCEL_LP_CLK_SEL indicates the Accelerometer LP mode.
When set to ‘1’ Accelerometer LP mode uses RC Oscilator clock
When set to ‘0’ Accelerometer LP mode uses Wake Up oscilator clock.

Parameters

  [in] | new_value | See enum ICM406XX_INTF_CONFIG1_ACCEL_LP_CLK_SEL_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_intf_config4_ap_spi()

int inv_icm406xx_wr_intf_config4_ap_spi | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INTF_CONFIG4_AP_SPI_t | new_value
| ) |  |

Set INTF_CONFIG4_B1 register SPI_AP_4WIRE bit.

When set to ‘1’, SPI AP is in 4 wire interface When set to ‘0’, SPI AP is in 3 wire interface

Parameters

  [in] | new_value | See enum ICM406XX_INTF_CONFIG4_AP_SPI_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_intf_config4_aux_spi()

int inv_icm406xx_wr_intf_config4_aux_spi | ( | struct inv_icm406xx * | s,
|  | ICM406XX_INTF_CONFIG4_AUX_SPI_t | new_value
| ) |  |

Set INTF_CONFIG4_B1 register SPI_AUX1_4WIRE bit.

When set to ‘1’, SPI AUX is in 4 wire interface When set to ‘0’, SPI AUX is in 3 wire interface

Parameters

  [in] | new_value | See enum ICM406XX_INTF_CONFIG4_AUX_SPI_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_ois1_config1_dec()

int inv_icm406xx_wr_ois1_config1_dec | ( | struct inv_icm406xx * | s,
|  | ICM406XX_OIS1_CONFIG1_DEC_t | new_value
| ) |  |

Set AUX1_CONFIG1 register AUX1_DEC bit.

Decimation factor for auxiliary1 signal path (common to Gyro and Accel) 0 1 1 2 2 4 3 8 4 16 5 32 6 N/A 7 N/A

Parameters

  [in] | new_value | See enum ICM406XX_OIS1_CONFIG1_DEC_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_ois1_config1_gyro_en()

int inv_icm406xx_wr_ois1_config1_gyro_en | ( | struct inv_icm406xx * | s,
|  | ICM406XX_OIS1_CONFIG1_GYRO_EN_t | new_value
| ) |  |

Set AUX1_CONFIG1 register GYRO_AUX1_EN bit.

0 - Disable AUX 1 Path 1 - Enable AUX1 Path

Parameters

  [in] | new_value | See enum ICM406XX_OIS1_CONFIG1_EN_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_ois1_config2_gyro_fs_sel()

int inv_icm406xx_wr_ois1_config2_gyro_fs_sel | ( | struct inv_icm406xx * | s,
|  | ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_t | new_value
| ) |  |

Set AUX1_CONFIG2 register GYRO_AUX1_FS_SEL bit.

Gyro OIS Full Scale Select:
000 = ±2000dps
001 = ±1000dps
010 = ±500dps
011 = ±250dps
100 = ±125dps
101 = ±62dps
110 = ±31dps
111 = ±16dps

Parameters

  [in] | new_value | See enum ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_ois2_config1_dec()

int inv_icm406xx_wr_ois2_config1_dec | ( | struct inv_icm406xx * | s,
|  | ICM406XX_OIS2_CONFIG1_DEC_t | new_value
| ) |  |

Set AUX2_CONFIG1 register AUX2_DEC bit.

Decimation factor for auxiliary2 signal path (common to Gyro and Accel) 0 1 1 2 2 4 3 8 4 16 5 32 6 N/A 7 N/A

Parameters

  [in] | new_value | See enum ICM406XX_OIS2_CONFIG1_DEC_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_ois2_config1_gyro_en()

int inv_icm406xx_wr_ois2_config1_gyro_en | ( | struct inv_icm406xx * | s,
|  | ICM406XX_OIS2_CONFIG1_GYRO_EN_t | new_value
| ) |  |

Set AUX2_CONFIG1 register GYRO_AUX2_EN bit.

0 - Disable AUX2 Path 1 - Enable AUX2 Path

Parameters

  [in] | new_value | See enum ICM406XX_OIS2_CONFIG1_EN_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_ois2_config2_gyro_fs_sel()

int inv_icm406xx_wr_ois2_config2_gyro_fs_sel | ( | struct inv_icm406xx * | s,
|  | ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_t | new_value
| ) |  |

Set AUX2_CONFIG2 register GYRO_AUX2_FS_SEL bit.

Gyro OIS Full Scale Select:
000 = ±2000dps
001 = ±1000dps
010 = ±500dps
011 = ±250dps
100 = ±125dps
101 = ±62dps
110 = ±31dps
111 = ±16dps

Parameters

  [in] | new_value | See enum ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_pwr_mgmt0_accel_mode()

int inv_icm406xx_wr_pwr_mgmt0_accel_mode | ( | struct inv_icm406xx * | s,
|  | ICM406XX_PWR_MGMT_0_ACCEL_MODE_t | new_value
| ) |  |

Set PWR_MGMT_0 register ACCEL_MODE bit.

     3 – accel low noise mode
     2 – accel low power mode
     0 – accel off

Parameters

  [in] | new_value | See enum ICM406XX_PWR_MGMT_0_ACCEL_MODE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_pwr_mgmt0_gyro_mode()

int inv_icm406xx_wr_pwr_mgmt0_gyro_mode | ( | struct inv_icm406xx * | s,
|  | ICM406XX_PWR_MGMT_0_GYRO_MODE_t | new_value
| ) |  |

Set PWR_MGMT_0 register GYRO_MODE bit.

     3 – gyro low noise mode
     0 – gyro off

note : others modes are not supported for gyro on 406xx

Parameters

  [in] | new_value | See enum ICM406XX_PWR_MGMT_0_GYRO_MODE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_pwr_mgmt0_temp_en()

int inv_icm406xx_wr_pwr_mgmt0_temp_en | ( | struct inv_icm406xx * | s,
|  | ICM406XX_PWR_MGMT_0_TEMP_t | new_value
| ) |  |

Set PWR_MGMT_0 register TEMP_DIS bit.

     1 – disable temperature sensor
     0 – enable temperature sensor

Parameters

  [in] | new_value | See enum ICM406XX_PWR_MGMT_0_TEMP_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_reg_bank_sel()

int inv_icm406xx_wr_reg_bank_sel | ( | struct inv_icm406xx * | s,
|  | uint8_t | new_value
| ) |  |

Set REG_BANK_SEL register value.

Register to select bank of registers to be accessed with subsequent register access.

Parameters

  [in] | value | Bank to be selected.

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_signal_path_rst_fifo_flush()

int inv_icm406xx_wr_signal_path_rst_fifo_flush | ( | struct inv_icm406xx * | s,
|  | ICM406XX_SIGNAL_PATH_RESET_FIFO_FLUSH_t | new_value
| ) |  |

Set SIGNAL_PATH_RESET register FIFO_FLUSH bit.

     1 – Fifo flush enable
     0 – Fifo flush disable

Parameters

  [in] | new_value | See enum ICM406XX_SIGNAL_PATH_RESET_FIFO_FLUSH_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_signal_path_rst_tmst_strobe()

int inv_icm406xx_wr_signal_path_rst_tmst_strobe | ( | struct inv_icm406xx * | s,
|  | ICM406XX_SIGNAL_PATH_RESET_TMST_STROBE_t | new_value
| ) |  |

Set SIGNAL_PATH_RESET register TMST_STROBE bit.

     1 – Timestamp counter is latched into timestamp register
     0 – Disable

Parameters

  [in] | new_value | See enum ICM406XX_SIGNAL_PATH_RESET_TMST_STROBE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_smd_config_smd_mode()

int inv_icm406xx_wr_smd_config_smd_mode | ( | struct inv_icm406xx * | s,
|  | ICM406XX_SMD_CONFIG_SMD_MODE_t | new_value
| ) |  |

Set MPUREG_SMD_CONFIG register SMD_MODE bit.

     3 - SMD long (3 sec wait)
     2 - SMD short (1 sec wait)
     1 – WOM using old definition
     0 – Disabled

Parameters

  [in] | new_value | See enum ICM406XX_SMD_CONFIG_SMD_MODE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_smd_config_wom_int_mode()

int inv_icm406xx_wr_smd_config_wom_int_mode | ( | struct inv_icm406xx * | s,
|  | ICM406XX_SMD_CONFIG_WOM_INT_MODE_t | new_value
| ) |  |

Set MPUREG_SMD_CONFIG register WOM_INT_MODE bit.

     1 – The WoM from 3 axis are ANDed to produce WoM signal
     0 – The WoM from 3 axis are ORed to produce WoM signal

Parameters

  [in] | new_value | See enum ICM406XX_SMD_CONFIG_WOM_INT_MODE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_smd_config_wom_mode()

int inv_icm406xx_wr_smd_config_wom_mode | ( | struct inv_icm406xx * | s,
|  | ICM406XX_SMD_CONFIG_WOM_MODE_t | new_value
| ) |  |

Set MPUREG_SMD_CONFIG register WOM_MODE bit.

     1 – Compare current sample to previous sample
     0 – Initial sample is stored. Future samples are compared to initial

Parameters

  [in] | new_value | See enum ICM406XX_SMD_CONFIG_WOM_MODE_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_tmst_config_en()

int inv_icm406xx_wr_tmst_config_en | ( | struct inv_icm406xx * | s,
|  | ICM406XX_TMST_CONFIG_TMST_EN_t | new_value
| ) |  |

Set TMST_CONFIG register ICM406XX_TMST_CONFIG_EN bit.

When set to ‘1’, Timestamp register enable. When set to ‘0’, Timestamp register disable

Parameters

  [in] | new_value | See enum ICM406XX_TMST_CONFIG_TMST_EN_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_tmst_config_fsync_en()

int inv_icm406xx_wr_tmst_config_fsync_en | ( | struct inv_icm406xx * | s,
|  | ICM406XX_TMST_CONFIG_TMST_FSYNC_EN_t | new_value
| ) |  |

Set TMST_CONFIG register TMST_FSYNC bit.

When set to ‘1’, Timestamp fsync enable. When set to ‘0’, Timestamp fsync disable

Parameters

  [in] | new_value | See enum ICM406XX_TMST_CONFIG_TMST_FSYNC_EN_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_tmst_config_resolution()

int inv_icm406xx_wr_tmst_config_resolution | ( | struct inv_icm406xx * | s,
|  | ICM406XX_TMST_CONFIG_RESOL_t | new_value
| ) |  |

Set TMST_CONFIG register TMST_RES bit.

When set to ‘1’, Timestamp 16us resolution. When set to ‘0’, Timestamp 1us resolution

Parameters

  [in] | new_value | See enum ICM406XX_TMST_CONFIG_RESOL_t

Returns
  0 in case of success, negative value on error. See enum inv_error

## ◆ inv_icm406xx_wr_tmst_config_tmst_to_reg()

int inv_icm406xx_wr_tmst_config_tmst_to_reg | ( | struct inv_icm406xx * | s,
|  | ICM406XX_TMST_CONFIG_TMST_TO_REGS_EN_t | new_value
| ) |  |

Set TMST_CONFIG register TMST_TO_REGS_EN bit.

When set to ‘1’, Timestamp to register enable. When set to ‘0’, Timestamp to register disable

Parameters

  [in] | new_value | See enum ICM406XX_TMST_CONFIG_TMST_TO_REGS_EN_t

Returns
  0 in case of success, negative value on error. See enum inv_error