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Icm406xxDefs.h
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1 /*
2 * ________________________________________________________________________________________________________
3 * Copyright (c) 2017 InvenSense Inc. All rights reserved.
4 *
5 * This software, related documentation and any modifications thereto (collectively “Software”) is subject
6 * to InvenSense and its licensors' intellectual property rights under U.S. and international copyright
7 * and other intellectual property rights laws.
8 *
9 * InvenSense and its licensors retain all intellectual property and proprietary rights in and to the Software
10 * and any use, reproduction, disclosure or distribution of the Software without an express license agreement
11 * from InvenSense is strictly prohibited.
12 *
13 * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE SOFTWARE IS
14 * PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
15 * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
16 * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL
17 * INVENSENSE BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY
18 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
19 * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THE SOFTWARE.
21 * ________________________________________________________________________________________________________
22 */
23
24 #ifndef _INV_ICM406XX_DEFS_H_
25 #define _INV_ICM406XX_DEFS_H_
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
35 #include <stdint.h>
36
37 /* forward declaration */
38 struct inv_icm406xx;
39
40 /* ----------------------------------------------------------------------------
41 * Device Register map
42 *
43 * Next macros defines address for all icm406xx registers as listed by device
44 * datasheet.
45 * Macros name is MPUREG_<REGISTER_NAME> with REGISTER_NAME being the name of
46 * the corresponding register in datasheet.
47 * Note that macro name is MPUREG_<REGISTER_NAME>_Bx with x being the bank
48 * number for registers that are in bank 1 and 2 (suffix is ommitted for
49 * bank0 registers)
50 * ---------------------------------------------------------------------------- */
51
52 /* Bank 0 */
53 #define MPUREG_DEVICE_CONFIG 0x11
54 #define MPUREG_DRIVE_CONFIG 0x19
55 #define MPUREG_INT_CONFIG 0x14
56 #define MPUREG_FIFO_CONFIG 0x16
57 #define MPUREG_TEMP_DATA1_UI 0x1D
58 #define MPUREG_TEMP_DATA0_UI 0x1E
59 #define MPUREG_ACCEL_DATA_X1_UI 0x1F
60 #define MPUREG_ACCEL_DATA_X0_UI 0x20
61 #define MPUREG_ACCEL_DATA_Y1_UI 0x21
62 #define MPUREG_ACCEL_DATA_Y0_UI 0x22
63 #define MPUREG_ACCEL_DATA_Z1_UI 0x23
64 #define MPUREG_ACCEL_DATA_Z0_UI 0x24
65 #define MPUREG_GYRO_DATA_X1_UI 0x25
66 #define MPUREG_GYRO_DATA_X0_UI 0x26
67 #define MPUREG_GYRO_DATA_Y1_UI 0x27
68 #define MPUREG_GYRO_DATA_Y0_UI 0x28
69 #define MPUREG_GYRO_DATA_Z1_UI 0x29
70 #define MPUREG_GYRO_DATA_Z0_UI 0x2A
71 #define MPUREG_TMST_FSYNCH 0x2B
72 #define MPUREG_TMST_FSYNCL 0x2C
73 #define MPUREG_INT_STATUS 0x2D
74 #define MPUREG_FIFO_COUNTH 0x2E
75 #define MPUREG_FIFO_COUNTL 0x2F
76 #define MPUREG_FIFO_DATA 0x30
77 #define MPUREG_SIGNAL_PATH_RESET 0x4B
78 #define MPUREG_INTF_CONFIG0 0x4C
79 #define MPUREG_INTF_CONFIG1 0x4D
80 #define MPUREG_PWR_MGMT_0 0x4E
81 #define MPUREG_GYRO_CONFIG0 0x4F
82 #define MPUREG_ACCEL_CONFIG0 0x50
83 #define MPUREG_GYRO_CONFIG1 0x51
84 #define MPUREG_GYRO_ACCEL_CONFIG0 0x52
85 #define MPUREG_ACCEL_CONFIG1 0x53
86 #ifndef ICM40609D
87 #define MPUREG_ACCEL_WOM_X_THR 0x54
88 #define MPUREG_ACCEL_WOM_Y_THR 0x55
89 #define MPUREG_ACCEL_WOM_Z_THR 0x56
90 #endif
91 #define MPUREG_SMD_CONFIG 0x57
92 #ifdef ICM40609D
93 #define MPUREG_INT_STATUS2 0x37
94 #define MPUREG_TMST_CONFIG 0x54
95 #define MPUREG_WOM_CONFIG 0x57
96 #else
97 #define MPUREG_INT_STATUS2 0x59
98 #define MPUREG_TMST_CONFIG 0x5A
99 #endif
100 #define MPUREG_FIFO_CONFIG1 0x5F
101 #define MPUREG_FIFO_CONFIG2 0x60
102 #define MPUREG_FIFO_CONFIG3 0x61
103 #define MPUREG_FSYNC_CONFIG 0x62
104 #define MPUREG_INT_CONFIG0 0x63
105 #define MPUREG_INT_CONFIG1 0x64
106 #define MPUREG_INT_SOURCE0 0x65
107 #define MPUREG_INT_SOURCE1 0x66
108 #define MPUREG_INT_SOURCE2 0x67
109 #define MPUREG_INT_SOURCE3 0x68
110 #define MPUREG_INT_SOURCE4 0x69
111 #define MPUREG_INT_SOURCE5 0x6A
112 #define MPUREG_FIFO_LOST_PKT0 0x6C
113 #define MPUREG_FIFO_LOST_PKT1 0x6D
114 #define MPUREG_SELF_TEST_CONFIG 0x70
115 #define MPUREG_WHO_AM_I 0x75
116 #define MPUREG_REG_BANK_SEL 0x76
117 #define MPUREG_GOS_USER0 0x77
118 #define MPUREG_GOS_USER1 0x78
119 #define MPUREG_GOS_USER2 0x79
120 #define MPUREG_GOS_USER3 0x7A
121 #define MPUREG_GOS_USER4 0x7B
122 #define MPUREG_GOS_USER5 0x7C
123 #define MPUREG_GOS_USER6 0x7D
124 #define MPUREG_GOS_USER7 0x7E
125 #define MPUREG_GOS_USER8 0x7F
126
127 /* Bank 1 */
128 #define MPUREG_SENSOR_CONFIG0 0x03
129 #define MPUREG_GYRO_CONFIG_STATIC2_B1 0x0B
130 #define MPUREG_GYRO_CONFIG_STATIC3_B1 0x0C
131 #define MPUREG_GYRO_CONFIG_STATIC4_B1 0x0D
132 #define MPUREG_GYRO_CONFIG_STATIC5_B1 0x0E
133 #define MPUREG_GYRO_CONFIG_STATIC6_B1 0x0F
134 #define MPUREG_GYRO_CONFIG_STATIC7_B1 0x10
135 #define MPUREG_GYRO_CONFIG_STATIC8_B1 0x11
136 #define MPUREG_GYRO_CONFIG_STATIC9_B1 0x12
137 #define MPUREG_GYRO_CONFIG_STATIC10_B1 0x13
138 #define MPUREG_XG_ST_DATA_B1 0x5F
139 #define MPUREG_YG_ST_DATA_B1 0x60
140 #define MPUREG_ZG_ST_DATA_B1 0x61
141 #define MPUREG_TMST_VAL0_B1 0x62
142 #define MPUREG_TMST_VAL1_B1 0x63
143 #define MPUREG_TMST_VAL2_B1 0x64
144 #define MPUREG_INTF_CONFIG4_B1 0x7A
145
146 /* Bank 2 */
147 #define MPU_ACCEL_CONFIG_STATIC2_B2 0x03
148 #define MPU_ACCEL_CONFIG_STATIC3_B2 0x04
149 #define MPU_ACCEL_CONFIG_STATIC4_B2 0x05
150 #define MPUREG_XA_ST_DATA_B2 0x3B
151 #define MPUREG_YA_ST_DATA_B2 0x3C
152 #define MPUREG_ZA_ST_DATA_B2 0x3D
153
154 #define MPUREG_AUX1_CONFIG1_B2 0x44
155 #define MPUREG_AUX1_CONFIG2_B2 0x45
156 #define MPUREG_AUX1_CONFIG3_B2 0x46
157 #define MPUREG_TEMP_DATA0_AUX1_B2 0x47
158 #define MPUREG_TEMP_DATA1_AUX1_B2 0x48
159 #define MPUREG_ACCEL_DATA_X0_AUX1_B2 0x49
160 #define MPUREG_ACCEL_DATA_X1_AUX1_B2 0x4A
161 #define MPUREG_ACCEL_DATA_Y0_AUX1_B2 0x4B
162 #define MPUREG_ACCEL_DATA_Y1_AUX1_B2 0x4C
163 #define MPUREG_ACCEL_DATA_Z0_AUX1_B2 0x4D
164 #define MPUREG_ACCEL_DATA_Z1_AUX1_B2 0x4E
165 #define MPUREG_GYRO_DATA_X0_AUX1_B2 0x4F
166 #define MPUREG_GYRO_DATA_X1_AUX1_B2 0x50
167 #define MPUREG_GYRO_DATA_Y0_AUX1_B2 0x51
168 #define MPUREG_GYRO_DATA_Y1_AUX1_B2 0x52
169 #define MPUREG_GYRO_DATA_Z0_AUX1_B2 0x53
170 #define MPUREG_GYRO_DATA_Z1_AUX1_B2 0x54
171 #define MPUREG_TMSTVAL0_AUX1_B2 0x55
172 #define MPUREG_TMSTVAL1_AUX1_B2 0x56
173 #define MPUREG_INT_STATUS_AUX1_B2 0x57
174
175 #define MPUREG_AUX2_CONFIG1_B2 0x59
176 #define MPUREG_AUX2_CONFIG2_B2 0x5A
177 #define MPUREG_AUX2_CONFIG3_B2 0x5B
178 #define MPUREG_TEMP_DATA0_AUX2_B2 0x5C
179 #define MPUREG_TEMP_DATA1_AUX2_B2 0x5D
180 #define MPUREG_ACCEL_DATA_X0_AUX2_B2 0x5E
181 #define MPUREG_ACCEL_DATA_X1_AUX2_B2 0x5F
182 #define MPUREG_ACCEL_DATA_Y0_AUX2_B2 0x60
183 #define MPUREG_ACCEL_DATA_Y1_AUX2_B2 0x61
184 #define MPUREG_ACCEL_DATA_Z0_AUX2_B2 0x62
185 #define MPUREG_ACCEL_DATA_Z1_AUX2_B2 0x63
186 #define MPUREG_GYRO_DATA_X0_AUX2_B2 0x64
187 #define MPUREG_GYRO_DATA_X1_AUX2_B2 0x65
188 #define MPUREG_GYRO_DATA_Y0_AUX2_B2 0x66
189 #define MPUREG_GYRO_DATA_Y1_AUX2_B2 0x67
190 #define MPUREG_GYRO_DATA_Z0_AUX2_B2 0x68
191 #define MPUREG_GYRO_DATA_Z1_AUX2_B2 0x69
192 #define MPUREG_TMSTVAL0_AUX2_B2 0x6A
193 #define MPUREG_TMSTVAL1_AUX2_B2 0x6B
194 #define MPUREG_INT_STATUS_AUX2_B2 0x6C
195
196 #ifdef ICM40609D
197 /* Bank 4 */
198 #define MPUREG_ACCEL_WOM_X_THR 0x4A
199 #define MPUREG_ACCEL_WOM_Y_THR 0x4B
200 #define MPUREG_ACCEL_WOM_Z_THR 0x4C
201 #endif
202 #define MPUREG_OFFSET_USER0_B4 0x77
203 #define MPUREG_OFFSET_USER1_B4 0x78
204 #define MPUREG_OFFSET_USER2_B4 0x79
205 #define MPUREG_OFFSET_USER3_B4 0x7A
206 #define MPUREG_OFFSET_USER4_B4 0x7B
207 #define MPUREG_OFFSET_USER5_B4 0x7C
208 #define MPUREG_OFFSET_USER6_B4 0x7D
209 #define MPUREG_OFFSET_USER7_B4 0x7E
210 #define MPUREG_OFFSET_USER8_B4 0x7F
211
212 /* ----------------------------------------------------------------------------
213 * Device features
214 *
215 * Next macros define some of the device features such as FIFO, sensor data
216 * size or whoami value.
217 * ---------------------------------------------------------------------------- */
218
219 #define ICM40609D_WHOAMI 0x3B
220 #define ICM40605_WHOAMI 0x33
221 #define ICM40604_WHOAMI 0x32
222 #define ICM40602_WHOAMI 0x31
223
224 #define ACCEL_DATA_SIZE 6
225 #define GYRO_DATA_SIZE 6
226
227 #define FIFO_HEADER_SIZE 1
228 #define FIFO_ACCEL_DATA_SIZE ACCEL_DATA_SIZE
229 #define FIFO_GYRO_DATA_SIZE GYRO_DATA_SIZE
230 #define FIFO_TEMP_DATA_SIZE 1
231 #define FIFO_TS_FSYNC_SIZE 2
232
233 #define FIFO_16BYTES_PACKET_SIZE \
234 (FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + \
235 FIFO_TS_FSYNC_SIZE)
236
237 #define FIFO_HEADER_ODR_ACCEL 0x01
238 #define FIFO_HEADER_ODR_GYRO 0x02
239 #define FIFO_HEADER_FSYNC 0x04
240 #define FIFO_HEADER_TMST 0x08
241 #define FIFO_HEADER_HEADER_20 0x10
242 #define FIFO_HEADER_GYRO 0x20
243 #define FIFO_HEADER_ACC 0x40
244 #define FIFO_HEADER_MSG 0x80
245
246 #define INVALID_VALUE_FIFO ((int16_t)0x8000)
247 #define INVALID_VALUE_FIFO_1B ((int8_t)0x80)
248
249 typedef union {
250 unsigned char Byte;
251 struct {
252 unsigned char gyro_20bit_ext : 1;
253 unsigned char accel_20bit_ext : 1;
254 unsigned char fsync_bit : 1;
255 unsigned char timestamp_bit : 1;
256 unsigned char twentybits_bit : 1;
257 unsigned char gyro_bit : 1;
258 unsigned char accel_bit : 1;
259 unsigned char msg_bit : 1;
260 } bits;
261 } fifo_header_t;
262
263 /* ----------------------------------------------------------------------------
264 * Device registers description
265 *
266 * Next section defines some of the registers bitfield and declare corresponding
267 * accessors.
268 * Note that descriptors and accessors are not provided for all the registers
269 * but only for the most useful ones.
270 * For all details on registers and bitfields functionalities please refer to
271 * the device datasheet.
272 * ---------------------------------------------------------------------------- */
273
274 /* ---------------------------------------------------------------------------
275 * register bank 0
276 * ---------------------------------------------------------------------------- */
277
278 /*
279 * MPUREG_DEVICE_CONFIG
280 * Register Name : DEVICE_CONFIG
281 */
282
283 /* SPI_MODE */
284 #define BIT_DEVICE_CONFIG_SPI_MODE_POS 1
285 #define BIT_DEVICE_CONFIG_SPI_MODE_MASK (0x1 << BIT_DEVICE_CONFIG_SPI_MODE_POS)
286
287 typedef enum {
288 ICM406XX_DEVICE_CONFIG_SPI_MODE_1_2 = (0x1 << BIT_DEVICE_CONFIG_SPI_MODE_POS),
289 ICM406XX_DEVICE_CONFIG_SPI_MODE_0_3 = (0x0 << BIT_DEVICE_CONFIG_SPI_MODE_POS),
290 } ICM406XX_DEVICE_CONFIG_SPI_MODE_t;
291
292 int inv_icm406xx_wr_device_config_spi_mode(struct inv_icm406xx * s,
293 ICM406XX_DEVICE_CONFIG_SPI_MODE_t new_value);
294
295 /* SOFT_RESET_CONFIG */
296 #define BIT_DEVICE_CONFIG_RESET_POS 0
297 #define BIT_DEVICE_CONFIG_RESET_MASK 0x01
298 typedef enum {
299 ICM406XX_DEVICE_CONFIG_RESET_EN = 0x01,
300 ICM406XX_DEVICE_CONFIG_RESET_NONE = 0x00,
301 } ICM406XX_DEVICE_CONFIG_RESET_t;
302
303 int inv_icm406xx_wr_device_config_reset(struct inv_icm406xx * s,
304 ICM406XX_DEVICE_CONFIG_RESET_t new_value);
305
306 /*
307 * MPUREG_INT_CONFIG
308 * Register Name: INT_CONFIG
309 */
310
311 /* INT1_DRIVE_CIRCUIT */
312 #define BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS 1
313 #define BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS)
314
315 typedef enum {
316 ICM406XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_PP = (0x01 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS),
317 ICM406XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_OD = (0x00 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS),
318 } ICM406XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t;
319
320 int inv_icm406xx_wr_int_cfg_int1_drive_circuit(struct inv_icm406xx * s,
321 ICM406XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t new_value);
322
323 /* INT1_POLARITY */
324 #define BIT_INT_CONFIG_INT1_POLARITY_POS 0
325 #define BIT_INT_CONFIG_INT1_POLARITY_MASK 0x01
326
327 typedef enum {
328 ICM406XX_INT_CONFIG_INT1_POLARITY_HIGH = 0x01,
329 ICM406XX_INT_CONFIG_INT1_POLARITY_LOW = 0x00,
330 } ICM406XX_INT_CONFIG_INT1_POLARITY_t;
331
332 int inv_icm406xx_wr_int_cfg_int1_polarity(struct inv_icm406xx * s,
333 ICM406XX_INT_CONFIG_INT1_POLARITY_t new_value);
334
335 /*
336 * MPUREG_FIFO_CONFIG
337 * Register Name: FIFO_CONFIG
338 */
339
340 /* FIFO_MODE */
341 #define BIT_FIFO_CONFIG_MODE_POS 6
342 #define BIT_FIFO_CONFIG_MODE_MASK (0x03 << BIT_FIFO_CONFIG_MODE_POS)
343
344 typedef enum {
345 ICM406XX_FIFO_CONFIG_MODE_SNAPSHOT = (0x02 << BIT_FIFO_CONFIG_MODE_POS),
346 ICM406XX_FIFO_CONFIG_MODE_STREAM = (0x01 << BIT_FIFO_CONFIG_MODE_POS),
347 ICM406XX_FIFO_CONFIG_MODE_BYPASS = (0x00 << BIT_FIFO_CONFIG_MODE_POS),
348 } ICM406XX_FIFO_CONFIG_MODE_t;
349
350 int inv_icm406xx_wr_fifo_config_mode(struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG_MODE_t new_value);
351 int inv_icm406xx_rd_fifo_config_mode(struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG_MODE_t *value);
352
353 /*
354 * MPUREG_INT_STATUS
355 * Register Name: INT_STATUS
356 */
357 #define BIT_INT_STATUS_UI_FSYNC 0x40
358 #define BIT_INT_STATUS_PLL_RDY 0x20
359 #define BIT_INT_STATUS_RESET_DONE 0x10
360 #define BIT_INT_STATUS_DRDY 0x08
361 #define BIT_INT_STATUS_FIFO_THS 0x04
362 #define BIT_INT_STATUS_FIFO_FULL 0x02
363 #define BIT_INT_STATUS_AGC_RDY 0x01
364 int inv_icm406xx_rd_int_status(struct inv_icm406xx *s, uint8_t *value);
365
366 /*
367 * MPUREG_FIFO_COUNTL - MPUREG_FIFO_COUNTH
368 * Register Name: FIFO_COUNTL - FIFO_COUNTH
369 */
370 int inv_icm406xx_rd_fifo_count(struct inv_icm406xx *s, uint8_t value[2]);
371
372 /*
373 * MPUREG_FIFO_DATA
374 * Register Name: FIFO_DATA_REG
375 */
376 int inv_icm406xx_rd_fifo(struct inv_icm406xx *s, int len, uint8_t *value);
377
378 /*
379 * MPUREG_SIGNAL_PATH_RESET
380 * Register Name: SIGNAL_PATH_RESET
381 */
382
383 /* TMST_STROBE */
384 #define BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS 2
385 #define BIT_SIGNAL_PATH_RESET_TMST_STROBE_MASK (0x01 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS)
386
387 typedef enum {
388 ICM406XX_SIGNAL_PATH_RESET_TMST_STROBE_EN = (0x01 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS),
389 ICM406XX_SIGNAL_PATH_RESET_TMST_STROBE_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS),
390 } ICM406XX_SIGNAL_PATH_RESET_TMST_STROBE_t;
391
392 int inv_icm406xx_wr_signal_path_rst_tmst_strobe(struct inv_icm406xx * s,
393 ICM406XX_SIGNAL_PATH_RESET_TMST_STROBE_t new_value);
394
395 /* FIFO_FLUSH */
396 #define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS 1
397 #define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_MASK (0x01 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS)
398
399 typedef enum {
400 ICM406XX_SIGNAL_PATH_RESET_FIFO_FLUSH_EN = (0x01 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS),
401 ICM406XX_SIGNAL_PATH_RESET_FIFO_FLUSH_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS),
402 } ICM406XX_SIGNAL_PATH_RESET_FIFO_FLUSH_t;
403
404 int inv_icm406xx_wr_signal_path_rst_fifo_flush(struct inv_icm406xx * s,
405 ICM406XX_SIGNAL_PATH_RESET_FIFO_FLUSH_t new_value);
406
407 /*
408 * MPUREG_INTF_CONFIG0
409 * Register Name: INTF_CONFIG0
410 */
411
412 /* FIFO_SREG_INVALID_IND */
413 #define BIT_FIFO_SREG_INVALID_IND_POS 7
414 #define BIT_FIFO_SREG_INVALID_IND_MASK (0x01 << BIT_FIFO_SREG_INVALID_IND_POS)
415
416 typedef enum {
417 ICM406XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_DIS = (0x01 << BIT_FIFO_SREG_INVALID_IND_POS),
418 ICM406XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_EN = (0x00 << BIT_FIFO_SREG_INVALID_IND_POS),
419 } ICM406XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t;
420
421 int inv_icm406xx_wr_intf_config0_fifo_sreg_invalid_ind(
422 struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t new_value);
423
424 /* FIFO_COUNT_REC */
425 #define BIT_FIFO_COUNT_REC_POS 6
426 #define BIT_FIFO_COUNT_REC_MASK (0x01 << BIT_FIFO_COUNT_REC_POS)
427
428 typedef enum {
429 ICM406XX_INTF_CONFIG0_FIFO_COUNT_REC_RECORD = (0x01 << BIT_FIFO_COUNT_REC_POS),
430 ICM406XX_INTF_CONFIG0_FIFO_COUNT_REC_BYTE = (0x00 << BIT_FIFO_COUNT_REC_POS),
431 } ICM406XX_INTF_CONFIG0_FIFO_COUNT_REC_t;
432
433 int inv_icm406xx_wr_intf_config0_fifo_count_rec(struct inv_icm406xx * s,
434 ICM406XX_INTF_CONFIG0_FIFO_COUNT_REC_t new_value);
435
436 /* FIFO_COUNT_ENDIAN */
437 #define BIT_FIFO_COUNT_ENDIAN_POS 5
438 #define BIT_FIFO_COUNT_ENDIAN_MASK (0x01 << BIT_FIFO_COUNT_ENDIAN_POS)
439
440 typedef enum {
441 ICM406XX_INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN = (0x01 << BIT_FIFO_COUNT_ENDIAN_POS),
442 ICM406XX_INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN = (0x00 << BIT_FIFO_COUNT_ENDIAN_POS),
443 } ICM406XX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t;
444
445 int inv_icm406xx_wr_intf_config0_fifo_count_endian(
446 struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t new_value);
447
448 /* DATA_ENDIAN */
449 #define BIT_DATA_ENDIAN_POS 4
450 #define BIT_DATA_ENDIAN_MASK (0x01 << BIT_DATA_ENDIAN_POS)
451
452 typedef enum {
453 ICM406XX_INTF_CONFIG0_DATA_BIG_ENDIAN = (0x01 << BIT_DATA_ENDIAN_POS),
454 ICM406XX_INTF_CONFIG0_DATA_LITTLE_ENDIAN = (0x00 << BIT_DATA_ENDIAN_POS),
455 } ICM406XX_INTF_CONFIG0_DATA_COUNT_ENDIAN_t;
456
457 int inv_icm406xx_wr_intf_config0_data_endian(struct inv_icm406xx * s,
458 ICM406XX_INTF_CONFIG0_DATA_COUNT_ENDIAN_t new_value);
459 int inv_icm406xx_rd_intf_config0_data_endian(struct inv_icm406xx * s,
460 ICM406XX_INTF_CONFIG0_DATA_COUNT_ENDIAN_t *value);
461
462 /* SPI_MODE_AUX2 */
463 #define BIT_SPI_MODE_OIS2_POS 3
464 #define BIT_SPI_MODE_OIS2_MASK (0x01 << BIT_SPI_MODE_OIS2_POS)
465
466 typedef enum {
467 ICM406XX_INTF_CONFIG0_SPI_MODE_OIS2_1_2 = (0x01 << BIT_SPI_MODE_OIS2_POS),
468 ICM406XX_INTF_CONFIG0_SPI_MODE_OIS2_0_3 = (0x00 << BIT_SPI_MODE_OIS2_POS),
469 } ICM406XX_INTF_CONFIG0_SPI_MODE_OIS2_t;
470
471 int inv_icm406xx_wr_intf_config0_spi_mode_ois2(struct inv_icm406xx * s,
472 ICM406XX_INTF_CONFIG0_SPI_MODE_OIS2_t new_value);
473
474 /* SPI_MODE_AUX1 */
475 #define BIT_SPI_MODE_OIS1_POS 2
476 #define BIT_SPI_MODE_OIS1_MASK (0x01 << BIT_SPI_MODE_OIS1_POS)
477
478 typedef enum {
479 ICM406XX_INTF_CONFIG0_SPI_MODE_OIS1_1_2 = (0x01 << BIT_SPI_MODE_OIS1_POS),
480 ICM406XX_INTF_CONFIG0_SPI_MODE_OIS1_0_3 = (0x00 << BIT_SPI_MODE_OIS1_POS),
481 } ICM406XX_INTF_CONFIG0_SPI_MODE_OIS1_t;
482
483 int inv_icm406xx_wr_intf_config0_spi_mode_ois1(struct inv_icm406xx * s,
484 ICM406XX_INTF_CONFIG0_SPI_MODE_OIS1_t new_value);
485
486 /*
487 * MPUREG_INTF_CONFIG1
488 * Register Name: INTF_CONFIG1
489 */
490
491 /* FIFO_SREG_INVALID_IND */
492 #define BIT_ACCEL_LP_CLK_POS 3
493 #define BIT_ACCEL_LP_CLK_MASK (0x01 << BIT_ACCEL_LP_CLK_POS)
494
495 typedef enum {
496 ICM406XX_INTF_CONFIG1_ACCEL_LP_CLK_SEL_RC = (0x01 << BIT_ACCEL_LP_CLK_POS),
497 ICM406XX_INTF_CONFIG1_ACCEL_LP_CLK_SEL_WU = (0x00 << BIT_ACCEL_LP_CLK_POS),
498 } ICM406XX_INTF_CONFIG1_ACCEL_LP_CLK_SEL_t;
499
500 int inv_icm406xx_wr_intf_config1_accel_lp_clk_sel(
501 struct inv_icm406xx *s, ICM406XX_INTF_CONFIG1_ACCEL_LP_CLK_SEL_t new_value);
502
503 /*
504 * MPUREG_PWR_MGMT_0
505 * Register Name: PWR_MGMT_0
506 */
507
508 /* TEMP_DIS */
509 #define BIT_PWR_MGMT_0_TEMP_POS 5
510 #define BIT_PWR_MGMT_0_TEMP_MASK (0x01 << BIT_PWR_MGMT_0_TEMP_POS)
511
512 typedef enum {
513 ICM406XX_PWR_MGMT_0_TEMP_DIS = (0x01 << BIT_PWR_MGMT_0_TEMP_POS),
514 ICM406XX_PWR_MGMT_0_TEMP_EN = (0x00 << BIT_PWR_MGMT_0_TEMP_POS),
515 } ICM406XX_PWR_MGMT_0_TEMP_t;
516
517 int inv_icm406xx_wr_pwr_mgmt0_temp_en(struct inv_icm406xx *s, ICM406XX_PWR_MGMT_0_TEMP_t new_value);
518 int inv_icm406xx_rd_pwr_mgmt0_temp_en(struct inv_icm406xx *s, ICM406XX_PWR_MGMT_0_TEMP_t *value);
519
520 /* GYRO_MODE */
521 #define BIT_PWR_MGMT_0_GYRO_MODE_POS 2
522 #define BIT_PWR_MGMT_0_GYRO_MODE_MASK (0x03 << BIT_PWR_MGMT_0_GYRO_MODE_POS)
523
524 typedef enum {
525 ICM406XX_PWR_MGMT_0_GYRO_MODE_LN = (0x03 << BIT_PWR_MGMT_0_GYRO_MODE_POS),
526 ICM406XX_PWR_MGMT_0_GYRO_MODE_OFF = (0x00 << BIT_PWR_MGMT_0_GYRO_MODE_POS),
527 } ICM406XX_PWR_MGMT_0_GYRO_MODE_t;
528
529 int inv_icm406xx_wr_pwr_mgmt0_gyro_mode(struct inv_icm406xx * s,
530 ICM406XX_PWR_MGMT_0_GYRO_MODE_t new_value);
531 int inv_icm406xx_rd_pwr_mgmt0_gyro_mode(struct inv_icm406xx * s,
532 ICM406XX_PWR_MGMT_0_GYRO_MODE_t *value);
533
534 /* ACCEL_MODE */
535 #define BIT_PWR_MGMT_0_ACCEL_MODE_POS 0
536 #define BIT_PWR_MGMT_0_ACCEL_MODE_MASK 0x03
537
538 typedef enum {
539 ICM406XX_PWR_MGMT_0_ACCEL_MODE_LN = 0x03,
540 ICM406XX_PWR_MGMT_0_ACCEL_MODE_LP = 0x02,
541 ICM406XX_PWR_MGMT_0_ACCEL_MODE_OFF = 0x00,
542 } ICM406XX_PWR_MGMT_0_ACCEL_MODE_t;
543
544 int inv_icm406xx_wr_pwr_mgmt0_accel_mode(struct inv_icm406xx * s,
545 ICM406XX_PWR_MGMT_0_ACCEL_MODE_t new_value);
546 int inv_icm406xx_rd_pwr_mgmt0_accel_mode(struct inv_icm406xx * s,
547 ICM406XX_PWR_MGMT_0_ACCEL_MODE_t *value);
548
549 /*
550 * MPUREG_GYRO_CONFIG0
551 * Register Name: GYRO_CONFIG0
552 */
553
554 /* GYRO_FS_SEL*/
555 #define BIT_GYRO_CONFIG0_FS_SEL_POS 5
556 #define BIT_GYRO_CONFIG0_FS_SEL_MASK (7 << BIT_GYRO_CONFIG0_FS_SEL_POS)
557
560 typedef enum {
561 ICM406XX_GYRO_CONFIG0_FS_SEL_16dps = (7 << BIT_GYRO_CONFIG0_FS_SEL_POS),
562 ICM406XX_GYRO_CONFIG0_FS_SEL_31dps = (6 << BIT_GYRO_CONFIG0_FS_SEL_POS),
563 ICM406XX_GYRO_CONFIG0_FS_SEL_62dps = (5 << BIT_GYRO_CONFIG0_FS_SEL_POS),
564 ICM406XX_GYRO_CONFIG0_FS_SEL_125dps = (4 << BIT_GYRO_CONFIG0_FS_SEL_POS),
565 ICM406XX_GYRO_CONFIG0_FS_SEL_250dps = (3 << BIT_GYRO_CONFIG0_FS_SEL_POS),
566 ICM406XX_GYRO_CONFIG0_FS_SEL_500dps = (2 << BIT_GYRO_CONFIG0_FS_SEL_POS),
567 ICM406XX_GYRO_CONFIG0_FS_SEL_1000dps = (1 << BIT_GYRO_CONFIG0_FS_SEL_POS),
568 ICM406XX_GYRO_CONFIG0_FS_SEL_2000dps = (0 << BIT_GYRO_CONFIG0_FS_SEL_POS),
569 } ICM406XX_GYRO_CONFIG0_FS_SEL_t;
570
571 int inv_icm406xx_wr_gyro_config0_fs_sel(struct inv_icm406xx * s,
572 ICM406XX_GYRO_CONFIG0_FS_SEL_t new_value);
573 int inv_icm406xx_rd_gyro_config0_fs_sel(struct inv_icm406xx * s,
574 ICM406XX_GYRO_CONFIG0_FS_SEL_t *value);
575
576 /* GYRO_ODR */
577 #define BIT_GYRO_CONFIG0_ODR_POS 0
578 #define BIT_GYRO_CONFIG0_ODR_MASK 0x0F
579
582 typedef enum {
583 #ifdef ICM40609D
584 ICM406XX_GYRO_CONFIG0_ODR_500_HZ = 0x0F,
585 #endif
586 ICM406XX_GYRO_CONFIG0_ODR_6_25_HZ = 0x0C,
587 ICM406XX_GYRO_CONFIG0_ODR_12_5_HZ = 0x0B,
588 ICM406XX_GYRO_CONFIG0_ODR_25_HZ = 0x0A,
589 ICM406XX_GYRO_CONFIG0_ODR_50_HZ = 0x09,
590 ICM406XX_GYRO_CONFIG0_ODR_100_HZ = 0x08,
591 ICM406XX_GYRO_CONFIG0_ODR_200_HZ = 0x07,
592 ICM406XX_GYRO_CONFIG0_ODR_1_KHZ = 0x06,
593 ICM406XX_GYRO_CONFIG0_ODR_2_KHZ = 0x05,
594 ICM406XX_GYRO_CONFIG0_ODR_4_KHZ = 0x04,
595 ICM406XX_GYRO_CONFIG0_ODR_8_KHZ = 0x03,
596 ICM406XX_GYRO_CONFIG0_ODR_16_KHZ = 0x02,
597 ICM406XX_GYRO_CONFIG0_ODR_32_KHZ = 0x01,
598 #ifndef ICM40609D
599 ICM406XX_GYRO_CONFIG0_ODR_64_KHZ = 0x00,
600 #endif
601 } ICM406XX_GYRO_CONFIG0_ODR_t;
602
603 int inv_icm406xx_wr_gyro_config0_odr(struct inv_icm406xx *s, ICM406XX_GYRO_CONFIG0_ODR_t new_value);
604 int inv_icm406xx_rd_gyro_config0_odr(struct inv_icm406xx *s, ICM406XX_GYRO_CONFIG0_ODR_t *value);
605
606 /*
607 * MPUREG_ACCEL_CONFIG0
608 * Register Name: ACCEL_CONFIG0
609 */
610
611 /* ACCEL_FS_SEL */
612 #define BIT_ACCEL_CONFIG0_FS_SEL_POS 5
613 #define BIT_ACCEL_CONFIG0_FS_SEL_MASK (0x7 << BIT_ACCEL_CONFIG0_FS_SEL_POS)
614
617 #ifdef ICM40609D
618 typedef enum {
619 ICM406XX_ACCEL_CONFIG0_FS_SEL_4g = (0x3 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
620 ICM406XX_ACCEL_CONFIG0_FS_SEL_8g = (0x2 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
621 ICM406XX_ACCEL_CONFIG0_FS_SEL_16g = (0x1 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
622 ICM406XX_ACCEL_CONFIG0_FS_SEL_32g = (0x0 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
623 } ICM406XX_ACCEL_CONFIG0_FS_SEL_t;
624 #else
625 typedef enum {
626 ICM406XX_ACCEL_CONFIG0_FS_SEL_1g = (0x4 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
627 ICM406XX_ACCEL_CONFIG0_FS_SEL_2g = (0x3 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
628 ICM406XX_ACCEL_CONFIG0_FS_SEL_4g = (0x2 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
629 ICM406XX_ACCEL_CONFIG0_FS_SEL_8g = (0x1 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
630 ICM406XX_ACCEL_CONFIG0_FS_SEL_16g = (0x0 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
631 } ICM406XX_ACCEL_CONFIG0_FS_SEL_t;
632 #endif
633
634 int inv_icm406xx_wr_accel_config0_fs_sel(struct inv_icm406xx * s,
635 ICM406XX_ACCEL_CONFIG0_FS_SEL_t new_value);
636 int inv_icm406xx_rd_accel_config0_fs_sel(struct inv_icm406xx * s,
637 ICM406XX_ACCEL_CONFIG0_FS_SEL_t *value);
638
639 /* ACCEL_ODR */
640 #define BIT_ACCEL_CONFIG0_ODR_POS 0
641 #define BIT_ACCEL_CONFIG0_ODR_MASK 0x0F
642
645 #ifdef ICM40609D
646 typedef enum {
647 ICM406XX_ACCEL_CONFIG0_ODR_500_HZ = 0xF,
648 ICM406XX_ACCEL_CONFIG0_ODR_1_5625_HZ = 0xE,
649 ICM406XX_ACCEL_CONFIG0_ODR_3_125_HZ = 0xD,
650 ICM406XX_ACCEL_CONFIG0_ODR_6_25_HZ = 0xC,
651 ICM406XX_ACCEL_CONFIG0_ODR_12_5_HZ = 0xB,
652 ICM406XX_ACCEL_CONFIG0_ODR_25_HZ = 0xA,
653 ICM406XX_ACCEL_CONFIG0_ODR_50_HZ = 0x9,
654 ICM406XX_ACCEL_CONFIG0_ODR_100_HZ = 0x8,
655 ICM406XX_ACCEL_CONFIG0_ODR_200_HZ = 0x7,
656 ICM406XX_ACCEL_CONFIG0_ODR_1_KHZ = 0x6,
657 ICM406XX_ACCEL_CONFIG0_ODR_2_KHZ = 0x5,
658 ICM406XX_ACCEL_CONFIG0_ODR_4_KHZ = 0x4,
659 ICM406XX_ACCEL_CONFIG0_ODR_8_KHZ = 0x3,
660 ICM406XX_ACCEL_CONFIG0_ODR_16_KHZ = 0x2,
661 ICM406XX_ACCEL_CONFIG0_ODR_32_KHZ = 0x1,
662 } ICM406XX_ACCEL_CONFIG0_ODR_t;
663 #else
664 typedef enum {
665 ICM406XX_ACCEL_CONFIG0_ODR_6_25_HZ = 0xC,
666 ICM406XX_ACCEL_CONFIG0_ODR_12_5_HZ = 0xB,
667 ICM406XX_ACCEL_CONFIG0_ODR_25_HZ = 0xA,
668 ICM406XX_ACCEL_CONFIG0_ODR_50_HZ = 0x9,
669 ICM406XX_ACCEL_CONFIG0_ODR_100_HZ = 0x8,
670 ICM406XX_ACCEL_CONFIG0_ODR_200_HZ = 0x7,
671 ICM406XX_ACCEL_CONFIG0_ODR_1_KHZ = 0x6,
672 ICM406XX_ACCEL_CONFIG0_ODR_2_KHZ = 0x5,
673 ICM406XX_ACCEL_CONFIG0_ODR_4_KHZ = 0x4,
674 ICM406XX_ACCEL_CONFIG0_ODR_8_KHZ = 0x3,
675 ICM406XX_ACCEL_CONFIG0_ODR_16_KHZ = 0x2,
676 ICM406XX_ACCEL_CONFIG0_ODR_32_KHZ = 0x1,
677 ICM406XX_ACCEL_CONFIG0_ODR_64_KHZ = 0x0,
678 } ICM406XX_ACCEL_CONFIG0_ODR_t;
679 #endif
680
681 int inv_icm406xx_wr_accel_config0_odr(struct inv_icm406xx * s,
682 ICM406XX_ACCEL_CONFIG0_ODR_t new_value);
683 int inv_icm406xx_rd_accel_config0_odr(struct inv_icm406xx *s, ICM406XX_ACCEL_CONFIG0_ODR_t *value);
684
685 /*
686 * MPUREG_GYRO_CONFIG1
687 * Register Name: GYRO_CONFIG1
688 */
689
690 /* TEMP_FILT_BW */
691 #define BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS 5
692 #define BIT_GYRO_CONFIG1_TEMP_FILT_BW_MASK (0x7 << BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS)
693
694 /* AVG_FILT_RATE */
695 #define BIT_GYRO_CONFIG1_AVG_FILT_RATE_POS 4
696 #define BIT_GYRO_CONFIG1_AVG_FILT_RATE_MASK (0x1 << BIT_GYRO_CONFIG1_AVG_FILT_RATE_POS)
697
698 typedef enum {
699 ICM406XX_GYRO_CONFIG1_AVG_FILT_RATE_8KHz = (0x01 << BIT_GYRO_CONFIG1_AVG_FILT_RATE_POS),
700 ICM406XX_GYRO_CONFIG1_AVG_FILT_RATE_1KHz = (0x00 << BIT_GYRO_CONFIG1_AVG_FILT_RATE_POS),
701 } ICM406XX_GYRO_CONFIG1_AVG_FILT_RATE_t;
702
703 int inv_icm406xx_wr_gyro_config1_avg_filt_rate(struct inv_icm406xx * s,
704 ICM406XX_GYRO_CONFIG1_AVG_FILT_RATE_t new_value);
705
706 /* GYRO_UI_FILT_ORD */
707 #define BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS 2
708 #define BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_MASK (0x3 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS)
709
710 /* GYRO_DEC2_M2_ORD */
711 #define BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_POS 0
712 #define BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_MASK (0x3 << BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_POS)
713
714 /*
715 * MPUREG_ACCEL_GYRO_CONFIG0
716 * Register Name: GYRO_ACCEL_CONFIG0
717 */
718
719 /* ACCEL_FILT */
720 #define BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS 4
721 #define BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_MASK (0xF << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS)
722
723 typedef enum {
724 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_40 = (0x7 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
725 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_20 = (0x6 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
726 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_16 = (0x5 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
727 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_10 = (0x4 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
728 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_8 = (0x3 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
729 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_5 = (0x2 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
730 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_4 = (0x1 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
731 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_2 = (0x0 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
732 } ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t;
733
734 int inv_icm406xx_wr_gyro_accel_config0_accel_filt_bw(
735 struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t new_value);
736 int inv_icm406xx_rd_gyro_accel_config0_accel_filt_bw(
737 struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t *value);
738
739 typedef enum {
740 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_128 = (0x9 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
741 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_64 = (0x8 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
742 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_32 = (0x7 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
743 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_16 = (0x6 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
744 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_8 = (0x5 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
745 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_4 = (0x4 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
746 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_3 = (0x3 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
747 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_2 = (0x2 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
748 ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_1 = (0x1 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
749 } ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t;
750 int inv_icm406xx_wr_gyro_accel_config0_accel_filt_avg(
751 struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t new_value);
752 int inv_icm406xx_rd_gyro_accel_config0_accel_filt_avg(
753 struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t *value);
754
755 /* GYRO_FILT */
756 #define BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_POS 0
757 #define BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_MASK 0x0F
758
759 typedef enum {
760 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_40 = 0x07,
761 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_20 = 0x06,
762 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_16 = 0x05,
763 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_10 = 0x04,
764 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_8 = 0x03,
765 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_5 = 0x02,
766 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_4 = 0x01,
767 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_2 = 0x00,
768 } ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t;
769 int inv_icm406xx_wr_gyro_accel_config0_gyro_filt_bw(
770 struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t new_value);
771 int inv_icm406xx_rd_gyro_accel_config0_gyro_filt_bw(
772 struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t *value);
773
774 typedef enum {
775 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_128 = 0x09,
776 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_64 = 0x08,
777 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_32 = 0x07,
778 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_16 = 0x06,
779 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_8 = 0x05,
780 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_4 = 0x04,
781 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_3 = 0x03,
782 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_2 = 0x02,
783 ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_1 = 0x01,
784 } ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_t;
785
786 int inv_icm406xx_wr_gyro_accel_config0_gyro_filt_avg(
787 struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_t new_value);
788
789 /*
790 * MPUREG_ACCEL_CONFIG1
791 * Register Name: ACCEL_CONFIG1
792 */
793
794 /* ACCEL_UI_FILT_ORD */
795 #define BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS 3
796 #define BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS)
797
798 /* ACCEL_DEC2_M2_ORD */
799 #define BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS 1
800 #define BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS)
801
802 /* AVG_FILT_RATE */
803 #define BIT_ACCEL_CONFIG1_AVG_FILT_RATE_POS 0
804 #define BIT_ACCEL_CONFIG1_AVG_FILT_RATE_MASK 0x1
805
806 typedef enum {
807 ICM406XX_ACCEL_CONFIG1_AVG_FILT_RATE_8KHz = 0x01,
808 ICM406XX_ACCEL_CONFIG1_AVG_FILT_RATE_1KHz = 0x00,
809 } ICM406XX_ACCEL_CONFIG1_AVG_FILT_RATE_t;
810
811 int inv_icm406xx_wr_accel_config1_avg_filt_rate(struct inv_icm406xx * s,
812 ICM406XX_ACCEL_CONFIG1_AVG_FILT_RATE_t new_value);
813 int inv_icm406xx_rd_accel_config1_avg_filt_rate(struct inv_icm406xx * s,
814 ICM406XX_ACCEL_CONFIG1_AVG_FILT_RATE_t *value);
815
816 /*
817 * MPUREG_ACCEL_WOM_X_THR
818 * Register Name: ACCEL_WOM_X_THR
819 */
820 int inv_icm406xx_wr_accel_wom_x_thr(struct inv_icm406xx *s, uint8_t new_value);
821
822 /*
823 * MPUREG_ACCEL_WOM_Y_THR
824 * Register Name: ACCEL_WOM_Y_THR
825 */
826 int inv_icm406xx_wr_accel_wom_y_thr(struct inv_icm406xx *s, uint8_t new_value);
827
828 /*
829 * MPUREG_ACCEL_WOM_Z_THR
830 * Register Name: ACCEL_WOM_Z_THR
831 */
832 int inv_icm406xx_wr_accel_wom_z_thr(struct inv_icm406xx *s, uint8_t new_value);
833
834 /*
835 * MPUREG_SMD_CONFIG
836 * Register Name: SMD_CONFIG
837 */
838
839 /* WOM_INT_MODE */
840 #define BIT_SMD_CONFIG_WOM_INT_MODE_POS 3
841 #define BIT_SMD_CONFIG_WOM_INT_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_INT_MODE_POS)
842
843 typedef enum {
844 ICM406XX_SMD_CONFIG_WOM_INT_MODE_ANDED = (0x01 << BIT_SMD_CONFIG_WOM_INT_MODE_POS),
845 ICM406XX_SMD_CONFIG_WOM_INT_MODE_ORED = (0x00 << BIT_SMD_CONFIG_WOM_INT_MODE_POS),
846 } ICM406XX_SMD_CONFIG_WOM_INT_MODE_t;
847
848 int inv_icm406xx_wr_smd_config_wom_int_mode(struct inv_icm406xx * s,
849 ICM406XX_SMD_CONFIG_WOM_INT_MODE_t new_value);
850 int inv_icm406xx_rd_smd_config_wom_int_mode(struct inv_icm406xx * s,
851 ICM406XX_SMD_CONFIG_WOM_INT_MODE_t *value);
852
853 /* WOM_MODE */
854 #define BIT_SMD_CONFIG_WOM_MODE_POS 2
855 #define BIT_SMD_CONFIG_WOM_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_MODE_POS)
856
857 typedef enum {
858 ICM406XX_SMD_CONFIG_WOM_MODE_CMP_PREV = (0x01 << BIT_SMD_CONFIG_WOM_MODE_POS),
859 ICM406XX_SMD_CONFIG_WOM_MODE_CMP_INIT = (0x00 << BIT_SMD_CONFIG_WOM_MODE_POS),
860 } ICM406XX_SMD_CONFIG_WOM_MODE_t;
861
862 int inv_icm406xx_wr_smd_config_wom_mode(struct inv_icm406xx * s,
863 ICM406XX_SMD_CONFIG_WOM_MODE_t new_value);
864 int inv_icm406xx_rd_smd_config_wom_mode(struct inv_icm406xx * s,
865 ICM406XX_SMD_CONFIG_WOM_MODE_t *value);
866
867 /* SMD_MODE */
868 #define BIT_SMD_CONFIG_SMD_MODE_POS 0
869 #define BIT_SMD_CONFIG_SMD_MODE_MASK 0x3
870
871 typedef enum {
872 ICM406XX_SMD_CONFIG_SMD_MODE_LONG = 0x03,
873 ICM406XX_SMD_CONFIG_SMD_MODE_SHORT = 0x02,
874 ICM406XX_SMD_CONFIG_SMD_MODE_WOM = 0x01,
875 ICM406XX_SMD_CONFIG_SMD_MODE_DISABLED = 0x00,
876 } ICM406XX_SMD_CONFIG_SMD_MODE_t;
877
878 int inv_icm406xx_wr_smd_config_smd_mode(struct inv_icm406xx * s,
879 ICM406XX_SMD_CONFIG_SMD_MODE_t new_value);
880 int inv_icm406xx_rd_smd_config_smd_mode(struct inv_icm406xx * s,
881 ICM406XX_SMD_CONFIG_SMD_MODE_t *value);
882
883 /*
884 * MPUREG_INT_STATUS2
885 * Register Name: INT_STATUS2
886 */
887 #define BIT_INT_STATUS2_SMD_INT 0x08
888 #define BIT_INT_STATUS2_WOM_Z_INT 0x04
889 #define BIT_INT_STATUS2_WOM_Y_INT 0x02
890 #define BIT_INT_STATUS2_WOM_X_INT 0x01
891 int inv_icm406xx_rd_int_status2(struct inv_icm406xx *s, uint8_t *value);
892
893 /*
894 * MPUREG_TMST_CONFIG
895 * Register Name: TMST_CONFIG
896 */
897
898 /* TMST_TO_REGS */
899 #define BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS 4
900 #define BIT_TMST_CONFIG_TMST_TO_REGS_EN_MASK (0x1 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS)
901
902 typedef enum {
903 ICM406XX_TMST_CONFIG_TMST_TO_REGS_EN = (0x1 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS),
904 ICM406XX_TMST_CONFIG_TMST_TO_REGS_DIS = (0x0 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS),
905 } ICM406XX_TMST_CONFIG_TMST_TO_REGS_EN_t;
906
907 int inv_icm406xx_wr_tmst_config_tmst_to_reg(struct inv_icm406xx * s,
908 ICM406XX_TMST_CONFIG_TMST_TO_REGS_EN_t new_value);
909
910 /* TMST_RES */
911 #define BIT_TMST_CONFIG_RESOL_POS 3
912 #define BIT_TMST_CONFIG_RESOL_MASK (0x1 << BIT_TMST_CONFIG_RESOL_POS)
913
914 typedef enum {
915 ICM406XX_TMST_CONFIG_RESOL_16us = (0x01 << BIT_TMST_CONFIG_RESOL_POS),
916 ICM406XX_TMST_CONFIG_RESOL_1us = (0x00 << BIT_TMST_CONFIG_RESOL_POS),
917 } ICM406XX_TMST_CONFIG_RESOL_t;
918
919 int inv_icm406xx_wr_tmst_config_resolution(struct inv_icm406xx * s,
920 ICM406XX_TMST_CONFIG_RESOL_t new_value);
921
922 /* TMST_FSYNC */
923 #define BIT_TMST_CONFIG_TMST_FSYNC_POS 1
924 #define BIT_TMST_CONFIG_TMST_FSYNC_MASK (0x1 << BIT_TMST_CONFIG_TMST_FSYNC_POS)
925
926 typedef enum {
927 ICM406XX_TMST_CONFIG_TMST_FSYNC_EN = (0x01 << BIT_TMST_CONFIG_TMST_FSYNC_POS),
928 ICM406XX_TMST_CONFIG_TMST_FSYNC_DIS = (0x00 << BIT_TMST_CONFIG_TMST_FSYNC_POS),
929 } ICM406XX_TMST_CONFIG_TMST_FSYNC_EN_t;
930
931 int inv_icm406xx_wr_tmst_config_fsync_en(struct inv_icm406xx * s,
932 ICM406XX_TMST_CONFIG_TMST_FSYNC_EN_t new_value);
933 int inv_icm406xx_rd_tmst_config_fsync_en(struct inv_icm406xx * s,
934 ICM406XX_TMST_CONFIG_TMST_FSYNC_EN_t *value);
935
936 /* TMST_EN */
937 #define BIT_TMST_CONFIG_TMST_EN_POS 0
938 #define BIT_TMST_CONFIG_TMST_EN_MASK 0x1
939
940 typedef enum {
941 ICM406XX_TMST_CONFIG_TMST_EN = 0x01,
942 ICM406XX_TMST_CONFIG_TMST_DIS = 0x00,
943 } ICM406XX_TMST_CONFIG_TMST_EN_t;
944
945 int inv_icm406xx_wr_tmst_config_en(struct inv_icm406xx * s,
946 ICM406XX_TMST_CONFIG_TMST_EN_t new_value);
947
948 /*
949 * MPUREG_FIFO_CONFIG1
950 * Register Name: FIFO_CONFIG1
951 */
952
953 /* FIFO_WM_GT_TH */
954 #define BIT_FIFO_CONFIG1_WM_GT_TH_POS 5
955 #define BIT_FIFO_CONFIG1_WM_GT_TH_MASK (0x1 << BIT_FIFO_CONFIG1_WM_GT_TH_POS)
956
957 typedef enum {
958 ICM406XX_FIFO_CONFIG1_WM_GT_TH_EN = (0x1 << BIT_FIFO_CONFIG1_WM_GT_TH_POS),
959 ICM406XX_FIFO_CONFIG1_WM_GT_TH_DIS = (0x0 << BIT_FIFO_CONFIG1_WM_GT_TH_POS),
960 } ICM406XX_FIFO_CONFIG1_WM_GT_t;
961
962 int inv_icm406xx_wr_fifo_config1_wm_gt_th(struct inv_icm406xx * s,
963 ICM406XX_FIFO_CONFIG1_WM_GT_t new_value);
964
965 /* FIFO_HIRES_EN */
966 #define BIT_FIFO_CONFIG1_HIRES_POS 4
967 #define BIT_FIFO_CONFIG1_HIRES_MASK (0x1 << BIT_FIFO_CONFIG1_HIRES_POS)
968
969 typedef enum {
970 ICM406XX_FIFO_CONFIG1_HIRES_EN = (0x1 << BIT_FIFO_CONFIG1_HIRES_POS),
971 ICM406XX_FIFO_CONFIG1_HIRES_DIS = (0x0 << BIT_FIFO_CONFIG1_HIRES_POS),
972 } ICM406XX_FIFO_CONFIG1_HIRES_t;
973
974 int inv_icm406xx_wr_fifo_config1_hires(struct inv_icm406xx * s,
975 ICM406XX_FIFO_CONFIG1_HIRES_t new_value);
976
977 /* FIFO_TMST_FSYNC_EN */
978 #define BIT_FIFO_CONFIG1_TMST_FSYNC_POS 3
979 #define BIT_FIFO_CONFIG1_TMST_FSYNC_MASK (0x1 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS)
980
981 typedef enum {
982 ICM406XX_FIFO_CONFIG1_TMST_FSYNC_EN = (0x1 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS),
983 ICM406XX_FIFO_CONFIG1_TMST_FSYNC_DIS = (0x0 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS),
984 } ICM406XX_FIFO_CONFIG1_TMST_FSYNC_t;
985
986 int inv_icm406xx_wr_fifo_config1_tmst_fsync(struct inv_icm406xx * s,
987 ICM406XX_FIFO_CONFIG1_TMST_FSYNC_t new_value);
988
989 /* FIFO_TEMP_EN */
990 #define BIT_FIFO_CONFIG1_TEMP_POS 2
991 #define BIT_FIFO_CONFIG1_TEMP_MASK (0x1 << BIT_FIFO_CONFIG1_TEMP_POS)
992
993 typedef enum {
994 ICM406XX_FIFO_CONFIG1_TEMP_EN = (0x1 << BIT_FIFO_CONFIG1_TEMP_POS),
995 ICM406XX_FIFO_CONFIG1_TEMP_DIS = (0x0 << BIT_FIFO_CONFIG1_TEMP_POS),
996 } ICM406XX_FIFO_CONFIG1_TEMP_t;
997
998 int inv_icm406xx_wr_fifo_config1_temp_en(struct inv_icm406xx * s,
999 ICM406XX_FIFO_CONFIG1_TEMP_t new_value);
1000
1001 /* FIFO_GYRO_EN */
1002 #define BIT_FIFO_CONFIG1_GYRO_POS 1
1003 #define BIT_FIFO_CONFIG1_GYRO_MASK (0x1 << BIT_FIFO_CONFIG1_GYRO_POS)
1004
1005 typedef enum {
1006 ICM406XX_FIFO_CONFIG1_GYRO_EN = (0x1 << BIT_FIFO_CONFIG1_GYRO_POS),
1007 ICM406XX_FIFO_CONFIG1_GYRO_DIS = (0x0 << BIT_FIFO_CONFIG1_GYRO_POS),
1008 } ICM406XX_FIFO_CONFIG1_GYRO_t;
1009
1010 int inv_icm406xx_wr_fifo_config1_gyro_en(struct inv_icm406xx * s,
1011 ICM406XX_FIFO_CONFIG1_GYRO_t new_value);
1012
1013 /* FIFO_ACCEL_EN*/
1014 #define BIT_FIFO_CONFIG1_ACCEL_POS 0
1015 #define BIT_FIFO_CONFIG1_ACCEL_MASK 0x1
1016
1017 typedef enum {
1018 ICM406XX_FIFO_CONFIG1_ACCEL_EN = 0x01,
1019 ICM406XX_FIFO_CONFIG1_ACCEL_DIS = 0x00,
1020 } ICM406XX_FIFO_CONFIG1_ACCEL_t;
1021
1022 int inv_icm406xx_wr_fifo_config1_accel_en(struct inv_icm406xx * s,
1023 ICM406XX_FIFO_CONFIG1_ACCEL_t new_value);
1024
1025 /*
1026 * MPUREG_FIFO_CONFIG2
1027 * Register Name: FIFO_CONFIG2
1028 */
1029 int inv_icm406xx_wr_fifo_config2(struct inv_icm406xx *s, uint8_t new_value);
1030
1031 /*
1032 * MPUREG_FSYNC_CONFIG
1033 * Register Name: FSYNC_CONFIG
1034 */
1035
1036 /* FSYNC_UI_SEL */
1037 #define BIT_FSYNC_CONFIG_UI_SEL_POS 4
1038 #define BIT_FSYNC_CONFIG_UI_SEL_MASK (0x7 << BIT_FSYNC_CONFIG_UI_SEL_POS)
1039
1040 typedef enum {
1041 ICM406XX_FSYNC_CONFIG_UI_SEL_NO = (0x0 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1042 ICM406XX_FSYNC_CONFIG_UI_SEL_TEMP = (0x1 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1043 ICM406XX_FSYNC_CONFIG_UI_SEL_GYRO_X = (0x2 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1044 ICM406XX_FSYNC_CONFIG_UI_SEL_GYRO_Y = (0x3 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1045 ICM406XX_FSYNC_CONFIG_UI_SEL_GYRO_Z = (0x4 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1046 ICM406XX_FSYNC_CONFIG_UI_SEL_ACCEL_X = (0x5 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1047 ICM406XX_FSYNC_CONFIG_UI_SEL_ACCEL_Y = (0x6 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1048 ICM406XX_FSYNC_CONFIG_UI_SEL_ACCEL_Z = (0x7 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1049 } ICM406XX_FSYNC_CONFIG_UI_SEL_t;
1050
1051 int inv_icm406xx_fsync_config_ui_sel(struct inv_icm406xx * s,
1052 ICM406XX_FSYNC_CONFIG_UI_SEL_t new_value);
1053
1054 /*
1055 * MPUREG_INT_CONFIG1
1056 * Register Name: INT_CONFIG1
1057 */
1058
1059 /* ASY_RESET_DISABLE */
1060 #define BIT_INT_CONFIG1_ASY_RST_POS 4
1061 #define BIT_INT_CONFIG1_ASY_RST_MASK (0x1 << BIT_INT_CONFIG1_ASY_RST_POS)
1062
1063 typedef enum {
1064 ICM406XX_INT_CONFIG1_ASY_RST_DISABLED = (0x1 << BIT_INT_CONFIG1_ASY_RST_POS),
1065 ICM406XX_INT_CONFIG1_ASY_RST_ENABLED = (0x0 << BIT_INT_CONFIG1_ASY_RST_POS),
1066 } ICM406XX_INT_CONFIG1_ASY_RST_t;
1067
1068 int inv_icm406xx_wr_int_config1_asy_rst_dis(struct inv_icm406xx * s,
1069 ICM406XX_INT_CONFIG1_ASY_RST_t new_value);
1070
1071 /*
1072 * MPUREG_INT_SOURCE0
1073 * Register Name: INT_SOURCE0
1074 */
1075 #define BIT_INT_SOURCE0_UI_FSYNC_INT1_EN 0x40
1076 #define BIT_INT_SOURCE0_PLL_RDY_INT1_EN 0x20
1077 #define BIT_INT_SOURCE0_RESET_DONE_INT1_EN 0x10
1078 #define BIT_INT_SOURCE0_UI_DRDY_INT1_EN 0x08
1079 #define BIT_INT_SOURCE0_FIFO_THS_INT1_EN 0x04
1080 #define BIT_INT_SOURCE0_FIFO_FULL_INT1_EN 0x02
1081 #define BIT_INT_SOURCE0_UI_AGC_RDY_INT1_EN 0x01
1082 int inv_icm406xx_wr_int_source0(struct inv_icm406xx *s, uint8_t new_value);
1083 int inv_icm406xx_rd_int_source0(struct inv_icm406xx *s, uint8_t *value);
1084
1085 /*
1086 * MPUREG_INT_SOURCE1
1087 * Register Name: INT_SOURCE1
1088 */
1089 #define BIT_INT_SOURCE1_SMD_INT1_EN 0x08
1090 #define BIT_INT_SOURCE1_WOM_Z_INT1_EN 0x04
1091 #define BIT_INT_SOURCE1_WOM_Y_INT1_EN 0x02
1092 #define BIT_INT_SOURCE1_WOM_X_INT1_EN 0x01
1093 int inv_icm406xx_wr_int_source1(struct inv_icm406xx *s, uint8_t new_value);
1094 int inv_icm406xx_rd_int_source1(struct inv_icm406xx *s, uint8_t *value);
1095
1096 /*
1097 * MPUREG_INT_SOURCE2
1098 * Register Name: INT_SOURCE2
1099 */
1100 #define BIT_INT_SOURCE2_OIS2_AGC_RDY_INT1_EN 0x20
1101 #define BIT_INT_SOURCE2_OIS2_FSYNC_INT1_EN 0x10
1102 #define BIT_INT_SOURCE2_OIS2_DRDY_INT1_EN 0x08
1103 #define BIT_INT_SOURCE2_OIS1_AGC_RDY_INT1_EN 0x04
1104 #define BIT_INT_SOURCE2_OIS1_FSYNC_INT1_EN 0x02
1105 #define BIT_INT_SOURCE2_OIS1_DRDY_INT1_EN 0x01
1106
1107 /*
1108 * MPUREG_INT_SOURCE3
1109 * Register Name: INT_SOURCE3
1110 */
1111 #define BIT_INT_SOURCE3_UI_FSYNC_INT2_EN 0x40
1112 #define BIT_INT_SOURCE3_PLL_RDY_INT2_EN 0x20
1113 #define BIT_INT_SOURCE3_RESET_DONE_INT2_EN 0x10
1114 #define BIT_INT_SOURCE3_UI_DRDY_INT2_EN 0x08
1115 #define BIT_INT_SOURCE3_FIFO_THS_INT2_EN 0x04
1116 #define BIT_INT_SOURCE3_FIFO_FULL_INT2_EN 0x02
1117 #define BIT_INT_SOURCE3_UI_AGC_RDY_INT2_EN 0x01
1118
1119 /*
1120 * MPUREG_INT_SOURCE4
1121 * Register Name: INT_SOURCE4
1122 */
1123 #define BIT_INT_SOURCE4_SMD_INT2_EN 0x08
1124 #define BIT_INT_SOURCE4_WOM_Z_INT2_EN 0x04
1125 #define BIT_INT_SOURCE4_WOM_Y_INT2_EN 0x02
1126 #define BIT_INT_SOURCE4_WOM_X_INT2_EN 0x01
1127
1128 /*
1129 * MPUREG_INT_SOURCE5
1130 * Register Name: INT_SOURCE5
1131 */
1132 #define BIT_INT_SOURCE5_OIS2_AGC_RDY_INT2_EN 0x20
1133 #define BIT_INT_SOURCE5_OIS2_FSYNC_INT2_EN 0x10
1134 #define BIT_INT_SOURCE5_OIS2_DRDY_INT2_EN 0x08
1135 #define BIT_INT_SOURCE5_OIS1_AGC_RDY_INT2_EN 0x04
1136 #define BIT_INT_SOURCE5_OIS1_FSYNC_INT2_EN 0x02
1137 #define BIT_INT_SOURCE5_OIS1_DRDY_INT2_EN 0x01
1138
1139 /*
1140 * MPUREG_SELF_TEST_CONFIG
1141 * Register Name: SELF_TEST_CONFIG
1142 */
1143 #define BIT_ST_REGULATOR_EN 0x40
1144 #define BIT_ACCEL_Z_ST_EN 0x20
1145 #define BIT_ACCEL_Y_ST_EN 0x10
1146 #define BIT_ACCEL_X_ST_EN 0x08
1147 #define BIT_GYRO_Z_ST_EN 0x04
1148 #define BIT_GYRO_Y_ST_EN 0x02
1149 #define BIT_GYRO_X_ST_EN 0x01
1150
1151 /*
1152 * MPUREG_WHO_AM_I
1153 * Register Name: WHO_AM_I
1154 */
1155 int inv_icm406xx_rd_who_am_i(struct inv_icm406xx *s, uint8_t *value);
1156
1157 /*
1158 * MPUREG_REG_BANK_SEL
1159 * Register Name: REG_BANK_SEL
1160 */
1161 int inv_icm406xx_wr_reg_bank_sel(struct inv_icm406xx *s, uint8_t new_value);
1162
1163 /* ----------------------------------------------------------------------------
1164 * Register bank 1
1165 * ---------------------------------------------------------------------------- */
1166
1167 /*
1168 * MPUREG_TMST_VAL0_B1
1169 * MPUREG_TMST_VAL1_B1
1170 * MPUREG_TMST_VAL2_B1
1171 *
1172 * Register Name: TMST_VAL0_B1
1173 * Register Name: TMST_VAL1_B1
1174 * Register Name: TMST_VAL2_B1
1175 */
1176 int inv_icm406xx_rd_tmst_val(struct inv_icm406xx *s, uint8_t value[3]);
1177
1178 /*
1179 * MPUREG_INTF_CONFIG4_B1
1180 * Register Name: INTF_CONFIG4_B1
1181 */
1182
1183 /* SPI_AUX1_4WIRE */
1184 #define BIT_INTF_CONFIG4_AUX_SPI_POS 2
1185 #define BIT_INTF_CONFIG4_AUX_SPI_MASK (0x1 << BIT_INTF_CONFIG4_AUX_SPI_POS)
1186
1187 typedef enum {
1188 ICM406XX_INTF_CONFIG4_AUX_SPI4W = (0x1 << BIT_INTF_CONFIG4_AUX_SPI_POS),
1189 ICM406XX_INTF_CONFIG4_AUX_SPI3W = (0x0 << BIT_INTF_CONFIG4_AUX_SPI_POS),
1190 } ICM406XX_INTF_CONFIG4_AUX_SPI_t;
1191
1192 int inv_icm406xx_wr_intf_config4_aux_spi(struct inv_icm406xx * s,
1193 ICM406XX_INTF_CONFIG4_AUX_SPI_t new_value);
1194 int inv_icm406xx_rd_intf_config4_aux_spi(struct inv_icm406xx * s,
1195 ICM406XX_INTF_CONFIG4_AUX_SPI_t *value);
1196
1197 /* SPI_AP_4WIRE */
1198 #define BIT_INTF_CONFIG4_AP_SPI_POS 1
1199 #define BIT_INTF_CONFIG4_AP_SPI_MASK (0x1 << BIT_INTF_CONFIG4_AP_SPI_POS)
1200
1201 typedef enum {
1202 ICM406XX_INTF_CONFIG4_AP_SPI4W = (0x1 << BIT_INTF_CONFIG4_AP_SPI_POS),
1203 ICM406XX_INTF_CONFIG4_AP_SPI3W = (0x0 << BIT_INTF_CONFIG4_AP_SPI_POS),
1204 } ICM406XX_INTF_CONFIG4_AP_SPI_t;
1205
1206 int inv_icm406xx_wr_intf_config4_ap_spi(struct inv_icm406xx * s,
1207 ICM406XX_INTF_CONFIG4_AP_SPI_t new_value);
1208 int inv_icm406xx_rd_intf_config4_ap_spi(struct inv_icm406xx * s,
1209 ICM406XX_INTF_CONFIG4_AP_SPI_t *value);
1210
1211 /* ----------------------------------------------------------------------------
1212 * Register bank 2
1213 * ---------------------------------------------------------------------------- */
1214
1215 /*
1216 * MPUREG_AUX1_CONFIG1_B2
1217 * Register Name: AUX1_CONFIG1
1218 */
1219
1220 /* AUX1_DEC */
1221 #define BIT_OIS1_CONFIG1_DEC_POS 2
1222 #define BIT_OIS1_CONFIG1_DEC_MASK (0x7 << BIT_OIS1_CONFIG1_DEC_POS)
1223
1224 typedef enum {
1225 ICM406XX_OIS1_CONFIG1_DEC_1 = (0x0 << BIT_OIS1_CONFIG1_DEC_POS),
1226 ICM406XX_OIS1_CONFIG1_DEC_2 = (0x1 << BIT_OIS1_CONFIG1_DEC_POS),
1227 ICM406XX_OIS1_CONFIG1_DEC_4 = (0x2 << BIT_OIS1_CONFIG1_DEC_POS),
1228 ICM406XX_OIS1_CONFIG1_DEC_8 = (0x3 << BIT_OIS1_CONFIG1_DEC_POS),
1229 ICM406XX_OIS1_CONFIG1_DEC_16 = (0x4 << BIT_OIS1_CONFIG1_DEC_POS),
1230 ICM406XX_OIS1_CONFIG1_DEC_32 = (0x5 << BIT_OIS1_CONFIG1_DEC_POS),
1231 } ICM406XX_OIS1_CONFIG1_DEC_t;
1232
1233 int inv_icm406xx_wr_ois1_config1_dec(struct inv_icm406xx *s, ICM406XX_OIS1_CONFIG1_DEC_t new_value);
1234
1235 /* GYRO_AUX1_EN */
1236 #define BIT_OIS1_CONFIG1_GYRO_EN_POS 1
1237 #define BIT_OIS1_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS1_CONFIG1_GYRO_EN_POS)
1238
1239 typedef enum {
1240 ICM406XX_OIS1_CONFIG1_GYRO_EN = (0x1 << BIT_OIS1_CONFIG1_GYRO_EN_POS),
1241 ICM406XX_OIS1_CONFIG1_GYRO_DIS = (0x0 << BIT_OIS1_CONFIG1_GYRO_EN_POS),
1242 } ICM406XX_OIS1_CONFIG1_GYRO_EN_t;
1243
1244 int inv_icm406xx_wr_ois1_config1_gyro_en(struct inv_icm406xx * s,
1245 ICM406XX_OIS1_CONFIG1_GYRO_EN_t new_value);
1246
1247 /*
1248 * MPUREG_AUX1_CONFIG2_B2
1249 * Register Name: AUX1_CONFIG2
1250 */
1251
1252 /* GYRO_AUX1_FS_SEL */
1253 #define BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS 3
1254 #define BIT_OIS1_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS)
1255
1256 typedef enum {
1257 ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_16dps = (0x7 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1258 ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_31dps = (0x6 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1259 ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_62dps = (0x5 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1260 ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_125dps = (0x4 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1261 ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_250dps = (0x3 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1262 ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_500dps = (0x2 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1263 ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_1000dps = (0x1 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1264 ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_2000dps = (0x0 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1265 } ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_t;
1266
1267 int inv_icm406xx_wr_ois1_config2_gyro_fs_sel(struct inv_icm406xx * s,
1268 ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_t new_value);
1269 int inv_icm406xx_rd_ois1_config2_gyro_fs_sel(struct inv_icm406xx * s,
1270 ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_t *value);
1271
1272 /*
1273 * MPUREG_GYRO_DATA_X0_AUX1_B2
1274 * MPUREG_GYRO_DATA_Y0_AUX1_B2
1275 * MPUREG_GYRO_DATA_Z0_AUX1_B2
1276 * Register Name: GYRO_DATA_X0_AUX1
1277 * Register Name: GYRO_DATA_Y0_AUX1
1278 * Register Name: GYRO_DATA_Z0_AUX1
1279 */
1280 int inv_icm406xx_rd_gyro_data_ois1(struct inv_icm406xx *s, uint8_t value[GYRO_DATA_SIZE]);
1281
1282 /*
1283 * MPUREG_INT_STATUS_AUX1_B2
1284 * Register Name: INT_STATUS_AUX1
1285 */
1286 #define BIT_INT_STATUS_AUX1_FSYNC 0x04
1287 #define BIT_INT_STATUS_AUX1_DRDY 0x02
1288 #define BIT_INT_STATUS_AUX1_AGC_RDY 0x01
1289 int inv_icm406xx_rd_int_status_aux1(struct inv_icm406xx *s, uint8_t *value);
1290
1291 /*
1292 * MPUREG_AUX2_CONFIG1_B2
1293 * Register Name: AUX2_CONFIG1
1294 */
1295
1296 /* AUX2_DEC */
1297 #define BIT_OIS2_CONFIG1_DEC_POS 2
1298 #define BIT_OIS2_CONFIG1_DEC_MASK (0x7 << BIT_OIS2_CONFIG1_DEC_POS)
1299
1300 typedef enum {
1301 ICM406XX_OIS2_CONFIG1_DEC_1 = (0x0 << BIT_OIS2_CONFIG1_DEC_POS),
1302 ICM406XX_OIS2_CONFIG1_DEC_2 = (0x1 << BIT_OIS2_CONFIG1_DEC_POS),
1303 ICM406XX_OIS2_CONFIG1_DEC_4 = (0x2 << BIT_OIS2_CONFIG1_DEC_POS),
1304 ICM406XX_OIS2_CONFIG1_DEC_8 = (0x3 << BIT_OIS2_CONFIG1_DEC_POS),
1305 ICM406XX_OIS2_CONFIG1_DEC_16 = (0x4 << BIT_OIS2_CONFIG1_DEC_POS),
1306 ICM406XX_OIS2_CONFIG1_DEC_32 = (0x5 << BIT_OIS2_CONFIG1_DEC_POS),
1307 } ICM406XX_OIS2_CONFIG1_DEC_t;
1308
1309 int inv_icm406xx_wr_ois2_config1_dec(struct inv_icm406xx *s, ICM406XX_OIS2_CONFIG1_DEC_t new_value);
1310
1311 /* GYRO_AUX2_EN */
1312 #define BIT_OIS2_CONFIG1_GYRO_EN_POS 1
1313 #define BIT_OIS2_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS2_CONFIG1_GYRO_EN_POS)
1314
1315 typedef enum {
1316 ICM406XX_OIS2_CONFIG1_GYRO_EN = (0x1 << BIT_OIS2_CONFIG1_GYRO_EN_POS),
1317 ICM406XX_OIS2_CONFIG1_GYRO_DIS = (0x0 << BIT_OIS2_CONFIG1_GYRO_EN_POS),
1318 } ICM406XX_OIS2_CONFIG1_GYRO_EN_t;
1319
1320 int inv_icm406xx_wr_ois2_config1_gyro_en(struct inv_icm406xx * s,
1321 ICM406XX_OIS2_CONFIG1_GYRO_EN_t new_value);
1322
1323 /*
1324 * MPUREG_AUX2_CONFIG2_B2
1325 * Register Name: AUX2_CONFIG2
1326 */
1327
1328 /* GYRO_AUX2_FS_SEL */
1329 #define BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS 3
1330 #define BIT_OIS2_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS)
1331
1332 typedef enum {
1333 ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_16dps = (0x7 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1334 ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_31dps = (0x6 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1335 ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_62dps = (0x5 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1336 ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_125dps = (0x4 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1337 ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_250dps = (0x3 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1338 ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_500dps = (0x2 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1339 ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_1000dps = (0x1 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1340 ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_2000dps = (0x0 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1341 } ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_t;
1342
1343 int inv_icm406xx_wr_ois2_config2_gyro_fs_sel(struct inv_icm406xx * s,
1344 ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_t new_value);
1345 int inv_icm406xx_rd_ois2_config2_gyro_fs_sel(struct inv_icm406xx * s,
1346 ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_t *value);
1347
1348 /*
1349 * MPUREG_GYRO_DATA_X0_AUX2_B2
1350 * MPUREG_GYRO_DATA_Y0_AUX2_B2
1351 * MPUREG_GYRO_DATA_Z0_AUX2_B2
1352 * Register Name: GYRO_DATA_X0_AUX2
1353 * Register Name: GYRO_DATA_Y0_AUX2
1354 * Register Name: GYRO_DATA_Z0_AUX2
1355 */
1356 int inv_icm406xx_rd_gyro_data_ois2(struct inv_icm406xx *s, uint8_t value[GYRO_DATA_SIZE]);
1357
1358 #ifdef __cplusplus
1359 }
1360 #endif
1361
1362 #endif /* #ifndef _INV_ICM406XX_DEFS_H_ */
ICM406XX_GYRO_CONFIG0_ODR_t
ICM406XX_GYRO_CONFIG0_ODR_t
Gyroscope ODR selection.
Definition: Icm406xxDefs.h:582
ICM406XX_GYRO_CONFIG0_ODR_200_HZ
@ ICM406XX_GYRO_CONFIG0_ODR_200_HZ
200 Hz (5 ms)
Definition: Icm406xxDefs.h:591
ICM406XX_GYRO_CONFIG0_ODR_16_KHZ
@ ICM406XX_GYRO_CONFIG0_ODR_16_KHZ
16 KHz (62.5 us)
Definition: Icm406xxDefs.h:596
ICM406XX_GYRO_CONFIG0_ODR_32_KHZ
@ ICM406XX_GYRO_CONFIG0_ODR_32_KHZ
32 KHz (31.25 us)
Definition: Icm406xxDefs.h:597
ICM406XX_GYRO_CONFIG0_ODR_4_KHZ
@ ICM406XX_GYRO_CONFIG0_ODR_4_KHZ
4 KHz (250 us)
Definition: Icm406xxDefs.h:594
ICM406XX_GYRO_CONFIG0_ODR_2_KHZ
@ ICM406XX_GYRO_CONFIG0_ODR_2_KHZ
2 KHz (500 us)
Definition: Icm406xxDefs.h:593
ICM406XX_GYRO_CONFIG0_ODR_100_HZ
@ ICM406XX_GYRO_CONFIG0_ODR_100_HZ
100 Hz (10 ms)
Definition: Icm406xxDefs.h:590
ICM406XX_GYRO_CONFIG0_ODR_64_KHZ
@ ICM406XX_GYRO_CONFIG0_ODR_64_KHZ
64 KHz (15.625 us)
Definition: Icm406xxDefs.h:599
ICM406XX_GYRO_CONFIG0_ODR_1_KHZ
@ ICM406XX_GYRO_CONFIG0_ODR_1_KHZ
1 KHz (1 ms)
Definition: Icm406xxDefs.h:592
ICM406XX_GYRO_CONFIG0_ODR_12_5_HZ
@ ICM406XX_GYRO_CONFIG0_ODR_12_5_HZ
12.5 Hz (80 ms)
Definition: Icm406xxDefs.h:587
ICM406XX_GYRO_CONFIG0_ODR_6_25_HZ
@ ICM406XX_GYRO_CONFIG0_ODR_6_25_HZ
6.25 Hz (160 ms)
Definition: Icm406xxDefs.h:586
ICM406XX_GYRO_CONFIG0_ODR_50_HZ
@ ICM406XX_GYRO_CONFIG0_ODR_50_HZ
50 Hz (20 ms)
Definition: Icm406xxDefs.h:589
ICM406XX_GYRO_CONFIG0_ODR_8_KHZ
@ ICM406XX_GYRO_CONFIG0_ODR_8_KHZ
8 KHz (125 us)
Definition: Icm406xxDefs.h:595
ICM406XX_GYRO_CONFIG0_ODR_25_HZ
@ ICM406XX_GYRO_CONFIG0_ODR_25_HZ
25 Hz (40 ms)
Definition: Icm406xxDefs.h:588
ICM406XX_ACCEL_CONFIG0_FS_SEL_t
ICM406XX_ACCEL_CONFIG0_FS_SEL_t
Accelerometer FSR selection.
Definition: Icm406xxDefs.h:625
ICM406XX_ACCEL_CONFIG0_FS_SEL_8g
@ ICM406XX_ACCEL_CONFIG0_FS_SEL_8g
8g
Definition: Icm406xxDefs.h:629
ICM406XX_ACCEL_CONFIG0_FS_SEL_2g
@ ICM406XX_ACCEL_CONFIG0_FS_SEL_2g
2g
Definition: Icm406xxDefs.h:627
ICM406XX_ACCEL_CONFIG0_FS_SEL_4g
@ ICM406XX_ACCEL_CONFIG0_FS_SEL_4g
4g
Definition: Icm406xxDefs.h:628
ICM406XX_ACCEL_CONFIG0_FS_SEL_16g
@ ICM406XX_ACCEL_CONFIG0_FS_SEL_16g
16g
Definition: Icm406xxDefs.h:630
ICM406XX_ACCEL_CONFIG0_FS_SEL_1g
@ ICM406XX_ACCEL_CONFIG0_FS_SEL_1g
1g
Definition: Icm406xxDefs.h:626
ICM406XX_ACCEL_CONFIG0_ODR_t
ICM406XX_ACCEL_CONFIG0_ODR_t
Accelerometer ODR selection.
Definition: Icm406xxDefs.h:664
ICM406XX_ACCEL_CONFIG0_ODR_200_HZ
@ ICM406XX_ACCEL_CONFIG0_ODR_200_HZ
200 Hz (5 ms)
Definition: Icm406xxDefs.h:670
ICM406XX_ACCEL_CONFIG0_ODR_16_KHZ
@ ICM406XX_ACCEL_CONFIG0_ODR_16_KHZ
16 KHz (62.5 us)
Definition: Icm406xxDefs.h:675
ICM406XX_ACCEL_CONFIG0_ODR_64_KHZ
@ ICM406XX_ACCEL_CONFIG0_ODR_64_KHZ
64 KHz (15.625 us)
Definition: Icm406xxDefs.h:677
ICM406XX_ACCEL_CONFIG0_ODR_2_KHZ
@ ICM406XX_ACCEL_CONFIG0_ODR_2_KHZ
2 KHz (500 us)
Definition: Icm406xxDefs.h:672
ICM406XX_ACCEL_CONFIG0_ODR_4_KHZ
@ ICM406XX_ACCEL_CONFIG0_ODR_4_KHZ
4 KHz (250 us)
Definition: Icm406xxDefs.h:673
ICM406XX_ACCEL_CONFIG0_ODR_32_KHZ
@ ICM406XX_ACCEL_CONFIG0_ODR_32_KHZ
32 KHz (31.25 us)
Definition: Icm406xxDefs.h:676
ICM406XX_ACCEL_CONFIG0_ODR_50_HZ
@ ICM406XX_ACCEL_CONFIG0_ODR_50_HZ
50 Hz (20 ms)
Definition: Icm406xxDefs.h:668
ICM406XX_ACCEL_CONFIG0_ODR_25_HZ
@ ICM406XX_ACCEL_CONFIG0_ODR_25_HZ
25 Hz (40 ms)
Definition: Icm406xxDefs.h:667
ICM406XX_ACCEL_CONFIG0_ODR_100_HZ
@ ICM406XX_ACCEL_CONFIG0_ODR_100_HZ
100 Hz (10 ms)
Definition: Icm406xxDefs.h:669
ICM406XX_ACCEL_CONFIG0_ODR_12_5_HZ
@ ICM406XX_ACCEL_CONFIG0_ODR_12_5_HZ
12.5 Hz (80 ms)
Definition: Icm406xxDefs.h:666
ICM406XX_ACCEL_CONFIG0_ODR_1_KHZ
@ ICM406XX_ACCEL_CONFIG0_ODR_1_KHZ
1 KHz (1 ms)
Definition: Icm406xxDefs.h:671
ICM406XX_ACCEL_CONFIG0_ODR_8_KHZ
@ ICM406XX_ACCEL_CONFIG0_ODR_8_KHZ
8 KHz (125 us)
Definition: Icm406xxDefs.h:674
ICM406XX_ACCEL_CONFIG0_ODR_6_25_HZ
@ ICM406XX_ACCEL_CONFIG0_ODR_6_25_HZ
6.25 Hz (160 ms)
Definition: Icm406xxDefs.h:665
ICM406XX_GYRO_CONFIG0_FS_SEL_t
ICM406XX_GYRO_CONFIG0_FS_SEL_t
Gyroscope FSR selection.
Definition: Icm406xxDefs.h:560
ICM406XX_GYRO_CONFIG0_FS_SEL_500dps
@ ICM406XX_GYRO_CONFIG0_FS_SEL_500dps
500dps
Definition: Icm406xxDefs.h:566
ICM406XX_GYRO_CONFIG0_FS_SEL_250dps
@ ICM406XX_GYRO_CONFIG0_FS_SEL_250dps
250dps
Definition: Icm406xxDefs.h:565
ICM406XX_GYRO_CONFIG0_FS_SEL_31dps
@ ICM406XX_GYRO_CONFIG0_FS_SEL_31dps
31dps
Definition: Icm406xxDefs.h:562
ICM406XX_GYRO_CONFIG0_FS_SEL_16dps
@ ICM406XX_GYRO_CONFIG0_FS_SEL_16dps
16dps
Definition: Icm406xxDefs.h:561
ICM406XX_GYRO_CONFIG0_FS_SEL_62dps
@ ICM406XX_GYRO_CONFIG0_FS_SEL_62dps
62dps
Definition: Icm406xxDefs.h:563
ICM406XX_GYRO_CONFIG0_FS_SEL_125dps
@ ICM406XX_GYRO_CONFIG0_FS_SEL_125dps
125dps
Definition: Icm406xxDefs.h:564
ICM406XX_GYRO_CONFIG0_FS_SEL_2000dps
@ ICM406XX_GYRO_CONFIG0_FS_SEL_2000dps
2000dps
Definition: Icm406xxDefs.h:568
ICM406XX_GYRO_CONFIG0_FS_SEL_1000dps
@ ICM406XX_GYRO_CONFIG0_FS_SEL_1000dps
1000dps
Definition: Icm406xxDefs.h:567
inv_icm406xx_fsync_config_ui_sel
int inv_icm406xx_fsync_config_ui_sel(struct inv_icm406xx *s, ICM406XX_FSYNC_CONFIG_UI_SEL_t new_value)
Set FSYNC_CONFIG register FSYNC_UI_SEL bit.
Definition: Icm406xxDriver.c:1756
inv_icm406xx_wr_fifo_config1_accel_en
int inv_icm406xx_wr_fifo_config1_accel_en(struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG1_ACCEL_t new_value)
Set FIFO_CONFIG1 register FIFO_ACCEL_EN bit.
Definition: Icm406xxDriver.c:1714
inv_icm406xx_rd_fifo_config_mode
int inv_icm406xx_rd_fifo_config_mode(struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG_MODE_t *value)
Read FIFO_CONFIG register FIFO_MODE bit.
Definition: Icm406xxDriver.c:174
inv_icm406xx_wr_accel_config0_odr
int inv_icm406xx_wr_accel_config0_odr(struct inv_icm406xx *s, ICM406XX_ACCEL_CONFIG0_ODR_t new_value)
Set ACCEL_CONFIG0 register ACCEL_ODR bits.
Definition: Icm406xxDriver.c:845
inv_icm406xx_rd_pwr_mgmt0_accel_mode
int inv_icm406xx_rd_pwr_mgmt0_accel_mode(struct inv_icm406xx *s, ICM406XX_PWR_MGMT_0_ACCEL_MODE_t *value)
Read PWR_MGMT_0 register ACCEL_MODE bit.
Definition: Icm406xxDriver.c:624
inv_icm406xx_wr_gyro_config0_odr
int inv_icm406xx_wr_gyro_config0_odr(struct inv_icm406xx *s, ICM406XX_GYRO_CONFIG0_ODR_t new_value)
Set GYRO_CONFIG0 register GYRO_ODR bits.
Definition: Icm406xxDriver.c:719
inv_icm406xx_wr_smd_config_wom_mode
int inv_icm406xx_wr_smd_config_wom_mode(struct inv_icm406xx *s, ICM406XX_SMD_CONFIG_WOM_MODE_t new_value)
Set MPUREG_SMD_CONFIG register WOM_MODE bit.
Definition: Icm406xxDriver.c:1337
inv_icm406xx_wr_smd_config_smd_mode
int inv_icm406xx_wr_smd_config_smd_mode(struct inv_icm406xx *s, ICM406XX_SMD_CONFIG_SMD_MODE_t new_value)
Set MPUREG_SMD_CONFIG register SMD_MODE bit.
Definition: Icm406xxDriver.c:1388
inv_icm406xx_wr_fifo_config1_gyro_en
int inv_icm406xx_wr_fifo_config1_gyro_en(struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG1_GYRO_t new_value)
Set FIFO_CONFIG1 register FIFO_GYRO_EN bit.
Definition: Icm406xxDriver.c:1685
inv_icm406xx_rd_accel_config1_avg_filt_rate
int inv_icm406xx_rd_accel_config1_avg_filt_rate(struct inv_icm406xx *s, ICM406XX_ACCEL_CONFIG1_AVG_FILT_RATE_t *value)
Get ACCEL_CONFIG1 register AVG_FILT_RATE bit.
Definition: Icm406xxDriver.c:1178
inv_icm406xx_wr_reg_bank_sel
int inv_icm406xx_wr_reg_bank_sel(struct inv_icm406xx *s, uint8_t new_value)
Set REG_BANK_SEL register value.
Definition: Icm406xxDriver.c:1859
inv_icm406xx_rd_gyro_config0_odr
int inv_icm406xx_rd_gyro_config0_odr(struct inv_icm406xx *s, ICM406XX_GYRO_CONFIG0_ODR_t *value)
Get GYRO_CONFIG0 register GYRO_ODR bits.
Definition: Icm406xxDriver.c:756
inv_icm406xx_wr_device_config_reset
int inv_icm406xx_wr_device_config_reset(struct inv_icm406xx *s, ICM406XX_DEVICE_CONFIG_RESET_t new_value)
Set DEVICE_CONFIG register SOFT_RESET_CONFIG bit.
Definition: Icm406xxDriver.c:69
inv_icm406xx_wr_intf_config0_spi_mode_ois1
int inv_icm406xx_wr_intf_config0_spi_mode_ois1(struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_SPI_MODE_OIS1_t new_value)
Set INTF_CONFIG0 register SPI_MODE_OIS1 bit.
Definition: Icm406xxDriver.c:440
inv_icm406xx_wr_tmst_config_resolution
int inv_icm406xx_wr_tmst_config_resolution(struct inv_icm406xx *s, ICM406XX_TMST_CONFIG_RESOL_t new_value)
Set TMST_CONFIG register TMST_RES bit.
Definition: Icm406xxDriver.c:1474
inv_icm406xx_rd_int_source0
int inv_icm406xx_rd_int_source0(struct inv_icm406xx *s, uint8_t *value)
Get INT_SOURCE0 register value.
Definition: Icm406xxDriver.c:1815
inv_icm406xx_wr_gyro_accel_config0_accel_filt_avg
int inv_icm406xx_wr_gyro_accel_config0_accel_filt_avg(struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t new_value)
Set GYRO_ACCEL_CONFIG0 register ACCEL_FILT bit.
Definition: Icm406xxDriver.c:1000
inv_icm406xx_wr_gyro_config0_fs_sel
int inv_icm406xx_wr_gyro_config0_fs_sel(struct inv_icm406xx *s, ICM406XX_GYRO_CONFIG0_FS_SEL_t new_value)
Set GYRO_CONFIG0 register GYRO_FS_SEL bits.
Definition: Icm406xxDriver.c:653
inv_icm406xx_rd_pwr_mgmt0_temp_en
int inv_icm406xx_rd_pwr_mgmt0_temp_en(struct inv_icm406xx *s, ICM406XX_PWR_MGMT_0_TEMP_t *value)
Read PWR_MGMT_0 register TEMP_DIS bit.
Definition: Icm406xxDriver.c:521
inv_icm406xx_wr_tmst_config_en
int inv_icm406xx_wr_tmst_config_en(struct inv_icm406xx *s, ICM406XX_TMST_CONFIG_TMST_EN_t new_value)
Set TMST_CONFIG register ICM406XX_TMST_CONFIG_EN bit.
Definition: Icm406xxDriver.c:1547
inv_icm406xx_wr_fifo_config1_temp_en
int inv_icm406xx_wr_fifo_config1_temp_en(struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG1_TEMP_t new_value)
Set FIFO_CONFIG1 register FIFO_TEMP_EN bit.
Definition: Icm406xxDriver.c:1655
inv_icm406xx_wr_intf_config0_data_endian
int inv_icm406xx_wr_intf_config0_data_endian(struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_DATA_COUNT_ENDIAN_t new_value)
Set INTF_CONFIG0 register DATA_ENDIAN bit.
Definition: Icm406xxDriver.c:363
inv_icm406xx_wr_ois1_config1_gyro_en
int inv_icm406xx_wr_ois1_config1_gyro_en(struct inv_icm406xx *s, ICM406XX_OIS1_CONFIG1_GYRO_EN_t new_value)
Set AUX1_CONFIG1 register GYRO_AUX1_EN bit.
Definition: Icm406xxDriver.c:2045
inv_icm406xx_rd_gyro_accel_config0_accel_filt_bw
int inv_icm406xx_rd_gyro_accel_config0_accel_filt_bw(struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t *value)
Get GYRO_ACCEL_CONFIG0 register ACCEL_FILT bit.
Definition: Icm406xxDriver.c:970
inv_icm406xx_rd_smd_config_wom_mode
int inv_icm406xx_rd_smd_config_wom_mode(struct inv_icm406xx *s, ICM406XX_SMD_CONFIG_WOM_MODE_t *value)
Get MPUREG_SMD_CONFIG register WOM_MODE bit.
Definition: Icm406xxDriver.c:1363
inv_icm406xx_rd_gyro_data_ois1
int inv_icm406xx_rd_gyro_data_ois1(struct inv_icm406xx *s, uint8_t value[GYRO_DATA_SIZE])
Get MPUREG_GYRO_DATA_X0_AUX1_B2.
Definition: Icm406xxDriver.c:2137
inv_icm406xx_wr_smd_config_wom_int_mode
int inv_icm406xx_wr_smd_config_wom_int_mode(struct inv_icm406xx *s, ICM406XX_SMD_CONFIG_WOM_INT_MODE_t new_value)
Set MPUREG_SMD_CONFIG register WOM_INT_MODE bit.
Definition: Icm406xxDriver.c:1288
inv_icm406xx_rd_int_status
int inv_icm406xx_rd_int_status(struct inv_icm406xx *s, uint8_t *value)
Get INT_STATUS register value.
Definition: Icm406xxDriver.c:192
inv_icm406xx_rd_gyro_config0_fs_sel
int inv_icm406xx_rd_gyro_config0_fs_sel(struct inv_icm406xx *s, ICM406XX_GYRO_CONFIG0_FS_SEL_t *value)
Get GYRO_CONFIG0 register GYRO_FS_SEL bits.
Definition: Icm406xxDriver.c:685
inv_icm406xx_wr_device_config_spi_mode
int inv_icm406xx_wr_device_config_spi_mode(struct inv_icm406xx *s, ICM406XX_DEVICE_CONFIG_SPI_MODE_t new_value)
Set DEVICE_CONFIG register SPI_MODE bits.
Definition: Icm406xxDriver.c:43
inv_icm406xx_wr_tmst_config_tmst_to_reg
int inv_icm406xx_wr_tmst_config_tmst_to_reg(struct inv_icm406xx *s, ICM406XX_TMST_CONFIG_TMST_TO_REGS_EN_t new_value)
Set TMST_CONFIG register TMST_TO_REGS_EN bit.
Definition: Icm406xxDriver.c:1448
inv_icm406xx_wr_ois2_config1_gyro_en
int inv_icm406xx_wr_ois2_config1_gyro_en(struct inv_icm406xx *s, ICM406XX_OIS2_CONFIG1_GYRO_EN_t new_value)
Set AUX2_CONFIG1 register GYRO_AUX2_EN bit.
Definition: Icm406xxDriver.c:2213
inv_icm406xx_wr_ois2_config1_dec
int inv_icm406xx_wr_ois2_config1_dec(struct inv_icm406xx *s, ICM406XX_OIS2_CONFIG1_DEC_t new_value)
Set AUX2_CONFIG1 register AUX2_DEC bit.
Definition: Icm406xxDriver.c:2186
inv_icm406xx_wr_tmst_config_fsync_en
int inv_icm406xx_wr_tmst_config_fsync_en(struct inv_icm406xx *s, ICM406XX_TMST_CONFIG_TMST_FSYNC_EN_t new_value)
Set TMST_CONFIG register TMST_FSYNC bit.
Definition: Icm406xxDriver.c:1500
inv_icm406xx_wr_intf_config4_ap_spi
int inv_icm406xx_wr_intf_config4_ap_spi(struct inv_icm406xx *s, ICM406XX_INTF_CONFIG4_AP_SPI_t new_value)
Set INTF_CONFIG4_B1 register SPI_AP_4WIRE bit.
Definition: Icm406xxDriver.c:1950
inv_icm406xx_wr_gyro_accel_config0_accel_filt_bw
int inv_icm406xx_wr_gyro_accel_config0_accel_filt_bw(struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t new_value)
Set GYRO_ACCEL_CONFIG0 register ACCEL_FILT bit.
Definition: Icm406xxDriver.c:937
inv_icm406xx_wr_accel_wom_y_thr
int inv_icm406xx_wr_accel_wom_y_thr(struct inv_icm406xx *s, uint8_t new_value)
Set ACCEL_WOM_Y_THR register WOM_Y_TH bits.
Definition: Icm406xxDriver.c:1228
inv_icm406xx_wr_ois2_config2_gyro_fs_sel
int inv_icm406xx_wr_ois2_config2_gyro_fs_sel(struct inv_icm406xx *s, ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_t new_value)
Set AUX2_CONFIG2 register GYRO_AUX2_FS_SEL bit.
Definition: Icm406xxDriver.c:2248
inv_icm406xx_rd_int_status_aux1
int inv_icm406xx_rd_int_status_aux1(struct inv_icm406xx *s, uint8_t *value)
Get INT_STATUS_AUX1 register value.
Definition: Icm406xxDriver.c:2157
inv_icm406xx_rd_who_am_i
int inv_icm406xx_rd_who_am_i(struct inv_icm406xx *s, uint8_t *value)
Get WHO_AM_I register value.
Definition: Icm406xxDriver.c:1847
inv_icm406xx_wr_ois1_config2_gyro_fs_sel
int inv_icm406xx_wr_ois1_config2_gyro_fs_sel(struct inv_icm406xx *s, ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_t new_value)
Set AUX1_CONFIG2 register GYRO_AUX1_FS_SEL bit.
Definition: Icm406xxDriver.c:2080
inv_icm406xx_wr_intf_config0_spi_mode_ois2
int inv_icm406xx_wr_intf_config0_spi_mode_ois2(struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_SPI_MODE_OIS2_t new_value)
Set INTF_CONFIG0 register SPI_MODE_AUX2 bit.
Definition: Icm406xxDriver.c:413
inv_icm406xx_wr_int_config1_asy_rst_dis
int inv_icm406xx_wr_int_config1_asy_rst_dis(struct inv_icm406xx *s, ICM406XX_INT_CONFIG1_ASY_RST_t new_value)
Set INT_CONFIG1 register ASY_RESET_DISABLE bit.
Definition: Icm406xxDriver.c:1782
inv_icm406xx_wr_int_cfg_int1_polarity
int inv_icm406xx_wr_int_cfg_int1_polarity(struct inv_icm406xx *s, ICM406XX_INT_CONFIG_INT1_POLARITY_t new_value)
Set INT_CONFIG register INT1_POLARITY bit.
Definition: Icm406xxDriver.c:121
inv_icm406xx_wr_accel_wom_x_thr
int inv_icm406xx_wr_accel_wom_x_thr(struct inv_icm406xx *s, uint8_t new_value)
Set ACCEL_WOM_X_THR register WOM_X_TH bits.
Definition: Icm406xxDriver.c:1199
inv_icm406xx_wr_ois1_config1_dec
int inv_icm406xx_wr_ois1_config1_dec(struct inv_icm406xx *s, ICM406XX_OIS1_CONFIG1_DEC_t new_value)
Set AUX1_CONFIG1 register AUX1_DEC bit.
Definition: Icm406xxDriver.c:2018
inv_icm406xx_wr_gyro_accel_config0_gyro_filt_avg
int inv_icm406xx_wr_gyro_accel_config0_gyro_filt_avg(struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_AVG_t new_value)
Set GYRO_ACCEL_CONFIG0 register GYRO_FILT_AVG bit.
Definition: Icm406xxDriver.c:1126
inv_icm406xx_wr_signal_path_rst_tmst_strobe
int inv_icm406xx_wr_signal_path_rst_tmst_strobe(struct inv_icm406xx *s, ICM406XX_SIGNAL_PATH_RESET_TMST_STROBE_t new_value)
Set SIGNAL_PATH_RESET register TMST_STROBE bit.
Definition: Icm406xxDriver.c:227
inv_icm406xx_rd_accel_config0_odr
int inv_icm406xx_rd_accel_config0_odr(struct inv_icm406xx *s, ICM406XX_ACCEL_CONFIG0_ODR_t *value)
Read ACCEL_CONFIG0 register ACCEL_ODR bits.
Definition: Icm406xxDriver.c:883
inv_icm406xx_wr_intf_config1_accel_lp_clk_sel
int inv_icm406xx_wr_intf_config1_accel_lp_clk_sel(struct inv_icm406xx *s, ICM406XX_INTF_CONFIG1_ACCEL_LP_CLK_SEL_t new_value)
Set INTF_CONFIG1 register ACCEL_LP_CLK_SEL bit.
Definition: Icm406xxDriver.c:467
inv_icm406xx_wr_pwr_mgmt0_gyro_mode
int inv_icm406xx_wr_pwr_mgmt0_gyro_mode(struct inv_icm406xx *s, ICM406XX_PWR_MGMT_0_GYRO_MODE_t new_value)
Set PWR_MGMT_0 register GYRO_MODE bit.
Definition: Icm406xxDriver.c:544
inv_icm406xx_rd_ois2_config2_gyro_fs_sel
int inv_icm406xx_rd_ois2_config2_gyro_fs_sel(struct inv_icm406xx *s, ICM406XX_OIS2_CONFIG2_GYRO_FS_SEL_t *value)
Get AUX2_CONFIG2 register GYRO_AUX2_FS_SEL bit.
Definition: Icm406xxDriver.c:2283
inv_icm406xx_wr_fifo_config_mode
int inv_icm406xx_wr_fifo_config_mode(struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG_MODE_t new_value)
Set FIFO_CONFIG register FIFO_MODE bit.
Definition: Icm406xxDriver.c:148
inv_icm406xx_rd_tmst_val
int inv_icm406xx_rd_tmst_val(struct inv_icm406xx *s, uint8_t value[3])
Get TMST_VAL from TMST_VAL0_B1, TMST_VAL1_B1 and TMST_VAL2_B1 registers.
Definition: Icm406xxDriver.c:1869
inv_icm406xx_wr_intf_config0_fifo_count_rec
int inv_icm406xx_wr_intf_config0_fifo_count_rec(struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_FIFO_COUNT_REC_t new_value)
Set INTF_CONFIG0 register FIFO_COUNT_REC bit.
Definition: Icm406xxDriver.c:309
inv_icm406xx_wr_fifo_config1_hires
int inv_icm406xx_wr_fifo_config1_hires(struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG1_HIRES_t new_value)
Set FIFO_CONFIG1 register FIFO_HIRES_EN bit.
Definition: Icm406xxDriver.c:1598
inv_icm406xx_wr_gyro_config1_avg_filt_rate
int inv_icm406xx_wr_gyro_config1_avg_filt_rate(struct inv_icm406xx *s, ICM406XX_GYRO_CONFIG1_AVG_FILT_RATE_t new_value)
Set GYRO_CONFIG1 register AVG_FILT_RATE bit.
Definition: Icm406xxDriver.c:905
inv_icm406xx_rd_int_source1
int inv_icm406xx_rd_int_source1(struct inv_icm406xx *s, uint8_t *value)
Get INT_SOURCE1 register value.
Definition: Icm406xxDriver.c:1835
inv_icm406xx_wr_accel_config1_avg_filt_rate
int inv_icm406xx_wr_accel_config1_avg_filt_rate(struct inv_icm406xx *s, ICM406XX_ACCEL_CONFIG1_AVG_FILT_RATE_t new_value)
Set ACCEL_CONFIG1 register AVG_FILT_RATE bit.
Definition: Icm406xxDriver.c:1152
inv_icm406xx_wr_int_cfg_int1_drive_circuit
int inv_icm406xx_wr_int_cfg_int1_drive_circuit(struct inv_icm406xx *s, ICM406XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t new_value)
Set INT_CONFIG register INT1_DRIVE_CIRCUIT bit.
Definition: Icm406xxDriver.c:95
inv_icm406xx_wr_fifo_config1_tmst_fsync
int inv_icm406xx_wr_fifo_config1_tmst_fsync(struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG1_TMST_FSYNC_t new_value)
Set FIFO_CONFIG1 register FIFO_TMST_FSYNC_EN bit.
Definition: Icm406xxDriver.c:1624
inv_icm406xx_rd_smd_config_wom_int_mode
int inv_icm406xx_rd_smd_config_wom_int_mode(struct inv_icm406xx *s, ICM406XX_SMD_CONFIG_WOM_INT_MODE_t *value)
Get MPUREG_SMD_CONFIG register WOM_INT_MODE bit.
Definition: Icm406xxDriver.c:1314
inv_icm406xx_wr_pwr_mgmt0_accel_mode
int inv_icm406xx_wr_pwr_mgmt0_accel_mode(struct inv_icm406xx *s, ICM406XX_PWR_MGMT_0_ACCEL_MODE_t new_value)
Set PWR_MGMT_0 register ACCEL_MODE bit.
Definition: Icm406xxDriver.c:596
inv_icm406xx_wr_intf_config0_fifo_count_endian
int inv_icm406xx_wr_intf_config0_fifo_count_endian(struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t new_value)
Set INTF_CONFIG0 register FIFO_COUNT_ENDIAN bit.
Definition: Icm406xxDriver.c:336
inv_icm406xx_rd_accel_config0_fs_sel
int inv_icm406xx_rd_accel_config0_fs_sel(struct inv_icm406xx *s, ICM406XX_ACCEL_CONFIG0_FS_SEL_t *value)
Get ACCEL_CONFIG0 register ACCEL_FS_SEL bits.
Definition: Icm406xxDriver.c:811
inv_icm406xx_wr_intf_config4_aux_spi
int inv_icm406xx_wr_intf_config4_aux_spi(struct inv_icm406xx *s, ICM406XX_INTF_CONFIG4_AUX_SPI_t new_value)
Set INTF_CONFIG4_B1 register SPI_AUX1_4WIRE bit.
Definition: Icm406xxDriver.c:1889
inv_icm406xx_rd_int_status2
int inv_icm406xx_rd_int_status2(struct inv_icm406xx *s, uint8_t *value)
Get INT_STATUS2 register value.
Definition: Icm406xxDriver.c:1435
inv_icm406xx_rd_gyro_accel_config0_gyro_filt_bw
int inv_icm406xx_rd_gyro_accel_config0_gyro_filt_bw(struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t *value)
Get GYRO_ACCEL_CONFIG0 register GYRO_FILT_BW bit.
Definition: Icm406xxDriver.c:1096
inv_icm406xx_wr_accel_wom_z_thr
int inv_icm406xx_wr_accel_wom_z_thr(struct inv_icm406xx *s, uint8_t new_value)
Set ACCEL_WOM_Z_THR register WOM_Z_TH bits.
Definition: Icm406xxDriver.c:1257
inv_icm406xx_rd_gyro_accel_config0_accel_filt_avg
int inv_icm406xx_rd_gyro_accel_config0_accel_filt_avg(struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t *value)
Get GYRO_ACCEL_CONFIG0 register ACCEL_FILT bit.
Definition: Icm406xxDriver.c:1034
inv_icm406xx_rd_ois1_config2_gyro_fs_sel
int inv_icm406xx_rd_ois1_config2_gyro_fs_sel(struct inv_icm406xx *s, ICM406XX_OIS1_CONFIG2_GYRO_FS_SEL_t *value)
Get AUX1_CONFIG2 register GYRO_AUX1_FS_SEL bit.
Definition: Icm406xxDriver.c:2115
inv_icm406xx_wr_fifo_config1_wm_gt_th
int inv_icm406xx_wr_fifo_config1_wm_gt_th(struct inv_icm406xx *s, ICM406XX_FIFO_CONFIG1_WM_GT_t new_value)
Set FIFO_CONFIG1 register FIFO_WM_GT_TH bit.
Definition: Icm406xxDriver.c:1572
inv_icm406xx_wr_int_source1
int inv_icm406xx_wr_int_source1(struct inv_icm406xx *s, uint8_t new_value)
Set INT_SOURCE1 register value.
Definition: Icm406xxDriver.c:1825
inv_icm406xx_wr_int_source0
int inv_icm406xx_wr_int_source0(struct inv_icm406xx *s, uint8_t new_value)
Set INT_SOURCE0 register value.
Definition: Icm406xxDriver.c:1805
inv_icm406xx_rd_pwr_mgmt0_gyro_mode
int inv_icm406xx_rd_pwr_mgmt0_gyro_mode(struct inv_icm406xx *s, ICM406XX_PWR_MGMT_0_GYRO_MODE_t *value)
Read PWR_MGMT_0 register GYRO_MODE bit.
Definition: Icm406xxDriver.c:572
inv_icm406xx_wr_fifo_config2
int inv_icm406xx_wr_fifo_config2(struct inv_icm406xx *s, uint8_t new_value)
Set FIFO_CONFIG2 register value.
Definition: Icm406xxDriver.c:1736
inv_icm406xx_rd_intf_config0_data_endian
int inv_icm406xx_rd_intf_config0_data_endian(struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_DATA_COUNT_ENDIAN_t *value)
Get INTF_CONFIG0 register DATA_ENDIAN bit.
Definition: Icm406xxDriver.c:390
inv_icm406xx_wr_intf_config0_fifo_sreg_invalid_ind
int inv_icm406xx_wr_intf_config0_fifo_sreg_invalid_ind(struct inv_icm406xx *s, ICM406XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t new_value)
Set INTF_CONFIG0 register FIFO_SREG_INVALID_IND bit.
Definition: Icm406xxDriver.c:282
inv_icm406xx_rd_gyro_data_ois2
int inv_icm406xx_rd_gyro_data_ois2(struct inv_icm406xx *s, uint8_t value[GYRO_DATA_SIZE])
Get MPUREG_GYRO_DATA_X0_AUX2_B2.
Definition: Icm406xxDriver.c:2305
inv_icm406xx_rd_intf_config4_aux_spi
int inv_icm406xx_rd_intf_config4_aux_spi(struct inv_icm406xx *s, ICM406XX_INTF_CONFIG4_AUX_SPI_t *value)
Get INTF_CONFIG4_B1 register SPI_AUX1_4WIRE bit.
Definition: Icm406xxDriver.c:1921
inv_icm406xx_rd_tmst_config_fsync_en
int inv_icm406xx_rd_tmst_config_fsync_en(struct inv_icm406xx *s, ICM406XX_TMST_CONFIG_TMST_FSYNC_EN_t *value)
Read TMST_CONFIG register TMST_FSYNC bit.
Definition: Icm406xxDriver.c:1525
inv_icm406xx_rd_smd_config_smd_mode
int inv_icm406xx_rd_smd_config_smd_mode(struct inv_icm406xx *s, ICM406XX_SMD_CONFIG_SMD_MODE_t *value)
Get MPUREG_SMD_CONFIG register SMD_MODE bit.
Definition: Icm406xxDriver.c:1416
inv_icm406xx_wr_gyro_accel_config0_gyro_filt_bw
int inv_icm406xx_wr_gyro_accel_config0_gyro_filt_bw(struct inv_icm406xx *s, ICM406XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t new_value)
Set GYRO_ACCEL_CONFIG0 register GYRO_FILT_BW bit.
Definition: Icm406xxDriver.c:1063
inv_icm406xx_rd_intf_config4_ap_spi
int inv_icm406xx_rd_intf_config4_ap_spi(struct inv_icm406xx *s, ICM406XX_INTF_CONFIG4_AP_SPI_t *value)
Get INTF_CONFIG4_B1 register SPI_AP_4WIRE bit.
Definition: Icm406xxDriver.c:1982
inv_icm406xx_wr_accel_config0_fs_sel
int inv_icm406xx_wr_accel_config0_fs_sel(struct inv_icm406xx *s, ICM406XX_ACCEL_CONFIG0_FS_SEL_t new_value)
Set ACCEL_CONFIG0 register ACCEL_FS_SEL bits.
Definition: Icm406xxDriver.c:781
inv_icm406xx_wr_signal_path_rst_fifo_flush
int inv_icm406xx_wr_signal_path_rst_fifo_flush(struct inv_icm406xx *s, ICM406XX_SIGNAL_PATH_RESET_FIFO_FLUSH_t new_value)
Set SIGNAL_PATH_RESET register FIFO_FLUSH bit.
Definition: Icm406xxDriver.c:255
inv_icm406xx_wr_pwr_mgmt0_temp_en
int inv_icm406xx_wr_pwr_mgmt0_temp_en(struct inv_icm406xx *s, ICM406XX_PWR_MGMT_0_TEMP_t new_value)
Set PWR_MGMT_0 register TEMP_DIS bit.
Definition: Icm406xxDriver.c:495
inv_icm406xx_rd_fifo_count
int inv_icm406xx_rd_fifo_count(struct inv_icm406xx *s, uint8_t value[2])
Get FIFO count from FIFO_COUNTL and FIFO_COUNTH registers.
Definition: Icm406xxDriver.c:202
inv_icm406xx_rd_fifo
int inv_icm406xx_rd_fifo(struct inv_icm406xx *s, int len, uint8_t *value)
Read FIFO_DATA_REG.
Definition: Icm406xxDriver.c:213
fifo_header_t
Definition: Icm406xxDefs.h:249
inv_icm406xx
Icm406xx driver states definition.
Definition: Icm406xxDriver_HL.h:79