| ICM42605 eMD Driver 2.0.9 Documentation of the eMD Driver API

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Icm426xxDefs.h File Reference

File exposing the device register map. More...

`#include <stdint.h>`
Include dependency graph for Icm426xxDefs.h:
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Go to the source code of this file.

## Classes
union | fifo_header_t
| Describe the content of the FIFO header. More...

## Macros
#define | ICM40608_WHOAMI 0x39
#define | ICM42600_WHOAMI 0x40
#define | ICM42602_WHOAMI 0x41
#define | ICM42605_WHOAMI 0x42
#define | ICM42622_WHOAMI 0x46
#define | ICM42631_WHOAMI 0x5C
#define | ICM42633_WHOAMI 0x5B
#define | ICM42686P_WHOAMI 0x44
#define | ICM42688P_WHOAMI 0x47
#define | ICM42686V_WHOAMI 0xDA
#define | ICM42688V_WHOAMI 0xDB
#define | ICM42608_WHOAMI 0x48
#define | ICM_FAMILY_BPLUS
| ICM family definition Possible values are ICM_FAMILY_CPLUS or ICM_FAMILY_BPLUS. More...
#define | MPUREG_DEVICE_CONFIG 0x11
#define | MPUREG_CHIP_CONFIG MPUREG_DEVICE_CONFIG
#define | MPUREG_DRIVE_CONFIG 0x13
#define | MPUREG_INT_CONFIG 0x14
#define | MPUREG_FIFO_CONFIG 0x16
#define | MPUREG_TEMP_DATA0_UI 0x1D
#define | MPUREG_ACCEL_DATA_X0_UI 0x1F
#define | MPUREG_GYRO_DATA_X0_UI 0x25
#define | MPUREG_TMST_FSYNCH 0x2B
#define | MPUREG_TMST_FSYNC1 MPUREG_TMST_FSYNCH
#define | MPUREG_INT_STATUS 0x2D
#define | MPUREG_FIFO_COUNTH 0x2E
#define | MPUREG_FIFO_BYTE_COUNT1 MPUREG_FIFO_COUNTH
#define | MPUREG_FIFO_COUNTL 0x2F
#define | MPUREG_FIFO_BYTE_COUNT2 MPUREG_FIFO_COUNTL
#define | MPUREG_FIFO_DATA 0x30
#define | MPUREG_APEX_DATA0 0x31
#define | MPUREG_APEX_DATA1 0x32
#define | MPUREG_APEX_DATA2 0x33
#define | MPUREG_APEX_DATA3 0x34
#define | MPUREG_APEX_DATA4 0x35
#define | MPUREG_APEX_DATA5 0x36
#define | MPUREG_INT_STATUS2 0x37
#define | MPUREG_INT_STATUS3 0x38
#define | MPUREG_SIGNAL_PATH_RESET 0x4B
#define | MPUREG_INTF_CONFIG0 0x4C
#define | MPUREG_INTF_CONFIG1 0x4D
#define | MPUREG_PWR_MGMT_0 0x4E
#define | MPUREG_GYRO_CONFIG0 0x4F
#define | MPUREG_ACCEL_CONFIG0 0x50
#define | MPUREG_GYRO_CONFIG1 0x51
#define | MPUREG_ACCEL_GYRO_CONFIG0 0x52
#define | MPUREG_ACCEL_CONFIG1 0x53
#define | MPUREG_TMST_CONFIG 0x54
#define | MPUREG_APEX_CONFIG0 0x56
#define | MPUREG_SMD_CONFIG 0x57
#define | MPUREG_FIFO_CONFIG1 0x5F
#define | MPUREG_FIFO_CONFIG2 0x60
#define | MPUREG_FSYNC_CONFIG 0x62
#define | MPUREG_INT_CONFIG0 0x63
#define | MPUREG_INT_CONFIG1 0x64
#define | MPUREG_INT_SOURCE0 0x65
#define | MPUREG_INT_SOURCE1 0x66
#define | MPUREG_INT_SOURCE2 0x67
#define | MPUREG_INT_SOURCE3 0x68
#define | MPUREG_INT_SOURCE4 0x69
#define | MPUREG_INT_SOURCE5 0x6A
#define | MPUREG_FIFO_LOST_PKT0 0x6C
#define | MPUREG_SELF_TEST_CONFIG 0x70
#define | MPUREG_WHO_AM_I 0x75
#define | MPUREG_SCAN0 0x71
#define | MPUREG_MEM_BANK_SEL 0x72
#define | MPUREG_MEM_START_ADDR 0x73
#define | MPUREG_MEM_R_W 0x74
#define | MPUREG_REG_BANK_SEL 0x76
#define | MPUREG_SENSOR_CONFIG1_B1 0x04
#define | MPUREG_GYRO_CONFIG_STATIC2_B1 0x0B
#define | MPUREG_GYRO_CONFIG_STATIC3_B1 0x0C
#define | MPUREG_GYRO_CONFIG_STATIC4_B1 0x0D
#define | MPUREG_GYRO_CONFIG_STATIC5_B1 0x0E
#define | MPUREG_XG_ST_DATA_B1 0x5F
#define | MPUREG_YG_ST_DATA_B1 0x60
#define | MPUREG_ZG_ST_DATA_B1 0x61
#define | MPUREG_TMST_VAL0_B1 0x62
#define | MPUREG_INTF_CONFIG4_B1 0x7A
#define | MPUREG_INTF_CONFIG5_B1 0x7B
#define | MPUREG_INTF_CONFIG6_B1 0x7C
#define | MPUREG_INTF_CONFIG3_B1 0x79
#define | MPUREG_ACCEL_CONFIG_STATIC2_B2 0x03
#define | MPUREG_ACCEL_CONFIG_STATIC3_B2 0x04
#define | MPUREG_ACCEL_CONFIG_STATIC4_B2 0x05
#define | MPUREG_ACCEL_CONFIG_STATIC0_B2 0x39
#define | MPUREG_XA_ST_DATA_B2 0x3B
#define | MPUREG_YA_ST_DATA_B2 0x3C
#define | MPUREG_ZA_ST_DATA_B2 0x3D
#define | MPUREG_OIS1_CONFIG1_B2 0x44
#define | MPUREG_OIS1_CONFIG2_B2 0x45
#define | MPUREG_OIS1_CONFIG3_B2 0x46
#define | MPUREG_ACCEL_DATA_X0_OIS1_B2 0x49
#define | MPUREG_GYRO_DATA_X0_OIS1_B2 0x4F
#define | MPUREG_INT_STATUS_OIS1_B2 0x57
#define | MPUREG_OIS2_CONFIG1_B2 0x59
#define | MPUREG_OIS2_CONFIG2_B2 0x5A
#define | MPUREG_OIS2_CONFIG3_B2 0x5B
#define | MPUREG_ACCEL_DATA_X0_OIS2_B2 0x5E
#define | MPUREG_GYRO_DATA_X0_OIS2_B2 0x64
#define | MPUREG_INT_STATUS_OIS2_B2 0x6C
#define | MPUREG_TMD4_B2 0x70
#define | MPUREG_TMD5_B2 0x71
#define | MPUREG_TMD6_B2 0x72
#define | MPUREG_TMD7_B2 0x73
#define | MPUREG_PU_PD_CONFIG1_B3 0x06
#define | MPUREG_PU_PD_CONFIG2_B3 0x0E
#define | MPUREG_FDR_CONFIG_B4 0x09
#define | MPUREG_APEX_CONFIG1_B4 0x40
#define | MPUREG_APEX_CONFIG2_B4 0x41
#define | MPUREG_APEX_CONFIG3_B4 0x42
#define | MPUREG_APEX_CONFIG4_B4 0x43
#define | MPUREG_APEX_CONFIG5_B4 0x44
#define | MPUREG_APEX_CONFIG6_B4 0x45
#define | MPUREG_APEX_CONFIG7_B4 0x46
#define | MPUREG_APEX_CONFIG8_B4 0x47
#define | MPUREG_APEX_CONFIG9_B4 0x48
#define | MPUREG_APEX_CONFIG10_B4 0x49
#define | MPUREG_ACCEL_WOM_X_THR_B4 0x4A
#define | MPUREG_ACCEL_WOM_Y_THR_B4 0x4B
#define | MPUREG_ACCEL_WOM_Z_THR_B4 0x4C
#define | MPUREG_INT_SOURCE6_B4 0x4D
#define | MPUREG_INT_SOURCE7_B4 0x4E
#define | MPUREG_INT_SOURCE8_B4 0x4F
#define | MPUREG_INT_SOURCE9_B4 0x50
#define | MPUREG_INT_SOURCE10_B4 0x51
#define | MPUREG_OFFSET_USER_0_B4 0x77
#define | MPUREG_OFFSET_USER_1_B4 0x78
#define | MPUREG_OFFSET_USER_2_B4 0x79
#define | MPUREG_OFFSET_USER_3_B4 0x7A
#define | MPUREG_OFFSET_USER_4_B4 0x7B
#define | MPUREG_OFFSET_USER_5_B4 0x7C
#define | MPUREG_OFFSET_USER_6_B4 0x7D
#define | MPUREG_OFFSET_USER_7_B4 0x7E
#define | MPUREG_OFFSET_USER_8_B4 0x7F
#define | ACCEL_DATA_SIZE 6
#define | GYRO_DATA_SIZE 6
#define | TEMP_DATA_SIZE 2
#define | FIFO_HEADER_SIZE 1
#define | FIFO_ACCEL_DATA_SIZE ACCEL_DATA_SIZE
#define | FIFO_GYRO_DATA_SIZE GYRO_DATA_SIZE
#define | FIFO_TEMP_DATA_SIZE 1
#define | FIFO_TS_FSYNC_SIZE 2
#define | FIFO_TEMP_HIGH_RES_SIZE 1
#define | FIFO_ACCEL_GYRO_HIGH_RES_SIZE 3
#define | FIFO_16BYTES_PACKET_SIZE
#define | FIFO_20BYTES_PACKET_SIZE
#define | FIFO_HEADER_ODR_ACCEL 0x01
#define | FIFO_HEADER_ODR_GYRO 0x02
#define | FIFO_HEADER_FSYNC 0x04
#define | FIFO_HEADER_TMST 0x08
#define | FIFO_HEADER_HEADER_20 0x10
#define | FIFO_HEADER_GYRO 0x20
#define | FIFO_HEADER_ACC 0x40
#define | FIFO_HEADER_MSG 0x80
#define | INVALID_VALUE_FIFO ((int16_t)0x8000)
#define | INVALID_VALUE_FIFO_1B ((int8_t)0x80)
#define | I3C_IBI_PAYLOAD_ALL 0xFF
#define | I3C_IBI_PAYLOAD_TIMEC 0x80
#define | I3C_IBI_PAYLOAD_CAT_MISC 0x40
#define | I3C_IBI_PAYLOAD_CAT_ERROR 0x20
#define | I3C_IBI_PAYLOAD_CAT_APEX2 0x10
#define | I3C_IBI_PAYLOAD_CAT_APEX1 0x08
#define | I3C_IBI_PAYLOAD_CAT_OIS1_DRDY 0x04
#define | I3C_IBI_PAYLOAD_CAT_FIFO 0x02
#define | I3C_IBI_PAYLOAD_CAT_UI_DRDY 0x01
#define | BIT_DEVICE_CONFIG_SPI_MODE_POS 4
#define | BIT_DEVICE_CONFIG_SPI_MODE_MASK (0x1 << BIT_DEVICE_CONFIG_SPI_MODE_POS)
#define | BIT_CHIP_CONFIG_SPI_MODE_MASK BIT_DEVICE_CONFIG_SPI_MODE_MASK
#define | BIT_CHIP_CONFIG_SPI_MODE_POS BIT_DEVICE_CONFIG_SPI_MODE_POS
#define | BIT_DEVICE_CONFIG_RESET_POS 0
#define | BIT_DEVICE_CONFIG_RESET_MASK 0x01
#define | BIT_CHIP_CONFIG_RESET_MASK BIT_DEVICE_CONFIG_RESET_MASK
#define | BIT_CHIP_CONFIG_RESET_POS BIT_DEVICE_CONFIG_RESET_POS
#define | BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS 4
#define | BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS)
#define | BIT_INT_CONFIG_INT2_POLARITY_POS 3
#define | BIT_INT_CONFIG_INT2_POLARITY_MASK (0x01 << BIT_INT_CONFIG_INT2_POLARITY_POS)
#define | BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS 1
#define | BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS)
#define | BIT_INT_CONFIG_INT1_POLARITY_POS 0
#define | BIT_INT_CONFIG_INT1_POLARITY_MASK 0x01
#define | BIT_FIFO_CONFIG_MODE_POS 6
#define | BIT_FIFO_CONFIG_MODE_MASK (0x03 << BIT_FIFO_CONFIG_MODE_POS)
#define | ICM426XX_FIFO_CONFIG_MODE_SNAPSHOT = ICM426XX_FIFO_CONFIG_MODE_STOP_ON_FULL;
#define | BIT_INT_STATUS_UI_FSYNC 0x40
#define | BIT_INT_STATUS_PLL_RDY 0x20
#define | BIT_INT_STATUS_RESET_DONE 0x10
#define | BIT_INT_STATUS_DRDY 0x08
#define | BIT_INT_STATUS_FIFO_THS 0x04
#define | BIT_INT_STATUS_FIFO_FULL 0x02
#define | BIT_INT_STATUS_AGC_RDY 0x01
#define | BIT_APEX_DATA3_ACTIVITY_CLASS_POS 0
#define | BIT_APEX_DATA3_ACTIVITY_CLASS_MASK 0x03
#define | BIT_APEX_DATA3_DMP_IDLE_POS 2
#define | BIT_APEX_DATA3_DMP_IDLE_MASK (0x01 << BIT_APEX_DATA3_DMP_IDLE_POS)
#define | BIT_APEX_DATA4_TAP_NUM_POS 3
| TAP status flags: non-zero value - tap detected bit0 - positive or negative edge bit1 and 2 - axis detected : 0-X ; 1-Y ; 2-Z bit3 and 4 - tap type : 1-single ; 2 -double. More...
#define | BIT_APEX_DATA4_TAP_NUM_MASK (0x03 << BIT_APEX_DATA4_TAP_NUM_POS)
#define | BIT_APEX_DATA4_TAP_AXIS_POS 1
#define | BIT_APEX_DATA4_TAP_AXIS_MASK (0x03 << BIT_APEX_DATA4_TAP_AXIS_POS)
#define | BIT_APEX_DATA4_TAP_DIR_POS 0
#define | BIT_APEX_DATA4_TAP_DIR_MASK 0x01
#define | BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS 0
#define | BIT_APEX_DATA5_DOUBLE_TAP_TIMING_MASK (0x3F << BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS)
#define | BIT_INT_STATUS2_SMD_INT 0x08
#define | BIT_INT_STATUS2_WOM_Z_INT 0x04
#define | BIT_INT_STATUS2_WOM_Y_INT 0x02
#define | BIT_INT_STATUS2_WOM_X_INT 0x01
#define | BIT_INT_STATUS3_STEP_DET 0x20
#define | BIT_INT_STATUS3_STEP_CNT_OVFL 0x10
#define | BIT_INT_STATUS3_TILT_DET 0x08
#define | BIT_INT_STATUS3_WAKE_DET 0x04
#define | BIT_INT_STATUS3_SLEEP_DET 0x02
#define | BIT_INT_STATUS3_TAP_DET 0x01
#define | BIT_SIGNAL_PATH_RESET_DMP_INIT_POS 6
#define | BIT_SIGNAL_PATH_RESET_DMP_INIT_MASK (0x01 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS)
#define | BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS 5
#define | BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_MASK (0x01 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS)
#define | BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS 2
#define | BIT_SIGNAL_PATH_RESET_TMST_STROBE_MASK (0x01 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS)
#define | BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS 1
#define | BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_MASK (0x01 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS)
#define | BIT_FIFO_SREG_INVALID_IND_POS 7
#define | BIT_FIFO_SREG_INVALID_IND_MASK (0x01 << BIT_FIFO_SREG_INVALID_IND_POS)
#define | BIT_FIFO_COUNT_REC_POS 6
#define | BIT_FIFO_COUNT_REC_MASK (0x01 << BIT_FIFO_COUNT_REC_POS)
#define | BIT_FIFO_COUNT_ENDIAN_POS 5
#define | BIT_FIFO_COUNT_ENDIAN_MASK (0x01 << BIT_FIFO_COUNT_ENDIAN_POS)
#define | BIT_DATA_ENDIAN_POS 4
#define | BIT_DATA_ENDIAN_MASK (0x01 << BIT_DATA_ENDIAN_POS)
#define | BIT_SPI_MODE_OIS2_POS 3
#define | BIT_SPI_MODE_OIS2_MASK (0x01 << BIT_SPI_MODE_OIS2_POS)
#define | BIT_SPI_MODE_OIS1_POS 2
#define | BIT_SPI_MODE_OIS1_MASK (0x01 << BIT_SPI_MODE_OIS1_POS)
#define | BIT_ACCEL_LP_CLK_SEL_POS 3
#define | BIT_ACCEL_LP_CLK_SEL_MASK (0x01 << BIT_ACCEL_LP_CLK_SEL_POS)
#define | BIT_RTC_MODE_POS 2
#define | BIT_RTC_MODE_MASK (0x01 << BIT_RTC_MODE_POS)
#define | BIT_PWR_MGMT_0_TEMP_POS 5
#define | BIT_PWR_MGMT_0_TEMP_MASK (0x01 << BIT_PWR_MGMT_0_TEMP_POS)
#define | BIT_PWR_MGMT_0_IDLE_POS 4
#define | BIT_PWR_MGMT_0_IDLE_MASK (0x01 << BIT_PWR_MGMT_0_IDLE_POS)
#define | BIT_PWR_MGMT_0_GYRO_MODE_POS 2
#define | BIT_PWR_MGMT_0_GYRO_MODE_MASK (0x03 << BIT_PWR_MGMT_0_GYRO_MODE_POS)
#define | BIT_PWR_MGMT_0_ACCEL_MODE_POS 0
#define | BIT_PWR_MGMT_0_ACCEL_MODE_MASK 0x03
#define | BIT_GYRO_CONFIG0_FS_SEL_POS 5
#define | BIT_GYRO_CONFIG0_FS_SEL_MASK (7 << BIT_GYRO_CONFIG0_FS_SEL_POS)
#define | BIT_GYRO_CONFIG0_ODR_POS 0
#define | BIT_GYRO_CONFIG0_ODR_MASK 0x0F
#define | BIT_ACCEL_CONFIG0_FS_SEL_POS 5
#define | BIT_ACCEL_CONFIG0_FS_SEL_MASK (0x7 << BIT_ACCEL_CONFIG0_FS_SEL_POS)
#define | BIT_ACCEL_CONFIG0_ODR_POS 0
#define | BIT_ACCEL_CONFIG0_ODR_MASK 0x0F
#define | BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS 5
#define | BIT_GYRO_CONFIG1_TEMP_FILT_BW_MASK (0x7 << BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS)
#define | BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS 2
#define | BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_MASK (0x3 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS)
#define | BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_POS 0
#define | BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_MASK 0x3
#define | BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS 4
#define | BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_MASK (0xF << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS)
#define | BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_POS 0
#define | BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_MASK 0x0F
#define | BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS 3
#define | BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS)
#define | BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS 1
#define | BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS)
#define | BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS 4
#define | BIT_TMST_CONFIG_TMST_TO_REGS_EN_MASK (0x1 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS)
#define | BIT_TMST_CONFIG_RESOL_POS 3
#define | BIT_TMST_CONFIG_RESOL_MASK (0x1 << BIT_TMST_CONFIG_RESOL_POS)
#define | BIT_TMST_CONFIG_TMST_FSYNC_POS 1
#define | BIT_TMST_CONFIG_TMST_FSYNC_MASK (0x1 << BIT_TMST_CONFIG_TMST_FSYNC_POS)
#define | BIT_TMST_CONFIG_TMST_EN_POS 0
#define | BIT_TMST_CONFIG_TMST_EN_MASK 0x1
#define | BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS 7
#define | BIT_APEX_CONFIG0_DMP_POWER_SAVE_MASK (0x1 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS)
#define | BIT_APEX_CONFIG0_TAP_ENABLE_POS 6
#define | BIT_APEX_CONFIG0_TAP_ENABLE_MASK (0x1 << BIT_APEX_CONFIG0_TAP_ENABLE_POS)
#define | BIT_APEX_CONFIG0_PEDO_EN_POS 5
#define | BIT_APEX_CONFIG0_PEDO_EN_MASK (0x1 << BIT_APEX_CONFIG0_PEDO_EN_POS)
#define | BIT_APEX_CONFIG0_R2W_EN_POS 3
#define | BIT_APEX_CONFIG0_R2W_EN_MASK (0x1 << BIT_APEX_CONFIG0_R2W_EN_POS)
#define | BIT_APEX_CONFIG0_TILT_EN_POS 4
#define | BIT_APEX_CONFIG0_TILT_EN_MASK (0x1 << BIT_APEX_CONFIG0_TILT_EN_POS)
#define | BIT_APEX_CONFIG0_DMP_ODR_POS 0
#define | BIT_APEX_CONFIG0_DMP_ODR_MASK (0x3 << BIT_APEX_CONFIG0_DMP_ODR_POS)
#define | BIT_SMD_CONFIG_WOM_INT_MODE_POS 3
#define | BIT_SMD_CONFIG_WOM_INT_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_INT_MODE_POS)
#define | BIT_SMD_CONFIG_WOM_MODE_POS 2
#define | BIT_SMD_CONFIG_WOM_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_MODE_POS)
#define | BIT_SMD_CONFIG_SMD_MODE_POS 0
#define | BIT_SMD_CONFIG_SMD_MODE_MASK 0x3
#define | BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS 6
#define | BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_MASK (0x1 << BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS)
#define | BIT_FIFO_CONFIG1_WM_GT_TH_POS 5
#define | BIT_FIFO_CONFIG1_WM_GT_TH_MASK (0x1 << BIT_FIFO_CONFIG1_WM_GT_TH_POS)
#define | BIT_FIFO_CONFIG1_HIRES_POS 4
#define | BIT_FIFO_CONFIG1_HIRES_MASK (0x1 << BIT_FIFO_CONFIG1_HIRES_POS)
#define | BIT_FIFO_CONFIG1_TMST_FSYNC_POS 3
#define | BIT_FIFO_CONFIG1_TMST_FSYNC_MASK (0x1 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS)
#define | BIT_FIFO_CONFIG1_TEMP_POS 2
#define | BIT_FIFO_CONFIG1_TEMP_MASK (0x1 << BIT_FIFO_CONFIG1_TEMP_POS)
#define | BIT_FIFO_CONFIG1_GYRO_POS 1
#define | BIT_FIFO_CONFIG1_GYRO_MASK (0x1 << BIT_FIFO_CONFIG1_GYRO_POS)
#define | BIT_FIFO_CONFIG1_ACCEL_POS 0
#define | BIT_FIFO_CONFIG1_ACCEL_MASK 0x1
#define | BIT_FSYNC_CONFIG_UI_SEL_POS 4
#define | BIT_FSYNC_CONFIG_UI_SEL_MASK (0x7 << BIT_FSYNC_CONFIG_UI_SEL_POS)
#define | BIT_INT_TPULSE_DURATION_POS 6
#define | BIT_INT_TPULSE_DURATION_MASK (0x1 << BIT_INT_TPULSE_DURATION_POS)
#define | BIT_INT_TDEASSERT_POS 5
#define | BIT_INT_TDEASSERT_MASK (0x1 << BIT_INT_TDEASSERT_POS)
#define | BIT_INT_CONFIG1_ASY_RST_POS 4
#define | BIT_INT_CONFIG1_ASY_RST_MASK (0x1 << BIT_INT_CONFIG1_ASY_RST_POS)
#define | BIT_INT_UI_FSYNC_INT_EN_POS 6
#define | BIT_INT_PLL_RDY_INT_EN_POS 5
#define | BIT_INT_RESET_DONE_INT_EN_POS 4
#define | BIT_INT_UI_DRDY_INT_EN_POS 3
#define | BIT_INT_FIFO_THS_INT_EN_POS 2
#define | BIT_INT_FIFO_FULL_INT_EN_POS 1
#define | BIT_INT_UI_AGC_RDY_INT_EN_POS 0
#define | BIT_INT_SOURCE0_UI_FSYNC_INT1_EN 0x40
#define | BIT_INT_SOURCE0_PLL_RDY_INT1_EN 0x20
#define | BIT_INT_SOURCE0_RESET_DONE_INT1_EN 0x10
#define | BIT_INT_SOURCE0_UI_DRDY_INT1_EN 0x08
#define | BIT_INT_SOURCE0_FIFO_THS_INT1_EN 0x04
#define | BIT_INT_SOURCE0_FIFO_FULL_INT1_EN 0x02
#define | BIT_INT_SOURCE0_UI_AGC_RDY_INT1_EN 0x01
#define | BIT_INT_SMD_INT_EN_POS 3
#define | BIT_INT_WOM_Z_INT_EN_POS 2
#define | BIT_INT_WOM_Y_INT_EN_POS 1
#define | BIT_INT_WOM_X_INT_EN_POS 0
#define | BIT_INT_SOURCE1_SMD_INT1_EN 0x08
#define | BIT_INT_SOURCE1_WOM_Z_INT1_EN 0x04
#define | BIT_INT_SOURCE1_WOM_Y_INT1_EN 0x02
#define | BIT_INT_SOURCE1_WOM_X_INT1_EN 0x01
#define | BIT_INT_SOURCE2_OIS2_AGC_RDY_INT1_EN 0x20
#define | BIT_INT_SOURCE2_OIS2_FSYNC_INT1_EN 0x10
#define | BIT_INT_SOURCE2_OIS2_DRDY_INT1_EN 0x08
#define | BIT_INT_SOURCE2_OIS1_AGC_RDY_INT1_EN 0x04
#define | BIT_INT_SOURCE2_OIS1_FSYNC_INT1_EN 0x02
#define | BIT_INT_SOURCE2_OIS1_DRDY_INT1_EN 0x01
#define | BIT_INT_SOURCE3_UI_FSYNC_INT2_EN 0x40
#define | BIT_INT_SOURCE3_PLL_RDY_INT2_EN 0x20
#define | BIT_INT_SOURCE3_RESET_DONE_INT2_EN 0x10
#define | BIT_INT_SOURCE3_UI_DRDY_INT2_EN 0x08
#define | BIT_INT_SOURCE3_FIFO_THS_INT2_EN 0x04
#define | BIT_INT_SOURCE3_FIFO_FULL_INT2_EN 0x02
#define | BIT_INT_SOURCE3_UI_AGC_RDY_INT2_EN 0x01
#define | BIT_INT_SOURCE4_SMD_INT2_EN 0x08
#define | BIT_INT_SOURCE4_WOM_Z_INT2_EN 0x04
#define | BIT_INT_SOURCE4_WOM_Y_INT2_EN 0x02
#define | BIT_INT_SOURCE4_WOM_X_INT2_EN 0x01
#define | BIT_INT_SOURCE5_OIS2_AGC_RDY_INT2_EN 0x20
#define | BIT_INT_SOURCE5_OIS2_FSYNC_INT2_EN 0x10
#define | BIT_INT_SOURCE5_OIS2_DRDY_INT2_EN 0x08
#define | BIT_INT_SOURCE5_OIS1_AGC_RDY_INT2_EN 0x04
#define | BIT_INT_SOURCE5_OIS1_FSYNC_INT2_EN 0x02
#define | BIT_INT_SOURCE5_OIS1_DRDY_INT2_EN 0x01
#define | BIT_ST_REGULATOR_EN 0x40
#define | BIT_ACCEL_Z_ST_EN 0x20
#define | BIT_ACCEL_Y_ST_EN 0x10
#define | BIT_ACCEL_X_ST_EN 0x08
#define | BIT_GYRO_Z_ST_EN 0x04
#define | BIT_GYRO_Y_ST_EN 0x02
#define | BIT_GYRO_X_ST_EN 0x01
#define | BIT_DMP_MEM_ACCESS_EN 0x08
#define | BIT_MEM_OTP_ACCESS_EN 0x04
#define | BIT_FIFO_MEM_RD_SYS 0x02
#define | BIT_FIFO_MEM_WR_SER 0x01
#define | BIT_SENSOR_CONFIG2_OIS_MODE_POS 4
#define | BIT_SENSOR_CONFIG2_OIS_MODE_MASK (0x03 << BIT_SENSOR_CONFIG2_OIS_MODE_POS)
#define | BIT_GYRO_AAF_DIS_POS 1
#define | BIT_GYRO_AAF_DIS_MASK (0x01 << BIT_GYRO_AAF_DIS_POS)
#define | BIT_GYRO_NF_DIS_POS 0
#define | BIT_GYRO_NF_DIS_MASK (0x01 << BIT_GYRO_NF_DIS_POS)
#define | BIT_GYRO_AAF_DELT_POS 0
#define | BIT_GYRO_AAF_DELT_MASK (0x3F << BIT_GYRO_AAF_DELT_POS)
#define | BIT_GYRO_AAF_DELTSQR_POS_LO 0
#define | BIT_GYRO_AAF_DELTSQR_MASK_LO (0xFF << BIT_GYRO_AAF_DELTSQR_POS_LO)
#define | BIT_GYRO_AAF_DELTSQR_POS_HI 0
#define | BIT_GYRO_AAF_DELTSQR_MASK_HI (0x0F << BIT_GYRO_AAF_DELTSQR_POS_HI)
#define | BIT_GYRO_AAF_BITSHIFT_POS 4
#define | BIT_GYRO_AAF_BITSHIFT_MASK (0x0F << BIT_GYRO_AAF_BITSHIFT_POS)
#define | BIT_INTF_CONFIG4_AP_SPI_POS 1
#define | BIT_INTF_CONFIG4_AP_SPI_MASK (0x1 << BIT_INTF_CONFIG4_AP_SPI_POS)
#define | BIT_INTF_CONFIG4_AUX1_SPI_POS 2
#define | BIT_INTF_CONFIG4_AUX1_SPI_MASK (0x1 << BIT_INTF_CONFIG4_AUX1_SPI_POS)
#define | BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS 1
#define | BIT_INTF_CONFIG5_GPIO_PAD_SEL_MASK (0x3 << BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS)
#define | BIT_INTF_CONFIG6_I3C_DDR_EN_POS 1
#define | BIT_INTF_CONFIG6_I3C_DDR_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_DDR_EN_POS)
#define | BIT_INTF_CONFIG6_I3C_SDR_EN_POS 0
#define | BIT_INTF_CONFIG6_I3C_SDR_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_SDR_EN_POS)
#define | BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS 3
#define | BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS)
#define | BIT_INTF_CONFIG6_I3C_IBI_EN_POS 2
#define | BIT_INTF_CONFIG6_I3C_IBI_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_IBI_EN_POS)
#define | BIT_ACCEL_AAF_DIS_POS 0
#define | BIT_ACCEL_AAF_DIS_MASK (0x01 << BIT_ACCEL_AAF_DIS_POS)
#define | BIT_ACCEL_AAF_DELT_POS 1
#define | BIT_ACCEL_AAF_DELT_MASK (0x3F << BIT_ACCEL_AAF_DELT_POS)
#define | BIT_ACCEL_AAF_DELTSQR_POS_LO 0
#define | BIT_ACCEL_AAF_DELTSQR_MASK_LO (0xFF << BIT_ACCEL_AAF_DELTSQR_POS_LO)
#define | BIT_ACCEL_AAF_DELTSQR_POS_HI 0
#define | BIT_ACCEL_AAF_DELTSQR_MASK_HI (0x0F << BIT_ACCEL_AAF_DELTSQR_POS_HI)
#define | BIT_ACCEL_AAF_BITSHIFT_POS 4
#define | BIT_ACCEL_AAF_BITSHIFT_MASK (0x0F << BIT_ACCEL_AAF_BITSHIFT_POS)
#define | BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS 5
#define | BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_MASK (0x1 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS)
#define | BIT_OIS1_CONFIG1_DEC_POS 2
#define | BIT_OIS1_CONFIG1_DEC_MASK (0x7 << BIT_OIS1_CONFIG1_DEC_POS)
#define | BIT_OIS1_CONFIG1_GYRO_EN_POS 1
#define | BIT_OIS1_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS1_CONFIG1_GYRO_EN_POS)
#define | BIT_OIS1_CONFIG1_ACCEL_EN_POS 0
#define | BIT_OIS1_CONFIG1_ACCEL_EN_MASK (0x1 << BIT_OIS1_CONFIG1_ACCEL_EN_POS)
#define | BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS 3
#define | BIT_OIS1_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS)
#define | BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS 0
#define | BIT_OIS1_CONFIG2_ACCEL_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS)
#define | BIT_INT_STATUS_OIS1_FSYNC 0x04
#define | BIT_INT_STATUS_OIS1_DRDY 0x02
#define | BIT_INT_STATUS_OIS1_AGC_RDY 0x01
#define | BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS 5
#define | BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_MASK (0x1 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS)
#define | BIT_OIS2_CONFIG1_DEC_POS 2
#define | BIT_OIS2_CONFIG1_DEC_MASK (0x7 << BIT_OIS2_CONFIG1_DEC_POS)
#define | BIT_OIS2_CONFIG1_GYRO_EN_POS 1
#define | BIT_OIS2_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS2_CONFIG1_GYRO_EN_POS)
#define | BIT_OIS2_CONFIG1_ACCEL_EN_POS 0
#define | BIT_OIS2_CONFIG1_ACCEL_EN_MASK (0x1 << BIT_OIS2_CONFIG1_ACCEL_EN_POS)
#define | BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS 3
#define | BIT_OIS2_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS)
#define | BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS 0
#define | BIT_OIS2_CONFIG2_ACCEL_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS)
#define | BIT_INT_STATUS_OIS2_FSYNC 0x04
#define | BIT_INT_STATUS_OIS2_DRDY 0x02
#define | BIT_INT_STATUS_OIS2_AGC_RDY 0x01
#define | BIT_FDR_CONFIG_FDR_SEL_POS 0
#define | BIT_FDR_CONFIG_FDR_SEL_MASK 0x7F
#define | BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_POS 0
#define | BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_MASK 0x0F
#define | BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS 4
#define | BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_MASK (0x0F << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS)
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1006632MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_30MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1174405MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_35MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1342177MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_40MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1509949MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_45MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1677721MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_50MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1845493MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_55MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2013265MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_60MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2181038MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_65MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2348810MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_70MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2516582MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_75MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2684354MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_80MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2852126MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_85MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3019898MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_90MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3187671MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_95MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3355443MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_100MG
#define | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3523215MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_105MG
#define | BIT_APEX_CONFIG2_PEDO_AMP_TH_POS 4
#define | BIT_APEX_CONFIG2_PEDO_AMP_TH_MASK (0x0F << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS)
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1006632_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_30MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1140850_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_34MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1275068_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_38MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1409286_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_42MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1543503_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_46MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1677721_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_50MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1811939_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_54MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1946157_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_58MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2080374_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_62MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2214592_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_66MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2348810_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_70MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2483027_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_74MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2617245_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_78MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2751463_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_82MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2885681_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_86MG
#define | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_3019898_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_90MG
#define | BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_POS 0
#define | BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_MASK 0x0F
#define | BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS 5
#define | BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_MASK (0x07 << BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS)
#define | BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS 2
#define | BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_MASK (0x07 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS)
#define | BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_POS 0
#define | BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_MASK 0x03
#define | BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS 6
#define | BIT_APEX_CONFIG4_TILT_WAIT_TIME_MASK (0x03 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS)
#define | BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS 3
#define | BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_MASK (0x07 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS)
#define | BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS 0
#define | BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_MASK (0x07 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS)
#define | BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS 0
#define | BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_MASK (0x07 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS)
#define | BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS 2
#define | BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_MASK (0x3F << BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS)
#define | ICM426XX_APEX_CONFIG7_TAP_MIN_JERK_THR_281MG_DEFAULT 0x11
#define | BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_POS 0
#define | BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_MASK 0x3
#define | BIT_APEX_CONFIG8_TAP_TMAX_POS 5
#define | BIT_APEX_CONFIG8_TAP_TMAX_MASK (0x03 << BIT_APEX_CONFIG8_TAP_TMAX_POS)
#define | BIT_APEX_CONFIG8_TAP_TAVG_POS 3
#define | BIT_APEX_CONFIG8_TAP_TAVG_MASK (0x03 << BIT_APEX_CONFIG8_TAP_TAVG_POS)
#define | BIT_APEX_CONFIG8_TAP_TMIN_POS 0
#define | BIT_APEX_CONFIG8_TAP_TMIN_MASK 0x07
#define | BIT_APEX_CONFIG9_SENSITIVITY_MODE_POS 0
#define | BIT_APEX_CONFIG9_SENSITIVITY_MODE_MASK 0x01
#define | BIT_INT_STEP_DET_INT_EN_POS 5
#define | BIT_INT_STEP_CNT_OVFL_INT_EN_POS 4
#define | BIT_INT_TILT_DET_INT_EN_POS 3
#define | BIT_INT_WAKE_DET_INT_EN_POS 2
#define | BIT_INT_SLEEP_DET_INT_EN_POS 1
#define | BIT_INT_TAP_DET_INT_EN_POS 0
#define | BIT_INT_SOURCE6_STEP_DET_INT1_EN 0x20
#define | BIT_INT_SOURCE6_STEP_CNT_OVFL_INT1_EN 0x10
#define | BIT_INT_SOURCE6_TILT_DET_INT1_EN 0x8
#define | BIT_INT_SOURCE6_WAKE_DET_INT1_EN 0x4
#define | BIT_INT_SOURCE6_SLEEP_DET_INT1_EN 0x2
#define | BIT_INT_SOURCE6_TAP_DET_INT1_EN 0x1
#define | BIT_INT_SOURCE7_STEP_DET_INT2_EN 0x20
#define | BIT_INT_SOURCE7_STEP_CNT_OVFL_INT2_EN 0x10
#define | BIT_INT_SOURCE7_TILT_DET_INT2_EN 0x8
#define | BIT_INT_SOURCE7_WAKE_DET_INT2_EN 0x4
#define | BIT_INT_SOURCE7_SLEEP_DET_INT2_EN 0x2
#define | BIT_INT_SOURCE7_TAP_DET_INT2_EN 0x1
#define | BIT_INT_OIS1_DRDY_IBI_EN_POS 6
#define | BIT_INT_UI_FSYNC_IBI_EN_POS 5
#define | BIT_INT_PLL_RDY_IBI_EN_POS 4
#define | BIT_INT_UI_DRDY_IBI_EN_POS 3
#define | BIT_INT_FIFO_THS_IBI_EN_POS 2
#define | BIT_INT_FIFO_FULL_IBI_EN_POS 1
#define | BIT_INT_UI_AGC_RDY_IBI_EN_POS 0
#define | BIT_INT_SOURCE8_OIS1_DRDY_IBI_EN 0x40
#define | BIT_INT_SOURCE8_UI_FSYNC_IBI_EN 0x20
#define | BIT_INT_SOURCE8_PLL_RDY_IBI_EN 0x10
#define | BIT_INT_SOURCE8_UI_DRDY_IBI_EN 0x08
#define | BIT_INT_SOURCE8_FIFO_THS_IBI_EN 0x04
#define | BIT_INT_SOURCE8_FIFO_FULL_IBI_EN 0x02
#define | BIT_INT_SOURCE8_UI_AGC_RDY_IBI_EN 0x01
#define | BIT_INT_SMD_IBI_EN_POS 4
#define | BIT_INT_WOM_Z_IBI_EN_POS 3
#define | BIT_INT_WOM_Y_IBI_EN_POS 2
#define | BIT_INT_WOM_X_IBI_EN_POS 1
#define | BIT_INT_SOURCE9_SMD_IBI_EN 0x10
#define | BIT_INT_SOURCE9_WOM_Z_IBI_EN 0x08
#define | BIT_INT_SOURCE9_WOM_Y_IBI_EN 0x04
#define | BIT_INT_SOURCE9_WOM_X_IBI_EN 0x02
#define | BIT_INT_STEP_DET_IBI_EN_POS 5
#define | BIT_INT_STEP_CNT_OVFL_IBI_EN_POS 4
#define | BIT_INT_TILT_DET_IBI_EN_POS 3
#define | BIT_INT_WAKE_DET_IBI_EN_POS 2
#define | BIT_INT_SLEEP_DET_IBI_EN_POS 1
#define | BIT_INT_TAP_DET_IBI_EN_POS 0
#define | BIT_INT_SOURCE10_STEP_DET_IBI_EN 0x20
#define | BIT_INT_SOURCE10_STEP_CNT_OVFL_IBI_EN 0x10
#define | BIT_INT_SOURCE10_TILT_DET_IBI_EN 0x08
#define | BIT_INT_SOURCE10_WAKE_DET_IBI_EN 0x04
#define | BIT_INT_SOURCE10_SLEEP_DET_IBI_EN 0x02
#define | BIT_INT_SOURCE10_TAP_DET_IBI_EN 0x01
#define | BIT_GYRO_X_OFFUSER_POS_LO 0
#define | BIT_GYRO_X_OFFUSER_MASK_LO (0xFF << BIT_GYRO_X_OFFUSER_POS_LO)
#define | BIT_GYRO_X_OFFUSER_POS_HI 0
#define | BIT_GYRO_X_OFFUSER_MASK_HI (0x0F << BIT_GYRO_X_OFFUSER_POS_HI)
#define | BIT_GYRO_Y_OFFUSER_POS_HI 4
#define | BIT_GYRO_Y_OFFUSER_MASK_HI (0x0F << BIT_GYRO_Y_OFFUSER_POS_HI)
#define | BIT_GYRO_Y_OFFUSER_POS_LO 0
#define | BIT_GYRO_Y_OFFUSER_MASK_LO (0xFF << BIT_GYRO_Y_OFFUSER_POS_LO)
#define | BIT_GYRO_Z_OFFUSER_POS_LO 0
#define | BIT_GYRO_Z_OFFUSER_MASK_LO (0xFF << BIT_GYRO_Z_OFFUSER_POS_LO)
#define | BIT_GYRO_Z_OFFUSER_POS_HI 0
#define | BIT_GYRO_Z_OFFUSER_MASK_HI (0x0F << BIT_GYRO_Z_OFFUSER_POS_HI)
#define | BIT_ACCEL_X_OFFUSER_POS_HI 4
#define | BIT_ACCEL_X_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_X_OFFUSER_POS_HI)
#define | BIT_ACCEL_X_OFFUSER_POS_LO 0
#define | BIT_ACCEL_X_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_X_OFFUSER_POS_LO)
#define | BIT_ACCEL_Y_OFFUSER_POS_LO 0
#define | BIT_ACCEL_Y_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_Y_OFFUSER_POS_LO)
#define | BIT_ACCEL_Y_OFFUSER_POS_HI 0
#define | BIT_ACCEL_Y_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_Y_OFFUSER_POS_HI)
#define | BIT_ACCEL_Z_OFFUSER_POS_HI 4
#define | BIT_ACCEL_Z_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_Z_OFFUSER_POS_HI)
#define | BIT_ACCEL_Z_OFFUSER_POS_LO 0
#define | BIT_ACCEL_Z_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_Z_OFFUSER_POS_LO)

## Enumerations
enum | ICM426XX_DEVICE_CONFIG_SPI_MODE_t { ICM426XX_DEVICE_CONFIG_SPI_MODE_1_2 = (0x1 << BIT_DEVICE_CONFIG_SPI_MODE_POS) , ICM426XX_DEVICE_CONFIG_SPI_MODE_0_3 = (0x0 << BIT_DEVICE_CONFIG_SPI_MODE_POS) }
enum | ICM426XX_CHIP_CONFIG_SPI_MODE_t { ICM426XX_CHIP_CONFIG_SPI_MODE_1_2 = (0x1 << BIT_CHIP_CONFIG_SPI_MODE_POS) , ICM426XX_CHIP_CONFIG_SPI_MODE_0_3 = (0x0 << BIT_CHIP_CONFIG_SPI_MODE_POS) }
enum | ICM426XX_DEVICE_CONFIG_RESET_t { ICM426XX_DEVICE_CONFIG_RESET_EN = 0x01 , ICM426XX_DEVICE_CONFIG_RESET_NONE = 0x00 }
enum | ICM426XX_CHIP_CONFIG_RESET_t { ICM426XX_CHIP_CONFIG_RESET_EN = 0x01 , ICM426XX_CHIP_CONFIG_RESET_NONE = 0x00 }
enum | ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_t { ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_PP = (0x01 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS) , ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_OD = (0x00 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS) }
enum | ICM426XX_INT_CONFIG_INT2_POLARITY_t { ICM426XX_INT_CONFIG_INT2_POLARITY_HIGH = (0x01 << BIT_INT_CONFIG_INT2_POLARITY_POS) , ICM426XX_INT_CONFIG_INT2_POLARITY_LOW = (0x00 << BIT_INT_CONFIG_INT2_POLARITY_POS) }
enum | ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t { ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_PP = (0x01 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS) , ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_OD = (0x00 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS) }
enum | ICM426XX_INT_CONFIG_INT1_POLARITY_t { ICM426XX_INT_CONFIG_INT1_POLARITY_HIGH = 0x01 , ICM426XX_INT_CONFIG_INT1_POLARITY_LOW = 0x00 }
enum | ICM426XX_FIFO_CONFIG_MODE_t { ICM426XX_FIFO_CONFIG_MODE_STOP_ON_FULL = (0x02 << BIT_FIFO_CONFIG_MODE_POS) , ICM426XX_FIFO_CONFIG_MODE_STREAM = (0x01 << BIT_FIFO_CONFIG_MODE_POS) , ICM426XX_FIFO_CONFIG_MODE_BYPASS = (0x00 << BIT_FIFO_CONFIG_MODE_POS) }
enum | ICM426XX_APEX_DATA3_ACTIVITY_CLASS_t { ICM426XX_APEX_DATA3_ACTIVITY_CLASS_OTHER = 0x0 , ICM426XX_APEX_DATA3_ACTIVITY_CLASS_WALK = 0x1 , ICM426XX_APEX_DATA3_ACTIVITY_CLASS_RUN = 0x2 }
enum | ICM426XX_APEX_DATA3_DMP_IDLE_OFF_t { ICM426XX_APEX_DATA3_DMP_IDLE_ON = (0x01 << BIT_APEX_DATA3_DMP_IDLE_POS) , ICM426XX_APEX_DATA3_DMP_IDLE_OFF = (0x00 << BIT_APEX_DATA3_DMP_IDLE_POS) }
enum | ICM426XX_APEX_DATA4_TAP_NUM_t { ICM426XX_APEX_DATA4_TAP_NUM_DOUBLE = (0x02 << BIT_APEX_DATA4_TAP_NUM_POS) , ICM426XX_APEX_DATA4_TAP_NUM_SINGLE = (0x01 << BIT_APEX_DATA4_TAP_NUM_POS) }
enum | ICM426XX_APEX_DATA4_TAP_AXIS_t { ICM426XX_APEX_DATA4_TAP_AXIS_Z = (0x02 << BIT_APEX_DATA4_TAP_AXIS_POS) , ICM426XX_APEX_DATA4_TAP_AXIS_Y = (0x01 << BIT_APEX_DATA4_TAP_AXIS_POS) , ICM426XX_APEX_DATA4_TAP_AXIS_X = (0x00 << BIT_APEX_DATA4_TAP_AXIS_POS) }
enum | ICM426XX_APEX_DATA4_TAP_DIR_t { ICM426XX_APEX_DATA4_TAP_DIR_POSITIVE = (0x01 << BIT_APEX_DATA4_TAP_DIR_POS) , ICM426XX_APEX_DATA4_TAP_DIR_NEGATIVE = (0x00 << BIT_APEX_DATA4_TAP_DIR_POS) }
enum | ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_t { ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_EN = (0x01 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS) , ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS) }
enum | ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_t { ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN = (0x01 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS) , ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_DIS }
enum | ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_t { ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_EN = (0x01 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS) , ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS) }
enum | ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_t { ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_EN = (0x01 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS) , ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS) }
enum | ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t { ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_DIS = (0x01 << BIT_FIFO_SREG_INVALID_IND_POS) , ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_EN = (0x00 << BIT_FIFO_SREG_INVALID_IND_POS) }
enum | ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_t { ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_RECORD = (0x01 << BIT_FIFO_COUNT_REC_POS) , ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_BYTE = (0x00 << BIT_FIFO_COUNT_REC_POS) }
enum | ICM426XX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t { ICM426XX_INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN = (0x01 << BIT_FIFO_COUNT_ENDIAN_POS) , ICM426XX_INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN = (0x00 << BIT_FIFO_COUNT_ENDIAN_POS) }
enum | ICM426XX_INTF_CONFIG0_DATA_ENDIAN_t { ICM426XX_INTF_CONFIG0_DATA_BIG_ENDIAN = (0x01 << BIT_DATA_ENDIAN_POS) , ICM426XX_INTF_CONFIG0_DATA_LITTLE_ENDIAN = (0x00 << BIT_DATA_ENDIAN_POS) }
enum | ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_t { ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_1_2 = (0x01 << BIT_SPI_MODE_OIS2_POS) , ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_0_3 = (0x00 << BIT_SPI_MODE_OIS2_POS) }
enum | ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_t { ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_1_2 = (0x01 << BIT_SPI_MODE_OIS1_POS) , ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_0_3 = (0x00 << BIT_SPI_MODE_OIS1_POS) }
enum | ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_t { ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_WUOSC = (0x00 << BIT_ACCEL_LP_CLK_SEL_POS) , ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_RCOSC = (0x01 << BIT_ACCEL_LP_CLK_SEL_POS) }
enum | ICM426XX_INTF_CONFIG1_RTC_MODE_t { ICM426XX_INTF_CONFIG1_RTC_MODE_DIS = (0x00 << BIT_RTC_MODE_POS) , ICM426XX_INTF_CONFIG1_RTC_MODE_EN = (0x01 << BIT_RTC_MODE_POS) }
enum | ICM426XX_PWR_MGMT_0_TEMP_t { ICM426XX_PWR_MGMT_0_TEMP_DIS = (0x01 << BIT_PWR_MGMT_0_TEMP_POS) , ICM426XX_PWR_MGMT_0_TEMP_EN = (0x00 << BIT_PWR_MGMT_0_TEMP_POS) }
enum | ICM426XX_PWR_MGMT_0_IDLE_t { ICM426XX_PWR_MGMT_0_IDLE_DIS = (0x01 << BIT_PWR_MGMT_0_IDLE_POS) , ICM426XX_PWR_MGMT_0_IDLE_EN = (0x00 << BIT_PWR_MGMT_0_IDLE_POS) }
enum | ICM426XX_PWR_MGMT_0_GYRO_MODE_t { ICM426XX_PWR_MGMT_0_GYRO_MODE_LN = (0x03 << BIT_PWR_MGMT_0_GYRO_MODE_POS) , ICM426XX_PWR_MGMT_0_GYRO_MODE_STANDBY = (0x01 << BIT_PWR_MGMT_0_GYRO_MODE_POS) , ICM426XX_PWR_MGMT_0_GYRO_MODE_OFF = (0x00 << BIT_PWR_MGMT_0_GYRO_MODE_POS) }
enum | ICM426XX_PWR_MGMT_0_ACCEL_MODE_t { ICM426XX_PWR_MGMT_0_ACCEL_MODE_LN = 0x03 , ICM426XX_PWR_MGMT_0_ACCEL_MODE_LP = 0x02 , ICM426XX_PWR_MGMT_0_ACCEL_MODE_OFF = 0x00 }
enum | ICM426XX_GYRO_CONFIG0_FS_SEL_t { ICM426XX_GYRO_CONFIG0_FS_SEL_16dps = (7 << BIT_GYRO_CONFIG0_FS_SEL_POS) , ICM426XX_GYRO_CONFIG0_FS_SEL_31dps = (6 << BIT_GYRO_CONFIG0_FS_SEL_POS) , ICM426XX_GYRO_CONFIG0_FS_SEL_62dps = (5 << BIT_GYRO_CONFIG0_FS_SEL_POS) , ICM426XX_GYRO_CONFIG0_FS_SEL_125dps = (4 << BIT_GYRO_CONFIG0_FS_SEL_POS) , ICM426XX_GYRO_CONFIG0_FS_SEL_250dps = (3 << BIT_GYRO_CONFIG0_FS_SEL_POS) , ICM426XX_GYRO_CONFIG0_FS_SEL_500dps = (2 << BIT_GYRO_CONFIG0_FS_SEL_POS) , ICM426XX_GYRO_CONFIG0_FS_SEL_1000dps = (1 << BIT_GYRO_CONFIG0_FS_SEL_POS) , ICM426XX_GYRO_CONFIG0_FS_SEL_2000dps = (0 << BIT_GYRO_CONFIG0_FS_SEL_POS) }
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enum | ICM426XX_GYRO_CONFIG0_ODR_t { ICM426XX_GYRO_CONFIG0_ODR_500_HZ = 0x0F , ICM426XX_GYRO_CONFIG0_ODR_12_5_HZ = 0x0B , ICM426XX_GYRO_CONFIG0_ODR_25_HZ = 0x0A , ICM426XX_GYRO_CONFIG0_ODR_50_HZ = 0x09 , ICM426XX_GYRO_CONFIG0_ODR_100_HZ = 0x08 , ICM426XX_GYRO_CONFIG0_ODR_200_HZ = 0x07 , ICM426XX_GYRO_CONFIG0_ODR_1_KHZ = 0x06 , ICM426XX_GYRO_CONFIG0_ODR_2_KHZ = 0x05 , ICM426XX_GYRO_CONFIG0_ODR_4_KHZ = 0x04 , ICM426XX_GYRO_CONFIG0_ODR_8_KHZ = 0x03 , ICM426XX_GYRO_CONFIG0_ODR_16_KHZ = 0x02 , ICM426XX_GYRO_CONFIG0_ODR_32_KHZ = 0x01 }
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enum | ICM426XX_ACCEL_CONFIG0_FS_SEL_t { ICM426XX_ACCEL_CONFIG0_FS_SEL_RESERVED = (0x4 << BIT_ACCEL_CONFIG0_FS_SEL_POS) , ICM426XX_ACCEL_CONFIG0_FS_SEL_2g = (0x3 << BIT_ACCEL_CONFIG0_FS_SEL_POS) , ICM426XX_ACCEL_CONFIG0_FS_SEL_4g = (0x2 << BIT_ACCEL_CONFIG0_FS_SEL_POS) , ICM426XX_ACCEL_CONFIG0_FS_SEL_8g = (0x1 << BIT_ACCEL_CONFIG0_FS_SEL_POS) , ICM426XX_ACCEL_CONFIG0_FS_SEL_16g = (0x0 << BIT_ACCEL_CONFIG0_FS_SEL_POS) }
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enum | ICM426XX_ACCEL_CONFIG0_ODR_t { ICM426XX_ACCEL_CONFIG0_ODR_500_HZ = 0xF , ICM426XX_ACCEL_CONFIG0_ODR_1_5625_HZ = 0xE , ICM426XX_ACCEL_CONFIG0_ODR_3_125_HZ = 0xD , ICM426XX_ACCEL_CONFIG0_ODR_6_25_HZ = 0xC , ICM426XX_ACCEL_CONFIG0_ODR_12_5_HZ = 0xB , ICM426XX_ACCEL_CONFIG0_ODR_25_HZ = 0xA , ICM426XX_ACCEL_CONFIG0_ODR_50_HZ = 0x9 , ICM426XX_ACCEL_CONFIG0_ODR_100_HZ = 0x8 , ICM426XX_ACCEL_CONFIG0_ODR_200_HZ = 0x7 , ICM426XX_ACCEL_CONFIG0_ODR_1_KHZ = 0x6 , ICM426XX_ACCEL_CONFIG0_ODR_2_KHZ = 0x5 , ICM426XX_ACCEL_CONFIG0_ODR_4_KHZ = 0x4 , ICM426XX_ACCEL_CONFIG0_ODR_8_KHZ = 0x3 , ICM426XX_ACCEL_CONFIG0_ODR_16_KHZ = 0x2 , ICM426XX_ACCEL_CONFIG0_ODR_32_KHZ = 0x1 }
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enum | ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_t { ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_1ST_ORDER , ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_2ND_ORDER , ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_3RD_ORDER }
enum | ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t { ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_40 = (0x7 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS) , ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_20 = (0x6 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS) , ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_16 = (0x5 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS) , ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_10 = (0x4 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS) , ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_8 = (0x3 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS) , ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_5 = (0x2 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS) , ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_4 = (0x1 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS) , ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_2 = (0x0 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS) }
enum | ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t { ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_16 = (0x6 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS) , ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_1 = (0x1 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS) }
enum | ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t { ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_40 = 0x07 , ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_20 = 0x06 , ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_16 = 0x05 , ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_10 = 0x04 , ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_8 = 0x03 , ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_5 = 0x02 , ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_4 = 0x01 , ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_2 = 0x00 }
enum | ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_t { ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_1ST_ORDER , ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_2ND_ORDER , ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_3RD_ORDER }
enum | ICM426XX_TMST_CONFIG_TMST_TO_REGS_EN_t { ICM426XX_TMST_CONFIG_TMST_TO_REGS_EN = (0x1 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS) , ICM426XX_TMST_CONFIG_TMST_TO_REGS_DIS = (0x0 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS) }
enum | ICM426XX_TMST_CONFIG_RESOL_t { ICM426XX_TMST_CONFIG_RESOL_16us = (0x01 << BIT_TMST_CONFIG_RESOL_POS) , ICM426XX_TMST_CONFIG_RESOL_1us = (0x00 << BIT_TMST_CONFIG_RESOL_POS) }
enum | ICM426XX_TMST_CONFIG_TMST_FSYNC_EN_t { ICM426XX_TMST_CONFIG_TMST_FSYNC_EN = (0x01 << BIT_TMST_CONFIG_TMST_FSYNC_POS) , ICM426XX_TMST_CONFIG_TMST_FSYNC_DIS = (0x00 << BIT_TMST_CONFIG_TMST_FSYNC_POS) }
enum | ICM426XX_TMST_CONFIG_TMST_EN_t { ICM426XX_TMST_CONFIG_TMST_EN = 0x01 , ICM426XX_TMST_CONFIG_TMST_DIS = 0x00 }
enum | ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_t { ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_EN = (0x1 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS) , ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_DIS = (0x0 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS) }
enum | ICM426XX_APEX_CONFIG0_TAP_ENABLE_t { ICM426XX_APEX_CONFIG0_TAP_ENABLE_EN = (0x1 << BIT_APEX_CONFIG0_TAP_ENABLE_POS) , ICM426XX_APEX_CONFIG0_TAP_ENABLE_DIS = (0x0 << BIT_APEX_CONFIG0_TAP_ENABLE_POS) }
enum | ICM426XX_APEX_CONFIG0_PEDO_EN_t { ICM426XX_APEX_CONFIG0_PEDO_EN_EN = (0x1 << BIT_APEX_CONFIG0_PEDO_EN_POS) , ICM426XX_APEX_CONFIG0_PEDO_EN_DIS = (0x0 << BIT_APEX_CONFIG0_PEDO_EN_POS) }
enum | ICM426XX_APEX_CONFIG0_R2W_EN_t { ICM426XX_APEX_CONFIG0_R2W_EN_EN = (0x1 << BIT_APEX_CONFIG0_R2W_EN_POS) , ICM426XX_APEX_CONFIG0_R2W_EN_DIS = (0x0 << BIT_APEX_CONFIG0_R2W_EN_POS) }
enum | ICM426XX_APEX_CONFIG0_TILT_EN_t { ICM426XX_APEX_CONFIG0_TILT_EN_EN = (0x1 << BIT_APEX_CONFIG0_TILT_EN_POS) , ICM426XX_APEX_CONFIG0_TILT_EN_DIS = (0x0 << BIT_APEX_CONFIG0_TILT_EN_POS) }
enum | ICM426XX_APEX_CONFIG0_DMP_ODR_t { ICM426XX_APEX_CONFIG0_DMP_ODR_25Hz = (0x0 << BIT_APEX_CONFIG0_DMP_ODR_POS) , ICM426XX_APEX_CONFIG0_DMP_ODR_50Hz = (0x2 << BIT_APEX_CONFIG0_DMP_ODR_POS) , ICM426XX_APEX_CONFIG0_DMP_ODR_100Hz , ICM426XX_APEX_CONFIG0_DMP_ODR_500Hz }
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enum | ICM426XX_SMD_CONFIG_WOM_INT_MODE_t { ICM426XX_SMD_CONFIG_WOM_INT_MODE_ANDED = (0x01 << BIT_SMD_CONFIG_WOM_INT_MODE_POS) , ICM426XX_SMD_CONFIG_WOM_INT_MODE_ORED = (0x00 << BIT_SMD_CONFIG_WOM_INT_MODE_POS) }
enum | ICM426XX_SMD_CONFIG_WOM_MODE_t { ICM426XX_SMD_CONFIG_WOM_MODE_CMP_PREV = (0x01 << BIT_SMD_CONFIG_WOM_MODE_POS) , ICM426XX_SMD_CONFIG_WOM_MODE_CMP_INIT = (0x00 << BIT_SMD_CONFIG_WOM_MODE_POS) }
enum | ICM426XX_SMD_CONFIG_SMD_MODE_t { ICM426XX_SMD_CONFIG_SMD_MODE_LONG = 0x03 , ICM426XX_SMD_CONFIG_SMD_MODE_SHORT = 0x02 , ICM426XX_SMD_CONFIG_SMD_MODE_WOM = 0x01 , ICM426XX_SMD_CONFIG_SMD_MODE_DISABLED = 0x00 }
enum | ICM426XX_FIFO_CONFIG1_WM_GT_t { ICM426XX_FIFO_CONFIG1_WM_GT_TH_EN = (0x1 << BIT_FIFO_CONFIG1_WM_GT_TH_POS) , ICM426XX_FIFO_CONFIG1_WM_GT_TH_DIS = (0x0 << BIT_FIFO_CONFIG1_WM_GT_TH_POS) }
enum | ICM426XX_FIFO_CONFIG1_HIRES_t { ICM426XX_FIFO_CONFIG1_HIRES_EN = (0x1 << BIT_FIFO_CONFIG1_HIRES_POS) , ICM426XX_FIFO_CONFIG1_HIRES_DIS = (0x0 << BIT_FIFO_CONFIG1_HIRES_POS) }
enum | ICM426XX_FIFO_CONFIG1_TMST_FSYNC_t { ICM426XX_FIFO_CONFIG1_TMST_FSYNC_EN = (0x1 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS) , ICM426XX_FIFO_CONFIG1_TMST_FSYNC_DIS = (0x0 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS) }
enum | ICM426XX_FIFO_CONFIG1_TEMP_t { ICM426XX_FIFO_CONFIG1_TEMP_EN = (0x1 << BIT_FIFO_CONFIG1_TEMP_POS) , ICM426XX_FIFO_CONFIG1_TEMP_DIS = (0x0 << BIT_FIFO_CONFIG1_TEMP_POS) }
enum | ICM426XX_FIFO_CONFIG1_GYRO_t { ICM426XX_FIFO_CONFIG1_GYRO_EN = (0x1 << BIT_FIFO_CONFIG1_GYRO_POS) , ICM426XX_FIFO_CONFIG1_GYRO_DIS = (0x0 << BIT_FIFO_CONFIG1_GYRO_POS) }
enum | ICM426XX_FIFO_CONFIG1_ACCEL_t { ICM426XX_FIFO_CONFIG1_ACCEL_EN = 0x01 , ICM426XX_FIFO_CONFIG1_ACCEL_DIS = 0x00 }
enum | ICM426XX_FSYNC_CONFIG_UI_SEL_t { ICM426XX_FSYNC_CONFIG_UI_SEL_NO = (0x0 << BIT_FSYNC_CONFIG_UI_SEL_POS) , ICM426XX_FSYNC_CONFIG_UI_SEL_TEMP = (0x1 << BIT_FSYNC_CONFIG_UI_SEL_POS) , ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_X = (0x2 << BIT_FSYNC_CONFIG_UI_SEL_POS) , ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_Y = (0x3 << BIT_FSYNC_CONFIG_UI_SEL_POS) , ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_Z = (0x4 << BIT_FSYNC_CONFIG_UI_SEL_POS) , ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_X = (0x5 << BIT_FSYNC_CONFIG_UI_SEL_POS) , ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_Y = (0x6 << BIT_FSYNC_CONFIG_UI_SEL_POS) , ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_Z = (0x7 << BIT_FSYNC_CONFIG_UI_SEL_POS) }
enum | ICM426XX_INT_TPULSE_DURATION_t { ICM426XX_INT_TPULSE_DURATION_8_US = (0x1 << BIT_INT_TPULSE_DURATION_POS) , ICM426XX_INT_TPULSE_DURATION_100_US = (0x0 << BIT_INT_TPULSE_DURATION_POS) }
enum | ICM426XX_INT_TDEASSERT_t { ICM426XX_INT_TDEASSERT_DISABLED = (0x1 << BIT_INT_TDEASSERT_POS) , ICM426XX_INT_TDEASSERT_ENABLED = (0x0 << BIT_INT_TDEASSERT_POS) }
enum | ICM426XX_INT_CONFIG1_ASY_RST_t { ICM426XX_INT_CONFIG1_ASY_RST_DISABLED = (0x1 << BIT_INT_CONFIG1_ASY_RST_POS) , ICM426XX_INT_CONFIG1_ASY_RST_ENABLED = (0x0 << BIT_INT_CONFIG1_ASY_RST_POS) }
enum | ICM426XX_SENSOR_CONFIG2_OIS_MODE_t { ICM426XX_SENSOR_CONFIG2_OIS_MODE_32KHZ = (0x2 << BIT_SENSOR_CONFIG2_OIS_MODE_POS) , ICM426XX_SENSOR_CONFIG2_OIS_MODE_8KHZ = (0x1 << BIT_SENSOR_CONFIG2_OIS_MODE_POS) , ICM426XX_SENSOR_CONFIG2_OIS_MODE_DIS = (0x0 << BIT_SENSOR_CONFIG2_OIS_MODE_POS) }
enum | ICM426XX_GYRO_AAF_DIS_t { ICM426XX_GYRO_AAF_EN = (0x0 << BIT_GYRO_AAF_DIS_POS) , ICM426XX_GYRO_AAF_DIS = (0x1 << BIT_GYRO_AAF_DIS_POS) }
enum | ICM426XX_GYRO_NF_DIS_t { ICM426XX_GYRO_NF_EN = (0x0 << BIT_GYRO_NF_DIS_POS) , ICM426XX_GYRO_NF_DIS = (0x1 << BIT_GYRO_NF_DIS_POS) }
enum | ICM426XX_INTF_CONFIG4_AP_SPI_t { ICM426XX_INTF_CONFIG4_AP_SPI4W = (0x1 << BIT_INTF_CONFIG4_AP_SPI_POS) , ICM426XX_INTF_CONFIG4_AP_SPI3W = (0x0 << BIT_INTF_CONFIG4_AP_SPI_POS) }
enum | ICM426XX_INTF_CONFIG4_AUX1_SPI_t { ICM426XX_INTF_CONFIG4_AUX1_SPI4W = (0x1 << BIT_INTF_CONFIG4_AUX1_SPI_POS) , ICM426XX_INTF_CONFIG4_AUX1_SPI3W = (0x0 << BIT_INTF_CONFIG4_AUX1_SPI_POS) }
enum | ICM426XX_ACCEL_AAF_DIS_t { ICM426XX_ACCEL_AAF_EN = (0x0 << BIT_ACCEL_AAF_DIS_POS) , ICM426XX_ACCEL_AAF_DIS = (0x1 << BIT_ACCEL_AAF_DIS_POS) }
enum | ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_t { ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC = (0x0 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS) , ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC = (0x1 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS) }
enum | ICM426XX_OIS1_CONFIG1_DEC_t { ICM426XX_OIS1_CONFIG1_DEC_1 = (0x0 << BIT_OIS1_CONFIG1_DEC_POS) , ICM426XX_OIS1_CONFIG1_DEC_2 = (0x1 << BIT_OIS1_CONFIG1_DEC_POS) , ICM426XX_OIS1_CONFIG1_DEC_4 = (0x2 << BIT_OIS1_CONFIG1_DEC_POS) , ICM426XX_OIS1_CONFIG1_DEC_8 = (0x3 << BIT_OIS1_CONFIG1_DEC_POS) , ICM426XX_OIS1_CONFIG1_DEC_16 = (0x4 << BIT_OIS1_CONFIG1_DEC_POS) , ICM426XX_OIS1_CONFIG1_DEC_32 = (0x5 << BIT_OIS1_CONFIG1_DEC_POS) }
| OIS1 rate selection (base clock fixed by OTP divided by decimator value) More...
enum | ICM426XX_OIS1_CONFIG1_GYRO_EN_t { ICM426XX_OIS1_CONFIG1_GYRO_EN = (0x1 << BIT_OIS1_CONFIG1_GYRO_EN_POS) , ICM426XX_OIS1_CONFIG1_GYRO_DIS = (0x0 << BIT_OIS1_CONFIG1_GYRO_EN_POS) }
enum | ICM426XX_OIS1_CONFIG1_ACCEL_EN_t { ICM426XX_OIS1_CONFIG1_ACCEL_EN = (0x1 << BIT_OIS1_CONFIG1_ACCEL_EN_POS) , ICM426XX_OIS1_CONFIG1_ACCEL_DIS = (0x0 << BIT_OIS1_CONFIG1_ACCEL_EN_POS) }
enum | ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_t { ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_16dps , ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_31dps , ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_62dps , ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_125dps , ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_250dps , ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_500dps , ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_1000dps , ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_2000dps }
| OIS1 gyroscope FSR selection. More...
enum | ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_t { ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_RESERVED = (0x4 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS) , ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_2g = (0x3 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS) , ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_4g = (0x2 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS) , ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_8g = (0x1 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS) , ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_16g = (0x0 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS) }
| OIS1 accelerometer FSR selection. More...
enum | ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_t { ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC = (0x0 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS) , ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC = (0x1 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS) }
enum | ICM426XX_OIS2_CONFIG1_DEC_t { ICM426XX_OIS2_CONFIG1_DEC_1 = (0x0 << BIT_OIS2_CONFIG1_DEC_POS) , ICM426XX_OIS2_CONFIG1_DEC_2 = (0x1 << BIT_OIS2_CONFIG1_DEC_POS) , ICM426XX_OIS2_CONFIG1_DEC_4 = (0x2 << BIT_OIS2_CONFIG1_DEC_POS) , ICM426XX_OIS2_CONFIG1_DEC_8 = (0x3 << BIT_OIS2_CONFIG1_DEC_POS) , ICM426XX_OIS2_CONFIG1_DEC_16 = (0x4 << BIT_OIS2_CONFIG1_DEC_POS) , ICM426XX_OIS2_CONFIG1_DEC_32 = (0x5 << BIT_OIS2_CONFIG1_DEC_POS) }
| OIS2 rate selection (base clock fixed by OTP divided by decimator value) More...
enum | ICM426XX_OIS2_CONFIG1_GYRO_EN_t { ICM426XX_OIS2_CONFIG1_GYRO_EN = (0x1 << BIT_OIS2_CONFIG1_GYRO_EN_POS) , ICM426XX_OIS2_CONFIG1_GYRO_DIS = (0x0 << BIT_OIS2_CONFIG1_GYRO_EN_POS) }
enum | ICM426XX_OIS2_CONFIG1_ACCEL_EN_t { ICM426XX_OIS2_CONFIG1_ACCEL_EN = (0x1 << BIT_OIS2_CONFIG1_ACCEL_EN_POS) , ICM426XX_OIS2_CONFIG1_ACCEL_DIS = (0x0 << BIT_OIS2_CONFIG1_ACCEL_EN_POS) }
enum | ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_t { ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_16dps , ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_31dps , ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_62dps , ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_125dps , ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_250dps , ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_500dps , ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_1000dps , ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_2000dps }
| OIS2 gyroscope FSR selection. More...
enum | ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_t { ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_RESERVED = (0x4 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS) , ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_2g = (0x3 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS) , ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_4g = (0x2 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS) , ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_8g = (0x1 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS) , ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_16g = (0x0 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS) }
| OIS2 accelerometer FSR selection. More...
enum | ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t { ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_0S = 0x0 , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_4S = 0x1 , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_8S = 0x2 , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_12S = 0x3 , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_16S = 0x4 , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_20S = 0x5 , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_24S = 0x6 , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_28S = 0x7 , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_32S = 0x8 , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_36S = 0x9 , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_40S = 0xA , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_44S = 0xB , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_48S = 0xC , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_52S = 0xD , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_56S = 0xE , ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_60S = 0xF }
enum | ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t { ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_30MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_35MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_40MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_45MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_50MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_55MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_60MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_65MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_70MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_75MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_80MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_85MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_90MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_95MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_100MG , ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_105MG }
enum | ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_t { ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_30MG = (0 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_34MG = (1 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_38MG = (2 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_42MG = (3 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_46MG = (4 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_50MG = (5 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_54MG = (6 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_58MG = (7 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_62MG = (8 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_66MG = (9 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_70MG = (10 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_74MG = (11 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_78MG = (12 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_82MG = (13 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_86MG = (14 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) , ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_90MG = (15 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) }
enum | ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t { ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_50_SAMPLES , ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_75_SAMPLES , ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_100_SAMPLES , ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_125_SAMPLES , ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_150_SAMPLES , ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_175_SAMPLES , ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_200_SAMPLES , ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_225_SAMPLES }
enum | ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t { ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_90 = 0x0 , ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_107 = 0x1 , ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_136 = 0x2 , ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_159 = 0x3 }
enum | ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_t { ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_0S = (0 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS) , ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_2S = (1 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS) , ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_4S = (2 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS) , ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_6S = (3 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS) }
enum | ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t { ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_1_28S = (0 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS) , ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_2_56S = (1 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS) , ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_3_84S = (2 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS) , ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_5_12S = (3 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS) , ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_6_4S = (4 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS) , ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_7_68S = (5 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS) , ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_8_96S = (6 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS) , ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_10_24S = (7 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS) }
enum | ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t { ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_0 = (0 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS) , ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_1 = (1 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS) , ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_2 = (2 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS) , ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_3 = (3 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS) , ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_4 = (4 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS) , ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_5 = (5 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS) , ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_6 = (6 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS) , ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_7 = (7 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS) }
enum | ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t { ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_32S , ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_64S , ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_96S , ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_28S , ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_6S , ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_92S , ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_24S , ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_56S }
enum | ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t { ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_12 = 0x0 , ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_25 = 0x1 , ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_37 = 0x2 , ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_50 = 0x3 }
enum | ICM426XX_APEX_CONFIG8_TAP_TMAX_t { ICM426XX_APEX_CONFIG8_TAP_TMAX_250MS = (0 << BIT_APEX_CONFIG8_TAP_TMAX_POS) , ICM426XX_APEX_CONFIG8_TAP_TMAX_375MS = (1 << BIT_APEX_CONFIG8_TAP_TMAX_POS) , ICM426XX_APEX_CONFIG8_TAP_TMAX_500MS = (2 << BIT_APEX_CONFIG8_TAP_TMAX_POS) , ICM426XX_APEX_CONFIG8_TAP_TMAX_625MS = (3 << BIT_APEX_CONFIG8_TAP_TMAX_POS) }
enum | ICM426XX_APEX_CONFIG8_TAP_TAVG_t { ICM426XX_APEX_CONFIG8_TAP_TAVG_1SAMPLE = (0 << BIT_APEX_CONFIG8_TAP_TAVG_POS) , ICM426XX_APEX_CONFIG8_TAP_TAVG_2SAMPLE = (1 << BIT_APEX_CONFIG8_TAP_TAVG_POS) , ICM426XX_APEX_CONFIG8_TAP_TAVG_4SAMPLE = (2 << BIT_APEX_CONFIG8_TAP_TAVG_POS) , ICM426XX_APEX_CONFIG8_TAP_TAVG_8SAMPLE = (3 << BIT_APEX_CONFIG8_TAP_TAVG_POS) }
enum | ICM426XX_APEX_CONFIG8_TAP_TMIN_t { ICM426XX_APEX_CONFIG8_TAP_TMIN_125MS = 0x0 , ICM426XX_APEX_CONFIG8_TAP_TMIN_140MS = 0x1 , ICM426XX_APEX_CONFIG8_TAP_TMIN_156MS = 0x2 , ICM426XX_APEX_CONFIG8_TAP_TMIN_171MS = 0x3 , ICM426XX_APEX_CONFIG8_TAP_TMIN_187MS = 0x4 , ICM426XX_APEX_CONFIG8_TAP_TMIN_203MS = 0x5 , ICM426XX_APEX_CONFIG8_TAP_TMIN_218MS = 0x6 , ICM426XX_APEX_CONFIG8_TAP_TMIN_234MS = 0x7 }
enum | ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_t { ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_NORMAL = 0x00 , ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_RESERVED = 0x01 }

## Detailed Description

File exposing the device register map.

## Macro Definition Documentation

## ◆ ACCEL_DATA_SIZE

#define ACCEL_DATA_SIZE 6

## ◆ BIT_ACCEL_AAF_BITSHIFT_MASK

#define BIT_ACCEL_AAF_BITSHIFT_MASK (0x0F << BIT_ACCEL_AAF_BITSHIFT_POS)

## ◆ BIT_ACCEL_AAF_BITSHIFT_POS

#define BIT_ACCEL_AAF_BITSHIFT_POS 4

## ◆ BIT_ACCEL_AAF_DELT_MASK

#define BIT_ACCEL_AAF_DELT_MASK (0x3F << BIT_ACCEL_AAF_DELT_POS)

## ◆ BIT_ACCEL_AAF_DELT_POS

#define BIT_ACCEL_AAF_DELT_POS 1

## ◆ BIT_ACCEL_AAF_DELTSQR_MASK_HI

#define BIT_ACCEL_AAF_DELTSQR_MASK_HI (0x0F << BIT_ACCEL_AAF_DELTSQR_POS_HI)

## ◆ BIT_ACCEL_AAF_DELTSQR_MASK_LO

#define BIT_ACCEL_AAF_DELTSQR_MASK_LO (0xFF << BIT_ACCEL_AAF_DELTSQR_POS_LO)

## ◆ BIT_ACCEL_AAF_DELTSQR_POS_HI

#define BIT_ACCEL_AAF_DELTSQR_POS_HI 0

## ◆ BIT_ACCEL_AAF_DELTSQR_POS_LO

#define BIT_ACCEL_AAF_DELTSQR_POS_LO 0

## ◆ BIT_ACCEL_AAF_DIS_MASK

#define BIT_ACCEL_AAF_DIS_MASK (0x01 << BIT_ACCEL_AAF_DIS_POS)

## ◆ BIT_ACCEL_AAF_DIS_POS

#define BIT_ACCEL_AAF_DIS_POS 0

## ◆ BIT_ACCEL_CONFIG0_FS_SEL_MASK

#define BIT_ACCEL_CONFIG0_FS_SEL_MASK (0x7 << BIT_ACCEL_CONFIG0_FS_SEL_POS)

## ◆ BIT_ACCEL_CONFIG0_FS_SEL_POS

#define BIT_ACCEL_CONFIG0_FS_SEL_POS 5

## ◆ BIT_ACCEL_CONFIG0_ODR_MASK

#define BIT_ACCEL_CONFIG0_ODR_MASK 0x0F

## ◆ BIT_ACCEL_CONFIG0_ODR_POS

#define BIT_ACCEL_CONFIG0_ODR_POS 0

## ◆ BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_MASK

#define BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS)

## ◆ BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS

#define BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS 1

## ◆ BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_MASK

#define BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS)

## ◆ BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS

#define BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS 3

## ◆ BIT_ACCEL_LP_CLK_SEL_MASK

#define BIT_ACCEL_LP_CLK_SEL_MASK (0x01 << BIT_ACCEL_LP_CLK_SEL_POS)

## ◆ BIT_ACCEL_LP_CLK_SEL_POS

#define BIT_ACCEL_LP_CLK_SEL_POS 3

## ◆ BIT_ACCEL_X_OFFUSER_MASK_HI

#define BIT_ACCEL_X_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_X_OFFUSER_POS_HI)

## ◆ BIT_ACCEL_X_OFFUSER_MASK_LO

#define BIT_ACCEL_X_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_X_OFFUSER_POS_LO)

## ◆ BIT_ACCEL_X_OFFUSER_POS_HI

#define BIT_ACCEL_X_OFFUSER_POS_HI 4

## ◆ BIT_ACCEL_X_OFFUSER_POS_LO

#define BIT_ACCEL_X_OFFUSER_POS_LO 0

## ◆ BIT_ACCEL_X_ST_EN

#define BIT_ACCEL_X_ST_EN 0x08

## ◆ BIT_ACCEL_Y_OFFUSER_MASK_HI

#define BIT_ACCEL_Y_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_Y_OFFUSER_POS_HI)

## ◆ BIT_ACCEL_Y_OFFUSER_MASK_LO

#define BIT_ACCEL_Y_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_Y_OFFUSER_POS_LO)

## ◆ BIT_ACCEL_Y_OFFUSER_POS_HI

#define BIT_ACCEL_Y_OFFUSER_POS_HI 0

## ◆ BIT_ACCEL_Y_OFFUSER_POS_LO

#define BIT_ACCEL_Y_OFFUSER_POS_LO 0

## ◆ BIT_ACCEL_Y_ST_EN

#define BIT_ACCEL_Y_ST_EN 0x10

## ◆ BIT_ACCEL_Z_OFFUSER_MASK_HI

#define BIT_ACCEL_Z_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_Z_OFFUSER_POS_HI)

## ◆ BIT_ACCEL_Z_OFFUSER_MASK_LO

#define BIT_ACCEL_Z_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_Z_OFFUSER_POS_LO)

## ◆ BIT_ACCEL_Z_OFFUSER_POS_HI

#define BIT_ACCEL_Z_OFFUSER_POS_HI 4

## ◆ BIT_ACCEL_Z_OFFUSER_POS_LO

#define BIT_ACCEL_Z_OFFUSER_POS_LO 0

## ◆ BIT_ACCEL_Z_ST_EN

#define BIT_ACCEL_Z_ST_EN 0x20

## ◆ BIT_APEX_CONFIG0_DMP_ODR_MASK

#define BIT_APEX_CONFIG0_DMP_ODR_MASK (0x3 << BIT_APEX_CONFIG0_DMP_ODR_POS)

## ◆ BIT_APEX_CONFIG0_DMP_ODR_POS

#define BIT_APEX_CONFIG0_DMP_ODR_POS 0

## ◆ BIT_APEX_CONFIG0_DMP_POWER_SAVE_MASK

#define BIT_APEX_CONFIG0_DMP_POWER_SAVE_MASK (0x1 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS)

## ◆ BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS

#define BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS 7

## ◆ BIT_APEX_CONFIG0_PEDO_EN_MASK

#define BIT_APEX_CONFIG0_PEDO_EN_MASK (0x1 << BIT_APEX_CONFIG0_PEDO_EN_POS)

## ◆ BIT_APEX_CONFIG0_PEDO_EN_POS

#define BIT_APEX_CONFIG0_PEDO_EN_POS 5

## ◆ BIT_APEX_CONFIG0_R2W_EN_MASK

#define BIT_APEX_CONFIG0_R2W_EN_MASK (0x1 << BIT_APEX_CONFIG0_R2W_EN_POS)

## ◆ BIT_APEX_CONFIG0_R2W_EN_POS

#define BIT_APEX_CONFIG0_R2W_EN_POS 3

## ◆ BIT_APEX_CONFIG0_TAP_ENABLE_MASK

#define BIT_APEX_CONFIG0_TAP_ENABLE_MASK (0x1 << BIT_APEX_CONFIG0_TAP_ENABLE_POS)

## ◆ BIT_APEX_CONFIG0_TAP_ENABLE_POS

#define BIT_APEX_CONFIG0_TAP_ENABLE_POS 6

## ◆ BIT_APEX_CONFIG0_TILT_EN_MASK

#define BIT_APEX_CONFIG0_TILT_EN_MASK (0x1 << BIT_APEX_CONFIG0_TILT_EN_POS)

## ◆ BIT_APEX_CONFIG0_TILT_EN_POS

#define BIT_APEX_CONFIG0_TILT_EN_POS 4

## ◆ BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_MASK

#define BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_MASK 0x0F

## ◆ BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_POS

#define BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_POS 0

## ◆ BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_MASK

#define BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_MASK (0x0F << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS)

## ◆ BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS

#define BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS 4

## ◆ BIT_APEX_CONFIG2_PEDO_AMP_TH_MASK

#define BIT_APEX_CONFIG2_PEDO_AMP_TH_MASK (0x0F << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS)

## ◆ BIT_APEX_CONFIG2_PEDO_AMP_TH_POS

#define BIT_APEX_CONFIG2_PEDO_AMP_TH_POS 4

## ◆ BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_MASK

#define BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_MASK 0x0F

## ◆ BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_POS

#define BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_POS 0

## ◆ BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_MASK

#define BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_MASK 0x03

## ◆ BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_POS

#define BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_POS 0

## ◆ BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_MASK

#define BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_MASK (0x07 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS)

## ◆ BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS

#define BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS 2

## ◆ BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_MASK

#define BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_MASK (0x07 << BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS)

## ◆ BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS

#define BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS 5

## ◆ BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_MASK

#define BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_MASK (0x07 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS)

## ◆ BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS

#define BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS 3

## ◆ BIT_APEX_CONFIG4_TILT_WAIT_TIME_MASK

#define BIT_APEX_CONFIG4_TILT_WAIT_TIME_MASK (0x03 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS)

## ◆ BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS

#define BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS 6

## ◆ BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_MASK

#define BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_MASK (0x07 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS)

## ◆ BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS

#define BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS 0

## ◆ BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_MASK

#define BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_MASK (0x07 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS)

## ◆ BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS

#define BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS 0

## ◆ BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_MASK

#define BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_MASK 0x3

## ◆ BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_POS

#define BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_POS 0

## ◆ BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_MASK

#define BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_MASK (0x3F << BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS)

## ◆ BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS

#define BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS 2

## ◆ BIT_APEX_CONFIG8_TAP_TAVG_MASK

#define BIT_APEX_CONFIG8_TAP_TAVG_MASK (0x03 << BIT_APEX_CONFIG8_TAP_TAVG_POS)

## ◆ BIT_APEX_CONFIG8_TAP_TAVG_POS

#define BIT_APEX_CONFIG8_TAP_TAVG_POS 3

## ◆ BIT_APEX_CONFIG8_TAP_TMAX_MASK

#define BIT_APEX_CONFIG8_TAP_TMAX_MASK (0x03 << BIT_APEX_CONFIG8_TAP_TMAX_POS)

## ◆ BIT_APEX_CONFIG8_TAP_TMAX_POS

#define BIT_APEX_CONFIG8_TAP_TMAX_POS 5

## ◆ BIT_APEX_CONFIG8_TAP_TMIN_MASK

#define BIT_APEX_CONFIG8_TAP_TMIN_MASK 0x07

## ◆ BIT_APEX_CONFIG8_TAP_TMIN_POS

#define BIT_APEX_CONFIG8_TAP_TMIN_POS 0

## ◆ BIT_APEX_CONFIG9_SENSITIVITY_MODE_MASK

#define BIT_APEX_CONFIG9_SENSITIVITY_MODE_MASK 0x01

## ◆ BIT_APEX_CONFIG9_SENSITIVITY_MODE_POS

#define BIT_APEX_CONFIG9_SENSITIVITY_MODE_POS 0

## ◆ BIT_APEX_DATA3_ACTIVITY_CLASS_MASK

#define BIT_APEX_DATA3_ACTIVITY_CLASS_MASK 0x03

## ◆ BIT_APEX_DATA3_ACTIVITY_CLASS_POS

#define BIT_APEX_DATA3_ACTIVITY_CLASS_POS 0

## ◆ BIT_APEX_DATA3_DMP_IDLE_MASK

#define BIT_APEX_DATA3_DMP_IDLE_MASK (0x01 << BIT_APEX_DATA3_DMP_IDLE_POS)

## ◆ BIT_APEX_DATA3_DMP_IDLE_POS

#define BIT_APEX_DATA3_DMP_IDLE_POS 2

## ◆ BIT_APEX_DATA4_TAP_AXIS_MASK

#define BIT_APEX_DATA4_TAP_AXIS_MASK (0x03 << BIT_APEX_DATA4_TAP_AXIS_POS)

## ◆ BIT_APEX_DATA4_TAP_AXIS_POS

#define BIT_APEX_DATA4_TAP_AXIS_POS 1

## ◆ BIT_APEX_DATA4_TAP_DIR_MASK

#define BIT_APEX_DATA4_TAP_DIR_MASK 0x01

## ◆ BIT_APEX_DATA4_TAP_DIR_POS

#define BIT_APEX_DATA4_TAP_DIR_POS 0

## ◆ BIT_APEX_DATA4_TAP_NUM_MASK

#define BIT_APEX_DATA4_TAP_NUM_MASK (0x03 << BIT_APEX_DATA4_TAP_NUM_POS)

## ◆ BIT_APEX_DATA4_TAP_NUM_POS

#define BIT_APEX_DATA4_TAP_NUM_POS 3

TAP status flags: non-zero value - tap detected bit0 - positive or negative edge bit1 and 2 - axis detected : 0-X ; 1-Y ; 2-Z bit3 and 4 - tap type : 1-single ; 2 -double.

## ◆ BIT_APEX_DATA5_DOUBLE_TAP_TIMING_MASK

#define BIT_APEX_DATA5_DOUBLE_TAP_TIMING_MASK (0x3F << BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS)

## ◆ BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS

#define BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS 0

## ◆ BIT_CHIP_CONFIG_RESET_MASK

#define BIT_CHIP_CONFIG_RESET_MASK BIT_DEVICE_CONFIG_RESET_MASK

## ◆ BIT_CHIP_CONFIG_RESET_POS

#define BIT_CHIP_CONFIG_RESET_POS BIT_DEVICE_CONFIG_RESET_POS

## ◆ BIT_CHIP_CONFIG_SPI_MODE_MASK

#define BIT_CHIP_CONFIG_SPI_MODE_MASK BIT_DEVICE_CONFIG_SPI_MODE_MASK

## ◆ BIT_CHIP_CONFIG_SPI_MODE_POS

#define BIT_CHIP_CONFIG_SPI_MODE_POS BIT_DEVICE_CONFIG_SPI_MODE_POS

## ◆ BIT_DATA_ENDIAN_MASK

#define BIT_DATA_ENDIAN_MASK (0x01 << BIT_DATA_ENDIAN_POS)

## ◆ BIT_DATA_ENDIAN_POS

#define BIT_DATA_ENDIAN_POS 4

## ◆ BIT_DEVICE_CONFIG_RESET_MASK

#define BIT_DEVICE_CONFIG_RESET_MASK 0x01

## ◆ BIT_DEVICE_CONFIG_RESET_POS

#define BIT_DEVICE_CONFIG_RESET_POS 0

## ◆ BIT_DEVICE_CONFIG_SPI_MODE_MASK

#define BIT_DEVICE_CONFIG_SPI_MODE_MASK (0x1 << BIT_DEVICE_CONFIG_SPI_MODE_POS)

## ◆ BIT_DEVICE_CONFIG_SPI_MODE_POS

#define BIT_DEVICE_CONFIG_SPI_MODE_POS 4

## ◆ BIT_DMP_MEM_ACCESS_EN

#define BIT_DMP_MEM_ACCESS_EN 0x08

## ◆ BIT_FDR_CONFIG_FDR_SEL_MASK

#define BIT_FDR_CONFIG_FDR_SEL_MASK 0x7F

## ◆ BIT_FDR_CONFIG_FDR_SEL_POS

#define BIT_FDR_CONFIG_FDR_SEL_POS 0

## ◆ BIT_FIFO_CONFIG1_ACCEL_MASK

#define BIT_FIFO_CONFIG1_ACCEL_MASK 0x1

## ◆ BIT_FIFO_CONFIG1_ACCEL_POS

#define BIT_FIFO_CONFIG1_ACCEL_POS 0

## ◆ BIT_FIFO_CONFIG1_GYRO_MASK

#define BIT_FIFO_CONFIG1_GYRO_MASK (0x1 << BIT_FIFO_CONFIG1_GYRO_POS)

## ◆ BIT_FIFO_CONFIG1_GYRO_POS

#define BIT_FIFO_CONFIG1_GYRO_POS 1

## ◆ BIT_FIFO_CONFIG1_HIRES_MASK

#define BIT_FIFO_CONFIG1_HIRES_MASK (0x1 << BIT_FIFO_CONFIG1_HIRES_POS)

## ◆ BIT_FIFO_CONFIG1_HIRES_POS

#define BIT_FIFO_CONFIG1_HIRES_POS 4

## ◆ BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_MASK

#define BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_MASK (0x1 << BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS)

## ◆ BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS

#define BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS 6

## ◆ BIT_FIFO_CONFIG1_TEMP_MASK

#define BIT_FIFO_CONFIG1_TEMP_MASK (0x1 << BIT_FIFO_CONFIG1_TEMP_POS)

## ◆ BIT_FIFO_CONFIG1_TEMP_POS

#define BIT_FIFO_CONFIG1_TEMP_POS 2

## ◆ BIT_FIFO_CONFIG1_TMST_FSYNC_MASK

#define BIT_FIFO_CONFIG1_TMST_FSYNC_MASK (0x1 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS)

## ◆ BIT_FIFO_CONFIG1_TMST_FSYNC_POS

#define BIT_FIFO_CONFIG1_TMST_FSYNC_POS 3

## ◆ BIT_FIFO_CONFIG1_WM_GT_TH_MASK

#define BIT_FIFO_CONFIG1_WM_GT_TH_MASK (0x1 << BIT_FIFO_CONFIG1_WM_GT_TH_POS)

## ◆ BIT_FIFO_CONFIG1_WM_GT_TH_POS

#define BIT_FIFO_CONFIG1_WM_GT_TH_POS 5

## ◆ BIT_FIFO_CONFIG_MODE_MASK

#define BIT_FIFO_CONFIG_MODE_MASK (0x03 << BIT_FIFO_CONFIG_MODE_POS)

## ◆ BIT_FIFO_CONFIG_MODE_POS

#define BIT_FIFO_CONFIG_MODE_POS 6

## ◆ BIT_FIFO_COUNT_ENDIAN_MASK

#define BIT_FIFO_COUNT_ENDIAN_MASK (0x01 << BIT_FIFO_COUNT_ENDIAN_POS)

## ◆ BIT_FIFO_COUNT_ENDIAN_POS

#define BIT_FIFO_COUNT_ENDIAN_POS 5

## ◆ BIT_FIFO_COUNT_REC_MASK

#define BIT_FIFO_COUNT_REC_MASK (0x01 << BIT_FIFO_COUNT_REC_POS)

## ◆ BIT_FIFO_COUNT_REC_POS

#define BIT_FIFO_COUNT_REC_POS 6

## ◆ BIT_FIFO_MEM_RD_SYS

#define BIT_FIFO_MEM_RD_SYS 0x02

## ◆ BIT_FIFO_MEM_WR_SER

#define BIT_FIFO_MEM_WR_SER 0x01

## ◆ BIT_FIFO_SREG_INVALID_IND_MASK

#define BIT_FIFO_SREG_INVALID_IND_MASK (0x01 << BIT_FIFO_SREG_INVALID_IND_POS)

## ◆ BIT_FIFO_SREG_INVALID_IND_POS

#define BIT_FIFO_SREG_INVALID_IND_POS 7

## ◆ BIT_FSYNC_CONFIG_UI_SEL_MASK

#define BIT_FSYNC_CONFIG_UI_SEL_MASK (0x7 << BIT_FSYNC_CONFIG_UI_SEL_POS)

## ◆ BIT_FSYNC_CONFIG_UI_SEL_POS

#define BIT_FSYNC_CONFIG_UI_SEL_POS 4

## ◆ BIT_GYRO_AAF_BITSHIFT_MASK

#define BIT_GYRO_AAF_BITSHIFT_MASK (0x0F << BIT_GYRO_AAF_BITSHIFT_POS)

## ◆ BIT_GYRO_AAF_BITSHIFT_POS

#define BIT_GYRO_AAF_BITSHIFT_POS 4

## ◆ BIT_GYRO_AAF_DELT_MASK

#define BIT_GYRO_AAF_DELT_MASK (0x3F << BIT_GYRO_AAF_DELT_POS)

## ◆ BIT_GYRO_AAF_DELT_POS

#define BIT_GYRO_AAF_DELT_POS 0

## ◆ BIT_GYRO_AAF_DELTSQR_MASK_HI

#define BIT_GYRO_AAF_DELTSQR_MASK_HI (0x0F << BIT_GYRO_AAF_DELTSQR_POS_HI)

## ◆ BIT_GYRO_AAF_DELTSQR_MASK_LO

#define BIT_GYRO_AAF_DELTSQR_MASK_LO (0xFF << BIT_GYRO_AAF_DELTSQR_POS_LO)

## ◆ BIT_GYRO_AAF_DELTSQR_POS_HI

#define BIT_GYRO_AAF_DELTSQR_POS_HI 0

## ◆ BIT_GYRO_AAF_DELTSQR_POS_LO

#define BIT_GYRO_AAF_DELTSQR_POS_LO 0

## ◆ BIT_GYRO_AAF_DIS_MASK

#define BIT_GYRO_AAF_DIS_MASK (0x01 << BIT_GYRO_AAF_DIS_POS)

## ◆ BIT_GYRO_AAF_DIS_POS

#define BIT_GYRO_AAF_DIS_POS 1

## ◆ BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_MASK

#define BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_MASK (0xF << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS)

## ◆ BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS

#define BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS 4

## ◆ BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_MASK

#define BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_MASK 0x0F

## ◆ BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_POS

#define BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_POS 0

## ◆ BIT_GYRO_CONFIG0_FS_SEL_MASK

#define BIT_GYRO_CONFIG0_FS_SEL_MASK (7 << BIT_GYRO_CONFIG0_FS_SEL_POS)

## ◆ BIT_GYRO_CONFIG0_FS_SEL_POS

#define BIT_GYRO_CONFIG0_FS_SEL_POS 5

## ◆ BIT_GYRO_CONFIG0_ODR_MASK

#define BIT_GYRO_CONFIG0_ODR_MASK 0x0F

## ◆ BIT_GYRO_CONFIG0_ODR_POS

#define BIT_GYRO_CONFIG0_ODR_POS 0

## ◆ BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_MASK

#define BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_MASK 0x3

## ◆ BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_POS

#define BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_POS 0

## ◆ BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_MASK

#define BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_MASK (0x3 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS)

## ◆ BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS

#define BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS 2

## ◆ BIT_GYRO_CONFIG1_TEMP_FILT_BW_MASK

#define BIT_GYRO_CONFIG1_TEMP_FILT_BW_MASK (0x7 << BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS)

## ◆ BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS

#define BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS 5

## ◆ BIT_GYRO_NF_DIS_MASK

#define BIT_GYRO_NF_DIS_MASK (0x01 << BIT_GYRO_NF_DIS_POS)

## ◆ BIT_GYRO_NF_DIS_POS

#define BIT_GYRO_NF_DIS_POS 0

## ◆ BIT_GYRO_X_OFFUSER_MASK_HI

#define BIT_GYRO_X_OFFUSER_MASK_HI (0x0F << BIT_GYRO_X_OFFUSER_POS_HI)

## ◆ BIT_GYRO_X_OFFUSER_MASK_LO

#define BIT_GYRO_X_OFFUSER_MASK_LO (0xFF << BIT_GYRO_X_OFFUSER_POS_LO)

## ◆ BIT_GYRO_X_OFFUSER_POS_HI

#define BIT_GYRO_X_OFFUSER_POS_HI 0

## ◆ BIT_GYRO_X_OFFUSER_POS_LO

#define BIT_GYRO_X_OFFUSER_POS_LO 0

## ◆ BIT_GYRO_X_ST_EN

#define BIT_GYRO_X_ST_EN 0x01

## ◆ BIT_GYRO_Y_OFFUSER_MASK_HI

#define BIT_GYRO_Y_OFFUSER_MASK_HI (0x0F << BIT_GYRO_Y_OFFUSER_POS_HI)

## ◆ BIT_GYRO_Y_OFFUSER_MASK_LO

#define BIT_GYRO_Y_OFFUSER_MASK_LO (0xFF << BIT_GYRO_Y_OFFUSER_POS_LO)

## ◆ BIT_GYRO_Y_OFFUSER_POS_HI

#define BIT_GYRO_Y_OFFUSER_POS_HI 4

## ◆ BIT_GYRO_Y_OFFUSER_POS_LO

#define BIT_GYRO_Y_OFFUSER_POS_LO 0

## ◆ BIT_GYRO_Y_ST_EN

#define BIT_GYRO_Y_ST_EN 0x02

## ◆ BIT_GYRO_Z_OFFUSER_MASK_HI

#define BIT_GYRO_Z_OFFUSER_MASK_HI (0x0F << BIT_GYRO_Z_OFFUSER_POS_HI)

## ◆ BIT_GYRO_Z_OFFUSER_MASK_LO

#define BIT_GYRO_Z_OFFUSER_MASK_LO (0xFF << BIT_GYRO_Z_OFFUSER_POS_LO)

## ◆ BIT_GYRO_Z_OFFUSER_POS_HI

#define BIT_GYRO_Z_OFFUSER_POS_HI 0

## ◆ BIT_GYRO_Z_OFFUSER_POS_LO

#define BIT_GYRO_Z_OFFUSER_POS_LO 0

## ◆ BIT_GYRO_Z_ST_EN

#define BIT_GYRO_Z_ST_EN 0x04

## ◆ BIT_INT_CONFIG1_ASY_RST_MASK

#define BIT_INT_CONFIG1_ASY_RST_MASK (0x1 << BIT_INT_CONFIG1_ASY_RST_POS)

## ◆ BIT_INT_CONFIG1_ASY_RST_POS

#define BIT_INT_CONFIG1_ASY_RST_POS 4

## ◆ BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_MASK

#define BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS)

## ◆ BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS

#define BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS 1

## ◆ BIT_INT_CONFIG_INT1_POLARITY_MASK

#define BIT_INT_CONFIG_INT1_POLARITY_MASK 0x01

## ◆ BIT_INT_CONFIG_INT1_POLARITY_POS

#define BIT_INT_CONFIG_INT1_POLARITY_POS 0

## ◆ BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_MASK

#define BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS)

## ◆ BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS

#define BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS 4

## ◆ BIT_INT_CONFIG_INT2_POLARITY_MASK

#define BIT_INT_CONFIG_INT2_POLARITY_MASK (0x01 << BIT_INT_CONFIG_INT2_POLARITY_POS)

## ◆ BIT_INT_CONFIG_INT2_POLARITY_POS

#define BIT_INT_CONFIG_INT2_POLARITY_POS 3

## ◆ BIT_INT_FIFO_FULL_IBI_EN_POS

#define BIT_INT_FIFO_FULL_IBI_EN_POS 1

## ◆ BIT_INT_FIFO_FULL_INT_EN_POS

#define BIT_INT_FIFO_FULL_INT_EN_POS 1

## ◆ BIT_INT_FIFO_THS_IBI_EN_POS

#define BIT_INT_FIFO_THS_IBI_EN_POS 2

## ◆ BIT_INT_FIFO_THS_INT_EN_POS

#define BIT_INT_FIFO_THS_INT_EN_POS 2

## ◆ BIT_INT_OIS1_DRDY_IBI_EN_POS

#define BIT_INT_OIS1_DRDY_IBI_EN_POS 6

## ◆ BIT_INT_PLL_RDY_IBI_EN_POS

#define BIT_INT_PLL_RDY_IBI_EN_POS 4

## ◆ BIT_INT_PLL_RDY_INT_EN_POS

#define BIT_INT_PLL_RDY_INT_EN_POS 5

## ◆ BIT_INT_RESET_DONE_INT_EN_POS

#define BIT_INT_RESET_DONE_INT_EN_POS 4

## ◆ BIT_INT_SLEEP_DET_IBI_EN_POS

#define BIT_INT_SLEEP_DET_IBI_EN_POS 1

## ◆ BIT_INT_SLEEP_DET_INT_EN_POS

#define BIT_INT_SLEEP_DET_INT_EN_POS 1

## ◆ BIT_INT_SMD_IBI_EN_POS

#define BIT_INT_SMD_IBI_EN_POS 4

## ◆ BIT_INT_SMD_INT_EN_POS

#define BIT_INT_SMD_INT_EN_POS 3

## ◆ BIT_INT_SOURCE0_FIFO_FULL_INT1_EN

#define BIT_INT_SOURCE0_FIFO_FULL_INT1_EN 0x02

## ◆ BIT_INT_SOURCE0_FIFO_THS_INT1_EN

#define BIT_INT_SOURCE0_FIFO_THS_INT1_EN 0x04

## ◆ BIT_INT_SOURCE0_PLL_RDY_INT1_EN

#define BIT_INT_SOURCE0_PLL_RDY_INT1_EN 0x20

## ◆ BIT_INT_SOURCE0_RESET_DONE_INT1_EN

#define BIT_INT_SOURCE0_RESET_DONE_INT1_EN 0x10

## ◆ BIT_INT_SOURCE0_UI_AGC_RDY_INT1_EN

#define BIT_INT_SOURCE0_UI_AGC_RDY_INT1_EN 0x01

## ◆ BIT_INT_SOURCE0_UI_DRDY_INT1_EN

#define BIT_INT_SOURCE0_UI_DRDY_INT1_EN 0x08

## ◆ BIT_INT_SOURCE0_UI_FSYNC_INT1_EN

#define BIT_INT_SOURCE0_UI_FSYNC_INT1_EN 0x40

## ◆ BIT_INT_SOURCE10_SLEEP_DET_IBI_EN

#define BIT_INT_SOURCE10_SLEEP_DET_IBI_EN 0x02

## ◆ BIT_INT_SOURCE10_STEP_CNT_OVFL_IBI_EN

#define BIT_INT_SOURCE10_STEP_CNT_OVFL_IBI_EN 0x10

## ◆ BIT_INT_SOURCE10_STEP_DET_IBI_EN

#define BIT_INT_SOURCE10_STEP_DET_IBI_EN 0x20

## ◆ BIT_INT_SOURCE10_TAP_DET_IBI_EN

#define BIT_INT_SOURCE10_TAP_DET_IBI_EN 0x01

## ◆ BIT_INT_SOURCE10_TILT_DET_IBI_EN

#define BIT_INT_SOURCE10_TILT_DET_IBI_EN 0x08

## ◆ BIT_INT_SOURCE10_WAKE_DET_IBI_EN

#define BIT_INT_SOURCE10_WAKE_DET_IBI_EN 0x04

## ◆ BIT_INT_SOURCE1_SMD_INT1_EN

#define BIT_INT_SOURCE1_SMD_INT1_EN 0x08

## ◆ BIT_INT_SOURCE1_WOM_X_INT1_EN

#define BIT_INT_SOURCE1_WOM_X_INT1_EN 0x01

## ◆ BIT_INT_SOURCE1_WOM_Y_INT1_EN

#define BIT_INT_SOURCE1_WOM_Y_INT1_EN 0x02

## ◆ BIT_INT_SOURCE1_WOM_Z_INT1_EN

#define BIT_INT_SOURCE1_WOM_Z_INT1_EN 0x04

## ◆ BIT_INT_SOURCE2_OIS1_AGC_RDY_INT1_EN

#define BIT_INT_SOURCE2_OIS1_AGC_RDY_INT1_EN 0x04

## ◆ BIT_INT_SOURCE2_OIS1_DRDY_INT1_EN

#define BIT_INT_SOURCE2_OIS1_DRDY_INT1_EN 0x01

## ◆ BIT_INT_SOURCE2_OIS1_FSYNC_INT1_EN

#define BIT_INT_SOURCE2_OIS1_FSYNC_INT1_EN 0x02

## ◆ BIT_INT_SOURCE2_OIS2_AGC_RDY_INT1_EN

#define BIT_INT_SOURCE2_OIS2_AGC_RDY_INT1_EN 0x20

## ◆ BIT_INT_SOURCE2_OIS2_DRDY_INT1_EN

#define BIT_INT_SOURCE2_OIS2_DRDY_INT1_EN 0x08

## ◆ BIT_INT_SOURCE2_OIS2_FSYNC_INT1_EN

#define BIT_INT_SOURCE2_OIS2_FSYNC_INT1_EN 0x10

## ◆ BIT_INT_SOURCE3_FIFO_FULL_INT2_EN

#define BIT_INT_SOURCE3_FIFO_FULL_INT2_EN 0x02

## ◆ BIT_INT_SOURCE3_FIFO_THS_INT2_EN

#define BIT_INT_SOURCE3_FIFO_THS_INT2_EN 0x04

## ◆ BIT_INT_SOURCE3_PLL_RDY_INT2_EN

#define BIT_INT_SOURCE3_PLL_RDY_INT2_EN 0x20

## ◆ BIT_INT_SOURCE3_RESET_DONE_INT2_EN

#define BIT_INT_SOURCE3_RESET_DONE_INT2_EN 0x10

## ◆ BIT_INT_SOURCE3_UI_AGC_RDY_INT2_EN

#define BIT_INT_SOURCE3_UI_AGC_RDY_INT2_EN 0x01

## ◆ BIT_INT_SOURCE3_UI_DRDY_INT2_EN

#define BIT_INT_SOURCE3_UI_DRDY_INT2_EN 0x08

## ◆ BIT_INT_SOURCE3_UI_FSYNC_INT2_EN

#define BIT_INT_SOURCE3_UI_FSYNC_INT2_EN 0x40

## ◆ BIT_INT_SOURCE4_SMD_INT2_EN

#define BIT_INT_SOURCE4_SMD_INT2_EN 0x08

## ◆ BIT_INT_SOURCE4_WOM_X_INT2_EN

#define BIT_INT_SOURCE4_WOM_X_INT2_EN 0x01

## ◆ BIT_INT_SOURCE4_WOM_Y_INT2_EN

#define BIT_INT_SOURCE4_WOM_Y_INT2_EN 0x02

## ◆ BIT_INT_SOURCE4_WOM_Z_INT2_EN

#define BIT_INT_SOURCE4_WOM_Z_INT2_EN 0x04

## ◆ BIT_INT_SOURCE5_OIS1_AGC_RDY_INT2_EN

#define BIT_INT_SOURCE5_OIS1_AGC_RDY_INT2_EN 0x04

## ◆ BIT_INT_SOURCE5_OIS1_DRDY_INT2_EN

#define BIT_INT_SOURCE5_OIS1_DRDY_INT2_EN 0x01

## ◆ BIT_INT_SOURCE5_OIS1_FSYNC_INT2_EN

#define BIT_INT_SOURCE5_OIS1_FSYNC_INT2_EN 0x02

## ◆ BIT_INT_SOURCE5_OIS2_AGC_RDY_INT2_EN

#define BIT_INT_SOURCE5_OIS2_AGC_RDY_INT2_EN 0x20

## ◆ BIT_INT_SOURCE5_OIS2_DRDY_INT2_EN

#define BIT_INT_SOURCE5_OIS2_DRDY_INT2_EN 0x08

## ◆ BIT_INT_SOURCE5_OIS2_FSYNC_INT2_EN

#define BIT_INT_SOURCE5_OIS2_FSYNC_INT2_EN 0x10

## ◆ BIT_INT_SOURCE6_SLEEP_DET_INT1_EN

#define BIT_INT_SOURCE6_SLEEP_DET_INT1_EN 0x2

## ◆ BIT_INT_SOURCE6_STEP_CNT_OVFL_INT1_EN

#define BIT_INT_SOURCE6_STEP_CNT_OVFL_INT1_EN 0x10

## ◆ BIT_INT_SOURCE6_STEP_DET_INT1_EN

#define BIT_INT_SOURCE6_STEP_DET_INT1_EN 0x20

## ◆ BIT_INT_SOURCE6_TAP_DET_INT1_EN

#define BIT_INT_SOURCE6_TAP_DET_INT1_EN 0x1

## ◆ BIT_INT_SOURCE6_TILT_DET_INT1_EN

#define BIT_INT_SOURCE6_TILT_DET_INT1_EN 0x8

## ◆ BIT_INT_SOURCE6_WAKE_DET_INT1_EN

#define BIT_INT_SOURCE6_WAKE_DET_INT1_EN 0x4

## ◆ BIT_INT_SOURCE7_SLEEP_DET_INT2_EN

#define BIT_INT_SOURCE7_SLEEP_DET_INT2_EN 0x2

## ◆ BIT_INT_SOURCE7_STEP_CNT_OVFL_INT2_EN

#define BIT_INT_SOURCE7_STEP_CNT_OVFL_INT2_EN 0x10

## ◆ BIT_INT_SOURCE7_STEP_DET_INT2_EN

#define BIT_INT_SOURCE7_STEP_DET_INT2_EN 0x20

## ◆ BIT_INT_SOURCE7_TAP_DET_INT2_EN

#define BIT_INT_SOURCE7_TAP_DET_INT2_EN 0x1

## ◆ BIT_INT_SOURCE7_TILT_DET_INT2_EN

#define BIT_INT_SOURCE7_TILT_DET_INT2_EN 0x8

## ◆ BIT_INT_SOURCE7_WAKE_DET_INT2_EN

#define BIT_INT_SOURCE7_WAKE_DET_INT2_EN 0x4

## ◆ BIT_INT_SOURCE8_FIFO_FULL_IBI_EN

#define BIT_INT_SOURCE8_FIFO_FULL_IBI_EN 0x02

## ◆ BIT_INT_SOURCE8_FIFO_THS_IBI_EN

#define BIT_INT_SOURCE8_FIFO_THS_IBI_EN 0x04

## ◆ BIT_INT_SOURCE8_OIS1_DRDY_IBI_EN

#define BIT_INT_SOURCE8_OIS1_DRDY_IBI_EN 0x40

## ◆ BIT_INT_SOURCE8_PLL_RDY_IBI_EN

#define BIT_INT_SOURCE8_PLL_RDY_IBI_EN 0x10

## ◆ BIT_INT_SOURCE8_UI_AGC_RDY_IBI_EN

#define BIT_INT_SOURCE8_UI_AGC_RDY_IBI_EN 0x01

## ◆ BIT_INT_SOURCE8_UI_DRDY_IBI_EN

#define BIT_INT_SOURCE8_UI_DRDY_IBI_EN 0x08

## ◆ BIT_INT_SOURCE8_UI_FSYNC_IBI_EN

#define BIT_INT_SOURCE8_UI_FSYNC_IBI_EN 0x20

## ◆ BIT_INT_SOURCE9_SMD_IBI_EN

#define BIT_INT_SOURCE9_SMD_IBI_EN 0x10

## ◆ BIT_INT_SOURCE9_WOM_X_IBI_EN

#define BIT_INT_SOURCE9_WOM_X_IBI_EN 0x02

## ◆ BIT_INT_SOURCE9_WOM_Y_IBI_EN

#define BIT_INT_SOURCE9_WOM_Y_IBI_EN 0x04

## ◆ BIT_INT_SOURCE9_WOM_Z_IBI_EN

#define BIT_INT_SOURCE9_WOM_Z_IBI_EN 0x08

## ◆ BIT_INT_STATUS2_SMD_INT

#define BIT_INT_STATUS2_SMD_INT 0x08

## ◆ BIT_INT_STATUS2_WOM_X_INT

#define BIT_INT_STATUS2_WOM_X_INT 0x01

## ◆ BIT_INT_STATUS2_WOM_Y_INT

#define BIT_INT_STATUS2_WOM_Y_INT 0x02

## ◆ BIT_INT_STATUS2_WOM_Z_INT

#define BIT_INT_STATUS2_WOM_Z_INT 0x04

## ◆ BIT_INT_STATUS3_SLEEP_DET

#define BIT_INT_STATUS3_SLEEP_DET 0x02

## ◆ BIT_INT_STATUS3_STEP_CNT_OVFL

#define BIT_INT_STATUS3_STEP_CNT_OVFL 0x10

## ◆ BIT_INT_STATUS3_STEP_DET

#define BIT_INT_STATUS3_STEP_DET 0x20

## ◆ BIT_INT_STATUS3_TAP_DET

#define BIT_INT_STATUS3_TAP_DET 0x01

## ◆ BIT_INT_STATUS3_TILT_DET

#define BIT_INT_STATUS3_TILT_DET 0x08

## ◆ BIT_INT_STATUS3_WAKE_DET

#define BIT_INT_STATUS3_WAKE_DET 0x04

## ◆ BIT_INT_STATUS_AGC_RDY

#define BIT_INT_STATUS_AGC_RDY 0x01

## ◆ BIT_INT_STATUS_DRDY

#define BIT_INT_STATUS_DRDY 0x08

## ◆ BIT_INT_STATUS_FIFO_FULL

#define BIT_INT_STATUS_FIFO_FULL 0x02

## ◆ BIT_INT_STATUS_FIFO_THS

#define BIT_INT_STATUS_FIFO_THS 0x04

## ◆ BIT_INT_STATUS_OIS1_AGC_RDY

#define BIT_INT_STATUS_OIS1_AGC_RDY 0x01

## ◆ BIT_INT_STATUS_OIS1_DRDY

#define BIT_INT_STATUS_OIS1_DRDY 0x02

## ◆ BIT_INT_STATUS_OIS1_FSYNC

#define BIT_INT_STATUS_OIS1_FSYNC 0x04

## ◆ BIT_INT_STATUS_OIS2_AGC_RDY

#define BIT_INT_STATUS_OIS2_AGC_RDY 0x01

## ◆ BIT_INT_STATUS_OIS2_DRDY

#define BIT_INT_STATUS_OIS2_DRDY 0x02

## ◆ BIT_INT_STATUS_OIS2_FSYNC

#define BIT_INT_STATUS_OIS2_FSYNC 0x04

## ◆ BIT_INT_STATUS_PLL_RDY

#define BIT_INT_STATUS_PLL_RDY 0x20

## ◆ BIT_INT_STATUS_RESET_DONE

#define BIT_INT_STATUS_RESET_DONE 0x10

## ◆ BIT_INT_STATUS_UI_FSYNC

#define BIT_INT_STATUS_UI_FSYNC 0x40

## ◆ BIT_INT_STEP_CNT_OVFL_IBI_EN_POS

#define BIT_INT_STEP_CNT_OVFL_IBI_EN_POS 4

## ◆ BIT_INT_STEP_CNT_OVFL_INT_EN_POS

#define BIT_INT_STEP_CNT_OVFL_INT_EN_POS 4

## ◆ BIT_INT_STEP_DET_IBI_EN_POS

#define BIT_INT_STEP_DET_IBI_EN_POS 5

## ◆ BIT_INT_STEP_DET_INT_EN_POS

#define BIT_INT_STEP_DET_INT_EN_POS 5

## ◆ BIT_INT_TAP_DET_IBI_EN_POS

#define BIT_INT_TAP_DET_IBI_EN_POS 0

## ◆ BIT_INT_TAP_DET_INT_EN_POS

#define BIT_INT_TAP_DET_INT_EN_POS 0

## ◆ BIT_INT_TDEASSERT_MASK

#define BIT_INT_TDEASSERT_MASK (0x1 << BIT_INT_TDEASSERT_POS)

## ◆ BIT_INT_TDEASSERT_POS

#define BIT_INT_TDEASSERT_POS 5

## ◆ BIT_INT_TILT_DET_IBI_EN_POS

#define BIT_INT_TILT_DET_IBI_EN_POS 3

## ◆ BIT_INT_TILT_DET_INT_EN_POS

#define BIT_INT_TILT_DET_INT_EN_POS 3

## ◆ BIT_INT_TPULSE_DURATION_MASK

#define BIT_INT_TPULSE_DURATION_MASK (0x1 << BIT_INT_TPULSE_DURATION_POS)

## ◆ BIT_INT_TPULSE_DURATION_POS

#define BIT_INT_TPULSE_DURATION_POS 6

## ◆ BIT_INT_UI_AGC_RDY_IBI_EN_POS

#define BIT_INT_UI_AGC_RDY_IBI_EN_POS 0

## ◆ BIT_INT_UI_AGC_RDY_INT_EN_POS

#define BIT_INT_UI_AGC_RDY_INT_EN_POS 0

## ◆ BIT_INT_UI_DRDY_IBI_EN_POS

#define BIT_INT_UI_DRDY_IBI_EN_POS 3

## ◆ BIT_INT_UI_DRDY_INT_EN_POS

#define BIT_INT_UI_DRDY_INT_EN_POS 3

## ◆ BIT_INT_UI_FSYNC_IBI_EN_POS

#define BIT_INT_UI_FSYNC_IBI_EN_POS 5

## ◆ BIT_INT_UI_FSYNC_INT_EN_POS

#define BIT_INT_UI_FSYNC_INT_EN_POS 6

## ◆ BIT_INT_WAKE_DET_IBI_EN_POS

#define BIT_INT_WAKE_DET_IBI_EN_POS 2

## ◆ BIT_INT_WAKE_DET_INT_EN_POS

#define BIT_INT_WAKE_DET_INT_EN_POS 2

## ◆ BIT_INT_WOM_X_IBI_EN_POS

#define BIT_INT_WOM_X_IBI_EN_POS 1

## ◆ BIT_INT_WOM_X_INT_EN_POS

#define BIT_INT_WOM_X_INT_EN_POS 0

## ◆ BIT_INT_WOM_Y_IBI_EN_POS

#define BIT_INT_WOM_Y_IBI_EN_POS 2

## ◆ BIT_INT_WOM_Y_INT_EN_POS

#define BIT_INT_WOM_Y_INT_EN_POS 1

## ◆ BIT_INT_WOM_Z_IBI_EN_POS

#define BIT_INT_WOM_Z_IBI_EN_POS 3

## ◆ BIT_INT_WOM_Z_INT_EN_POS

#define BIT_INT_WOM_Z_INT_EN_POS 2

## ◆ BIT_INTF_CONFIG4_AP_SPI_MASK

#define BIT_INTF_CONFIG4_AP_SPI_MASK (0x1 << BIT_INTF_CONFIG4_AP_SPI_POS)

## ◆ BIT_INTF_CONFIG4_AP_SPI_POS

#define BIT_INTF_CONFIG4_AP_SPI_POS 1

## ◆ BIT_INTF_CONFIG4_AUX1_SPI_MASK

#define BIT_INTF_CONFIG4_AUX1_SPI_MASK (0x1 << BIT_INTF_CONFIG4_AUX1_SPI_POS)

## ◆ BIT_INTF_CONFIG4_AUX1_SPI_POS

#define BIT_INTF_CONFIG4_AUX1_SPI_POS 2

## ◆ BIT_INTF_CONFIG5_GPIO_PAD_SEL_MASK

#define BIT_INTF_CONFIG5_GPIO_PAD_SEL_MASK (0x3 << BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS)

## ◆ BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS

#define BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS 1

## ◆ BIT_INTF_CONFIG6_I3C_DDR_EN_MASK

#define BIT_INTF_CONFIG6_I3C_DDR_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_DDR_EN_POS)

## ◆ BIT_INTF_CONFIG6_I3C_DDR_EN_POS

#define BIT_INTF_CONFIG6_I3C_DDR_EN_POS 1

## ◆ BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_MASK

#define BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS)

## ◆ BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS

#define BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS 3

## ◆ BIT_INTF_CONFIG6_I3C_IBI_EN_MASK

#define BIT_INTF_CONFIG6_I3C_IBI_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_IBI_EN_POS)

## ◆ BIT_INTF_CONFIG6_I3C_IBI_EN_POS

#define BIT_INTF_CONFIG6_I3C_IBI_EN_POS 2

## ◆ BIT_INTF_CONFIG6_I3C_SDR_EN_MASK

#define BIT_INTF_CONFIG6_I3C_SDR_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_SDR_EN_POS)

## ◆ BIT_INTF_CONFIG6_I3C_SDR_EN_POS

#define BIT_INTF_CONFIG6_I3C_SDR_EN_POS 0

## ◆ BIT_MEM_OTP_ACCESS_EN

#define BIT_MEM_OTP_ACCESS_EN 0x04

## ◆ BIT_OIS1_CONFIG1_ACCEL_EN_MASK

#define BIT_OIS1_CONFIG1_ACCEL_EN_MASK (0x1 << BIT_OIS1_CONFIG1_ACCEL_EN_POS)

## ◆ BIT_OIS1_CONFIG1_ACCEL_EN_POS

#define BIT_OIS1_CONFIG1_ACCEL_EN_POS 0

## ◆ BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_MASK

#define BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_MASK (0x1 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS)

## ◆ BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS

#define BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS 5

## ◆ BIT_OIS1_CONFIG1_DEC_MASK

#define BIT_OIS1_CONFIG1_DEC_MASK (0x7 << BIT_OIS1_CONFIG1_DEC_POS)

## ◆ BIT_OIS1_CONFIG1_DEC_POS

#define BIT_OIS1_CONFIG1_DEC_POS 2

## ◆ BIT_OIS1_CONFIG1_GYRO_EN_MASK

#define BIT_OIS1_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS1_CONFIG1_GYRO_EN_POS)

## ◆ BIT_OIS1_CONFIG1_GYRO_EN_POS

#define BIT_OIS1_CONFIG1_GYRO_EN_POS 1

## ◆ BIT_OIS1_CONFIG2_ACCEL_FS_SEL_MASK

#define BIT_OIS1_CONFIG2_ACCEL_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS)

## ◆ BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS

#define BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS 0

## ◆ BIT_OIS1_CONFIG2_GYRO_FS_SEL_MASK

#define BIT_OIS1_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS)

## ◆ BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS

#define BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS 3

## ◆ BIT_OIS2_CONFIG1_ACCEL_EN_MASK

#define BIT_OIS2_CONFIG1_ACCEL_EN_MASK (0x1 << BIT_OIS2_CONFIG1_ACCEL_EN_POS)

## ◆ BIT_OIS2_CONFIG1_ACCEL_EN_POS

#define BIT_OIS2_CONFIG1_ACCEL_EN_POS 0

## ◆ BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_MASK

#define BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_MASK (0x1 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS)

## ◆ BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS

#define BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS 5

## ◆ BIT_OIS2_CONFIG1_DEC_MASK

#define BIT_OIS2_CONFIG1_DEC_MASK (0x7 << BIT_OIS2_CONFIG1_DEC_POS)

## ◆ BIT_OIS2_CONFIG1_DEC_POS

#define BIT_OIS2_CONFIG1_DEC_POS 2

## ◆ BIT_OIS2_CONFIG1_GYRO_EN_MASK

#define BIT_OIS2_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS2_CONFIG1_GYRO_EN_POS)

## ◆ BIT_OIS2_CONFIG1_GYRO_EN_POS

#define BIT_OIS2_CONFIG1_GYRO_EN_POS 1

## ◆ BIT_OIS2_CONFIG2_ACCEL_FS_SEL_MASK

#define BIT_OIS2_CONFIG2_ACCEL_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS)

## ◆ BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS

#define BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS 0

## ◆ BIT_OIS2_CONFIG2_GYRO_FS_SEL_MASK

#define BIT_OIS2_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS)

## ◆ BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS

#define BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS 3

## ◆ BIT_PWR_MGMT_0_ACCEL_MODE_MASK

#define BIT_PWR_MGMT_0_ACCEL_MODE_MASK 0x03

## ◆ BIT_PWR_MGMT_0_ACCEL_MODE_POS

#define BIT_PWR_MGMT_0_ACCEL_MODE_POS 0

## ◆ BIT_PWR_MGMT_0_GYRO_MODE_MASK

#define BIT_PWR_MGMT_0_GYRO_MODE_MASK (0x03 << BIT_PWR_MGMT_0_GYRO_MODE_POS)

## ◆ BIT_PWR_MGMT_0_GYRO_MODE_POS

#define BIT_PWR_MGMT_0_GYRO_MODE_POS 2

## ◆ BIT_PWR_MGMT_0_IDLE_MASK

#define BIT_PWR_MGMT_0_IDLE_MASK (0x01 << BIT_PWR_MGMT_0_IDLE_POS)

## ◆ BIT_PWR_MGMT_0_IDLE_POS

#define BIT_PWR_MGMT_0_IDLE_POS 4

## ◆ BIT_PWR_MGMT_0_TEMP_MASK

#define BIT_PWR_MGMT_0_TEMP_MASK (0x01 << BIT_PWR_MGMT_0_TEMP_POS)

## ◆ BIT_PWR_MGMT_0_TEMP_POS

#define BIT_PWR_MGMT_0_TEMP_POS 5

## ◆ BIT_RTC_MODE_MASK

#define BIT_RTC_MODE_MASK (0x01 << BIT_RTC_MODE_POS)

## ◆ BIT_RTC_MODE_POS

#define BIT_RTC_MODE_POS 2

## ◆ BIT_SENSOR_CONFIG2_OIS_MODE_MASK

#define BIT_SENSOR_CONFIG2_OIS_MODE_MASK (0x03 << BIT_SENSOR_CONFIG2_OIS_MODE_POS)

## ◆ BIT_SENSOR_CONFIG2_OIS_MODE_POS

#define BIT_SENSOR_CONFIG2_OIS_MODE_POS 4

## ◆ BIT_SIGNAL_PATH_RESET_DMP_INIT_MASK

#define BIT_SIGNAL_PATH_RESET_DMP_INIT_MASK (0x01 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS)

## ◆ BIT_SIGNAL_PATH_RESET_DMP_INIT_POS

#define BIT_SIGNAL_PATH_RESET_DMP_INIT_POS 6

## ◆ BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_MASK

#define BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_MASK (0x01 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS)

## ◆ BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS

#define BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS 5

## ◆ BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_MASK

#define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_MASK (0x01 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS)

## ◆ BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS

#define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS 1

## ◆ BIT_SIGNAL_PATH_RESET_TMST_STROBE_MASK

#define BIT_SIGNAL_PATH_RESET_TMST_STROBE_MASK (0x01 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS)

## ◆ BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS

#define BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS 2

## ◆ BIT_SMD_CONFIG_SMD_MODE_MASK

#define BIT_SMD_CONFIG_SMD_MODE_MASK 0x3

## ◆ BIT_SMD_CONFIG_SMD_MODE_POS

#define BIT_SMD_CONFIG_SMD_MODE_POS 0

## ◆ BIT_SMD_CONFIG_WOM_INT_MODE_MASK

#define BIT_SMD_CONFIG_WOM_INT_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_INT_MODE_POS)

## ◆ BIT_SMD_CONFIG_WOM_INT_MODE_POS

#define BIT_SMD_CONFIG_WOM_INT_MODE_POS 3

## ◆ BIT_SMD_CONFIG_WOM_MODE_MASK

#define BIT_SMD_CONFIG_WOM_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_MODE_POS)

## ◆ BIT_SMD_CONFIG_WOM_MODE_POS

#define BIT_SMD_CONFIG_WOM_MODE_POS 2

## ◆ BIT_SPI_MODE_OIS1_MASK

#define BIT_SPI_MODE_OIS1_MASK (0x01 << BIT_SPI_MODE_OIS1_POS)

## ◆ BIT_SPI_MODE_OIS1_POS

#define BIT_SPI_MODE_OIS1_POS 2

## ◆ BIT_SPI_MODE_OIS2_MASK

#define BIT_SPI_MODE_OIS2_MASK (0x01 << BIT_SPI_MODE_OIS2_POS)

## ◆ BIT_SPI_MODE_OIS2_POS

#define BIT_SPI_MODE_OIS2_POS 3

## ◆ BIT_ST_REGULATOR_EN

#define BIT_ST_REGULATOR_EN 0x40

## ◆ BIT_TMST_CONFIG_RESOL_MASK

#define BIT_TMST_CONFIG_RESOL_MASK (0x1 << BIT_TMST_CONFIG_RESOL_POS)

## ◆ BIT_TMST_CONFIG_RESOL_POS

#define BIT_TMST_CONFIG_RESOL_POS 3

## ◆ BIT_TMST_CONFIG_TMST_EN_MASK

#define BIT_TMST_CONFIG_TMST_EN_MASK 0x1

## ◆ BIT_TMST_CONFIG_TMST_EN_POS

#define BIT_TMST_CONFIG_TMST_EN_POS 0

## ◆ BIT_TMST_CONFIG_TMST_FSYNC_MASK

#define BIT_TMST_CONFIG_TMST_FSYNC_MASK (0x1 << BIT_TMST_CONFIG_TMST_FSYNC_POS)

## ◆ BIT_TMST_CONFIG_TMST_FSYNC_POS

#define BIT_TMST_CONFIG_TMST_FSYNC_POS 1

## ◆ BIT_TMST_CONFIG_TMST_TO_REGS_EN_MASK

#define BIT_TMST_CONFIG_TMST_TO_REGS_EN_MASK (0x1 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS)

## ◆ BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS

#define BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS 4

## ◆ FIFO_16BYTES_PACKET_SIZE

#define FIFO_16BYTES_PACKET_SIZE

Value:
(FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + \
FIFO_TS_FSYNC_SIZE)
FIFO_ACCEL_DATA_SIZE
#define FIFO_ACCEL_DATA_SIZE
Definition: Icm426xxDefs.h:260
FIFO_HEADER_SIZE
#define FIFO_HEADER_SIZE
Definition: Icm426xxDefs.h:259
FIFO_GYRO_DATA_SIZE
#define FIFO_GYRO_DATA_SIZE
Definition: Icm426xxDefs.h:261
FIFO_TEMP_DATA_SIZE
#define FIFO_TEMP_DATA_SIZE
Definition: Icm426xxDefs.h:262

## ◆ FIFO_20BYTES_PACKET_SIZE

#define FIFO_20BYTES_PACKET_SIZE

Value:
(FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + \
FIFO_TS_FSYNC_SIZE + FIFO_TEMP_HIGH_RES_SIZE + FIFO_ACCEL_GYRO_HIGH_RES_SIZE)
FIFO_ACCEL_GYRO_HIGH_RES_SIZE
#define FIFO_ACCEL_GYRO_HIGH_RES_SIZE
Definition: Icm426xxDefs.h:265
FIFO_TEMP_HIGH_RES_SIZE
#define FIFO_TEMP_HIGH_RES_SIZE
Definition: Icm426xxDefs.h:264

## ◆ FIFO_ACCEL_DATA_SIZE

#define FIFO_ACCEL_DATA_SIZE ACCEL_DATA_SIZE

## ◆ FIFO_ACCEL_GYRO_HIGH_RES_SIZE

#define FIFO_ACCEL_GYRO_HIGH_RES_SIZE 3

## ◆ FIFO_GYRO_DATA_SIZE

#define FIFO_GYRO_DATA_SIZE GYRO_DATA_SIZE

## ◆ FIFO_HEADER_ACC

#define FIFO_HEADER_ACC 0x40

## ◆ FIFO_HEADER_FSYNC

#define FIFO_HEADER_FSYNC 0x04

## ◆ FIFO_HEADER_GYRO

#define FIFO_HEADER_GYRO 0x20

## ◆ FIFO_HEADER_HEADER_20

#define FIFO_HEADER_HEADER_20 0x10

## ◆ FIFO_HEADER_MSG

#define FIFO_HEADER_MSG 0x80

## ◆ FIFO_HEADER_ODR_ACCEL

#define FIFO_HEADER_ODR_ACCEL 0x01

## ◆ FIFO_HEADER_ODR_GYRO

#define FIFO_HEADER_ODR_GYRO 0x02

## ◆ FIFO_HEADER_SIZE

#define FIFO_HEADER_SIZE 1

## ◆ FIFO_HEADER_TMST

#define FIFO_HEADER_TMST 0x08

## ◆ FIFO_TEMP_DATA_SIZE

#define FIFO_TEMP_DATA_SIZE 1

## ◆ FIFO_TEMP_HIGH_RES_SIZE

#define FIFO_TEMP_HIGH_RES_SIZE 1

## ◆ FIFO_TS_FSYNC_SIZE

#define FIFO_TS_FSYNC_SIZE 2

## ◆ GYRO_DATA_SIZE

#define GYRO_DATA_SIZE 6

## ◆ I3C_IBI_PAYLOAD_ALL

#define I3C_IBI_PAYLOAD_ALL 0xFF

## ◆ I3C_IBI_PAYLOAD_CAT_APEX1

#define I3C_IBI_PAYLOAD_CAT_APEX1 0x08

## ◆ I3C_IBI_PAYLOAD_CAT_APEX2

#define I3C_IBI_PAYLOAD_CAT_APEX2 0x10

## ◆ I3C_IBI_PAYLOAD_CAT_ERROR

#define I3C_IBI_PAYLOAD_CAT_ERROR 0x20

## ◆ I3C_IBI_PAYLOAD_CAT_FIFO

#define I3C_IBI_PAYLOAD_CAT_FIFO 0x02

## ◆ I3C_IBI_PAYLOAD_CAT_MISC

#define I3C_IBI_PAYLOAD_CAT_MISC 0x40

## ◆ I3C_IBI_PAYLOAD_CAT_OIS1_DRDY

#define I3C_IBI_PAYLOAD_CAT_OIS1_DRDY 0x04

## ◆ I3C_IBI_PAYLOAD_CAT_UI_DRDY

#define I3C_IBI_PAYLOAD_CAT_UI_DRDY 0x01

## ◆ I3C_IBI_PAYLOAD_TIMEC

#define I3C_IBI_PAYLOAD_TIMEC 0x80

## ◆ ICM40608_WHOAMI

#define ICM40608_WHOAMI 0x39

## ◆ ICM42600_WHOAMI

#define ICM42600_WHOAMI 0x40

## ◆ ICM42602_WHOAMI

#define ICM42602_WHOAMI 0x41

## ◆ ICM42605_WHOAMI

#define ICM42605_WHOAMI 0x42

## ◆ ICM42608_WHOAMI

#define ICM42608_WHOAMI 0x48

## ◆ ICM42622_WHOAMI

#define ICM42622_WHOAMI 0x46

## ◆ ICM42631_WHOAMI

#define ICM42631_WHOAMI 0x5C

## ◆ ICM42633_WHOAMI

#define ICM42633_WHOAMI 0x5B

## ◆ ICM42686P_WHOAMI

#define ICM42686P_WHOAMI 0x44

## ◆ ICM42686V_WHOAMI

#define ICM42686V_WHOAMI 0xDA

## ◆ ICM42688P_WHOAMI

#define ICM42688P_WHOAMI 0x47

## ◆ ICM42688V_WHOAMI

#define ICM42688V_WHOAMI 0xDB

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1006632MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1006632MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_30MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1174405MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1174405MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_35MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1342177MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1342177MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_40MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1509949MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1509949MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_45MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1677721MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1677721MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_50MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1845493MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1845493MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_55MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2013265MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2013265MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_60MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2181038MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2181038MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_65MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2348810MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2348810MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_70MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2516582MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2516582MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_75MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2684354MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2684354MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_80MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2852126MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2852126MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_85MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3019898MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3019898MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_90MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3187671MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3187671MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_95MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3355443MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3355443MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_100MG

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3523215MG

#define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3523215MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_105MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1006632_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1006632_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_30MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1140850_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1140850_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_34MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1275068_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1275068_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_38MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1409286_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1409286_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_42MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1543503_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1543503_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_46MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1677721_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1677721_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_50MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1811939_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1811939_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_54MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1946157_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1946157_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_58MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2080374_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2080374_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_62MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2214592_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2214592_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_66MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2348810_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2348810_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_70MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2483027_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2483027_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_74MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2617245_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2617245_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_78MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2751463_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2751463_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_82MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2885681_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2885681_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_86MG

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_3019898_MG

#define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_3019898_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_90MG

## ◆ ICM426XX_APEX_CONFIG7_TAP_MIN_JERK_THR_281MG_DEFAULT

#define ICM426XX_APEX_CONFIG7_TAP_MIN_JERK_THR_281MG_DEFAULT 0x11

## ◆ ICM426XX_FIFO_CONFIG_MODE_SNAPSHOT

#define ICM426XX_FIFO_CONFIG_MODE_SNAPSHOT = ICM426XX_FIFO_CONFIG_MODE_STOP_ON_FULL;

## ◆ ICM_FAMILY_BPLUS

#define ICM_FAMILY_BPLUS

ICM family definition Possible values are ICM_FAMILY_CPLUS or ICM_FAMILY_BPLUS.

## ◆ INVALID_VALUE_FIFO

#define INVALID_VALUE_FIFO ((int16_t)0x8000)

## ◆ INVALID_VALUE_FIFO_1B

#define INVALID_VALUE_FIFO_1B ((int8_t)0x80)

## ◆ MPUREG_ACCEL_CONFIG0

#define MPUREG_ACCEL_CONFIG0 0x50

## ◆ MPUREG_ACCEL_CONFIG1

#define MPUREG_ACCEL_CONFIG1 0x53

## ◆ MPUREG_ACCEL_CONFIG_STATIC0_B2

#define MPUREG_ACCEL_CONFIG_STATIC0_B2 0x39

## ◆ MPUREG_ACCEL_CONFIG_STATIC2_B2

#define MPUREG_ACCEL_CONFIG_STATIC2_B2 0x03

## ◆ MPUREG_ACCEL_CONFIG_STATIC3_B2

#define MPUREG_ACCEL_CONFIG_STATIC3_B2 0x04

## ◆ MPUREG_ACCEL_CONFIG_STATIC4_B2

#define MPUREG_ACCEL_CONFIG_STATIC4_B2 0x05

## ◆ MPUREG_ACCEL_DATA_X0_OIS1_B2

#define MPUREG_ACCEL_DATA_X0_OIS1_B2 0x49

## ◆ MPUREG_ACCEL_DATA_X0_OIS2_B2

#define MPUREG_ACCEL_DATA_X0_OIS2_B2 0x5E

## ◆ MPUREG_ACCEL_DATA_X0_UI

#define MPUREG_ACCEL_DATA_X0_UI 0x1F

## ◆ MPUREG_ACCEL_GYRO_CONFIG0

#define MPUREG_ACCEL_GYRO_CONFIG0 0x52

## ◆ MPUREG_ACCEL_WOM_X_THR_B4

#define MPUREG_ACCEL_WOM_X_THR_B4 0x4A

## ◆ MPUREG_ACCEL_WOM_Y_THR_B4

#define MPUREG_ACCEL_WOM_Y_THR_B4 0x4B

## ◆ MPUREG_ACCEL_WOM_Z_THR_B4

#define MPUREG_ACCEL_WOM_Z_THR_B4 0x4C

## ◆ MPUREG_APEX_CONFIG0

#define MPUREG_APEX_CONFIG0 0x56

## ◆ MPUREG_APEX_CONFIG10_B4

#define MPUREG_APEX_CONFIG10_B4 0x49

## ◆ MPUREG_APEX_CONFIG1_B4

#define MPUREG_APEX_CONFIG1_B4 0x40

## ◆ MPUREG_APEX_CONFIG2_B4

#define MPUREG_APEX_CONFIG2_B4 0x41

## ◆ MPUREG_APEX_CONFIG3_B4

#define MPUREG_APEX_CONFIG3_B4 0x42

## ◆ MPUREG_APEX_CONFIG4_B4

#define MPUREG_APEX_CONFIG4_B4 0x43

## ◆ MPUREG_APEX_CONFIG5_B4

#define MPUREG_APEX_CONFIG5_B4 0x44

## ◆ MPUREG_APEX_CONFIG6_B4

#define MPUREG_APEX_CONFIG6_B4 0x45

## ◆ MPUREG_APEX_CONFIG7_B4

#define MPUREG_APEX_CONFIG7_B4 0x46

## ◆ MPUREG_APEX_CONFIG8_B4

#define MPUREG_APEX_CONFIG8_B4 0x47

## ◆ MPUREG_APEX_CONFIG9_B4

#define MPUREG_APEX_CONFIG9_B4 0x48

## ◆ MPUREG_APEX_DATA0

#define MPUREG_APEX_DATA0 0x31

## ◆ MPUREG_APEX_DATA1

#define MPUREG_APEX_DATA1 0x32

## ◆ MPUREG_APEX_DATA2

#define MPUREG_APEX_DATA2 0x33

## ◆ MPUREG_APEX_DATA3

#define MPUREG_APEX_DATA3 0x34

## ◆ MPUREG_APEX_DATA4

#define MPUREG_APEX_DATA4 0x35

## ◆ MPUREG_APEX_DATA5

#define MPUREG_APEX_DATA5 0x36

## ◆ MPUREG_CHIP_CONFIG

#define MPUREG_CHIP_CONFIG MPUREG_DEVICE_CONFIG

## ◆ MPUREG_DEVICE_CONFIG

#define MPUREG_DEVICE_CONFIG 0x11

## ◆ MPUREG_DRIVE_CONFIG

#define MPUREG_DRIVE_CONFIG 0x13

## ◆ MPUREG_FDR_CONFIG_B4

#define MPUREG_FDR_CONFIG_B4 0x09

## ◆ MPUREG_FIFO_BYTE_COUNT1

#define MPUREG_FIFO_BYTE_COUNT1 MPUREG_FIFO_COUNTH

## ◆ MPUREG_FIFO_BYTE_COUNT2

#define MPUREG_FIFO_BYTE_COUNT2 MPUREG_FIFO_COUNTL

## ◆ MPUREG_FIFO_CONFIG

#define MPUREG_FIFO_CONFIG 0x16

## ◆ MPUREG_FIFO_CONFIG1

#define MPUREG_FIFO_CONFIG1 0x5F

## ◆ MPUREG_FIFO_CONFIG2

#define MPUREG_FIFO_CONFIG2 0x60

## ◆ MPUREG_FIFO_COUNTH

#define MPUREG_FIFO_COUNTH 0x2E

## ◆ MPUREG_FIFO_COUNTL

#define MPUREG_FIFO_COUNTL 0x2F

## ◆ MPUREG_FIFO_DATA

#define MPUREG_FIFO_DATA 0x30

## ◆ MPUREG_FIFO_LOST_PKT0

#define MPUREG_FIFO_LOST_PKT0 0x6C

## ◆ MPUREG_FSYNC_CONFIG

#define MPUREG_FSYNC_CONFIG 0x62

## ◆ MPUREG_GYRO_CONFIG0

#define MPUREG_GYRO_CONFIG0 0x4F

## ◆ MPUREG_GYRO_CONFIG1

#define MPUREG_GYRO_CONFIG1 0x51

## ◆ MPUREG_GYRO_CONFIG_STATIC2_B1

#define MPUREG_GYRO_CONFIG_STATIC2_B1 0x0B

## ◆ MPUREG_GYRO_CONFIG_STATIC3_B1

#define MPUREG_GYRO_CONFIG_STATIC3_B1 0x0C

## ◆ MPUREG_GYRO_CONFIG_STATIC4_B1

#define MPUREG_GYRO_CONFIG_STATIC4_B1 0x0D

## ◆ MPUREG_GYRO_CONFIG_STATIC5_B1

#define MPUREG_GYRO_CONFIG_STATIC5_B1 0x0E

## ◆ MPUREG_GYRO_DATA_X0_OIS1_B2

#define MPUREG_GYRO_DATA_X0_OIS1_B2 0x4F

## ◆ MPUREG_GYRO_DATA_X0_OIS2_B2

#define MPUREG_GYRO_DATA_X0_OIS2_B2 0x64

## ◆ MPUREG_GYRO_DATA_X0_UI

#define MPUREG_GYRO_DATA_X0_UI 0x25

## ◆ MPUREG_INT_CONFIG

#define MPUREG_INT_CONFIG 0x14

## ◆ MPUREG_INT_CONFIG0

#define MPUREG_INT_CONFIG0 0x63

## ◆ MPUREG_INT_CONFIG1

#define MPUREG_INT_CONFIG1 0x64

## ◆ MPUREG_INT_SOURCE0

#define MPUREG_INT_SOURCE0 0x65

## ◆ MPUREG_INT_SOURCE1

#define MPUREG_INT_SOURCE1 0x66

## ◆ MPUREG_INT_SOURCE10_B4

#define MPUREG_INT_SOURCE10_B4 0x51

## ◆ MPUREG_INT_SOURCE2

#define MPUREG_INT_SOURCE2 0x67

## ◆ MPUREG_INT_SOURCE3

#define MPUREG_INT_SOURCE3 0x68

## ◆ MPUREG_INT_SOURCE4

#define MPUREG_INT_SOURCE4 0x69

## ◆ MPUREG_INT_SOURCE5

#define MPUREG_INT_SOURCE5 0x6A

## ◆ MPUREG_INT_SOURCE6_B4

#define MPUREG_INT_SOURCE6_B4 0x4D

## ◆ MPUREG_INT_SOURCE7_B4

#define MPUREG_INT_SOURCE7_B4 0x4E

## ◆ MPUREG_INT_SOURCE8_B4

#define MPUREG_INT_SOURCE8_B4 0x4F

## ◆ MPUREG_INT_SOURCE9_B4

#define MPUREG_INT_SOURCE9_B4 0x50

## ◆ MPUREG_INT_STATUS

#define MPUREG_INT_STATUS 0x2D

## ◆ MPUREG_INT_STATUS2

#define MPUREG_INT_STATUS2 0x37

## ◆ MPUREG_INT_STATUS3

#define MPUREG_INT_STATUS3 0x38

## ◆ MPUREG_INT_STATUS_OIS1_B2

#define MPUREG_INT_STATUS_OIS1_B2 0x57

## ◆ MPUREG_INT_STATUS_OIS2_B2

#define MPUREG_INT_STATUS_OIS2_B2 0x6C

## ◆ MPUREG_INTF_CONFIG0

#define MPUREG_INTF_CONFIG0 0x4C

## ◆ MPUREG_INTF_CONFIG1

#define MPUREG_INTF_CONFIG1 0x4D

## ◆ MPUREG_INTF_CONFIG3_B1

#define MPUREG_INTF_CONFIG3_B1 0x79

## ◆ MPUREG_INTF_CONFIG4_B1

#define MPUREG_INTF_CONFIG4_B1 0x7A

## ◆ MPUREG_INTF_CONFIG5_B1

#define MPUREG_INTF_CONFIG5_B1 0x7B

## ◆ MPUREG_INTF_CONFIG6_B1

#define MPUREG_INTF_CONFIG6_B1 0x7C

## ◆ MPUREG_MEM_BANK_SEL

#define MPUREG_MEM_BANK_SEL 0x72

## ◆ MPUREG_MEM_R_W

#define MPUREG_MEM_R_W 0x74

## ◆ MPUREG_MEM_START_ADDR

#define MPUREG_MEM_START_ADDR 0x73

## ◆ MPUREG_OFFSET_USER_0_B4

#define MPUREG_OFFSET_USER_0_B4 0x77

## ◆ MPUREG_OFFSET_USER_1_B4

#define MPUREG_OFFSET_USER_1_B4 0x78

## ◆ MPUREG_OFFSET_USER_2_B4

#define MPUREG_OFFSET_USER_2_B4 0x79

## ◆ MPUREG_OFFSET_USER_3_B4

#define MPUREG_OFFSET_USER_3_B4 0x7A

## ◆ MPUREG_OFFSET_USER_4_B4

#define MPUREG_OFFSET_USER_4_B4 0x7B

## ◆ MPUREG_OFFSET_USER_5_B4

#define MPUREG_OFFSET_USER_5_B4 0x7C

## ◆ MPUREG_OFFSET_USER_6_B4

#define MPUREG_OFFSET_USER_6_B4 0x7D

## ◆ MPUREG_OFFSET_USER_7_B4

#define MPUREG_OFFSET_USER_7_B4 0x7E

## ◆ MPUREG_OFFSET_USER_8_B4

#define MPUREG_OFFSET_USER_8_B4 0x7F

## ◆ MPUREG_OIS1_CONFIG1_B2

#define MPUREG_OIS1_CONFIG1_B2 0x44

## ◆ MPUREG_OIS1_CONFIG2_B2

#define MPUREG_OIS1_CONFIG2_B2 0x45

## ◆ MPUREG_OIS1_CONFIG3_B2

#define MPUREG_OIS1_CONFIG3_B2 0x46

## ◆ MPUREG_OIS2_CONFIG1_B2

#define MPUREG_OIS2_CONFIG1_B2 0x59

## ◆ MPUREG_OIS2_CONFIG2_B2

#define MPUREG_OIS2_CONFIG2_B2 0x5A

## ◆ MPUREG_OIS2_CONFIG3_B2

#define MPUREG_OIS2_CONFIG3_B2 0x5B

## ◆ MPUREG_PU_PD_CONFIG1_B3

#define MPUREG_PU_PD_CONFIG1_B3 0x06

## ◆ MPUREG_PU_PD_CONFIG2_B3

#define MPUREG_PU_PD_CONFIG2_B3 0x0E

## ◆ MPUREG_PWR_MGMT_0

#define MPUREG_PWR_MGMT_0 0x4E

## ◆ MPUREG_REG_BANK_SEL

#define MPUREG_REG_BANK_SEL 0x76

## ◆ MPUREG_SCAN0

#define MPUREG_SCAN0 0x71

## ◆ MPUREG_SELF_TEST_CONFIG

#define MPUREG_SELF_TEST_CONFIG 0x70

## ◆ MPUREG_SENSOR_CONFIG1_B1

#define MPUREG_SENSOR_CONFIG1_B1 0x04

## ◆ MPUREG_SIGNAL_PATH_RESET

#define MPUREG_SIGNAL_PATH_RESET 0x4B

## ◆ MPUREG_SMD_CONFIG

#define MPUREG_SMD_CONFIG 0x57

## ◆ MPUREG_TEMP_DATA0_UI

#define MPUREG_TEMP_DATA0_UI 0x1D

## ◆ MPUREG_TMD4_B2

#define MPUREG_TMD4_B2 0x70

## ◆ MPUREG_TMD5_B2

#define MPUREG_TMD5_B2 0x71

## ◆ MPUREG_TMD6_B2

#define MPUREG_TMD6_B2 0x72

## ◆ MPUREG_TMD7_B2

#define MPUREG_TMD7_B2 0x73

## ◆ MPUREG_TMST_CONFIG

#define MPUREG_TMST_CONFIG 0x54

## ◆ MPUREG_TMST_FSYNC1

#define MPUREG_TMST_FSYNC1 MPUREG_TMST_FSYNCH

## ◆ MPUREG_TMST_FSYNCH

#define MPUREG_TMST_FSYNCH 0x2B

## ◆ MPUREG_TMST_VAL0_B1

#define MPUREG_TMST_VAL0_B1 0x62

## ◆ MPUREG_WHO_AM_I

#define MPUREG_WHO_AM_I 0x75

## ◆ MPUREG_XA_ST_DATA_B2

#define MPUREG_XA_ST_DATA_B2 0x3B

## ◆ MPUREG_XG_ST_DATA_B1

#define MPUREG_XG_ST_DATA_B1 0x5F

## ◆ MPUREG_YA_ST_DATA_B2

#define MPUREG_YA_ST_DATA_B2 0x3C

## ◆ MPUREG_YG_ST_DATA_B1

#define MPUREG_YG_ST_DATA_B1 0x60

## ◆ MPUREG_ZA_ST_DATA_B2

#define MPUREG_ZA_ST_DATA_B2 0x3D

## ◆ MPUREG_ZG_ST_DATA_B1

#define MPUREG_ZG_ST_DATA_B1 0x61

## ◆ TEMP_DATA_SIZE

#define TEMP_DATA_SIZE 2

## Enumeration Type Documentation

## ◆ ICM426XX_ACCEL_AAF_DIS_t

enum ICM426XX_ACCEL_AAF_DIS_t

Enumerator
ICM426XX_ACCEL_AAF_EN |
ICM426XX_ACCEL_AAF_DIS |

## ◆ ICM426XX_ACCEL_CONFIG0_FS_SEL_t

enum ICM426XX_ACCEL_CONFIG0_FS_SEL_t

Accelerometer FSR selection.

Enumerator
ICM426XX_ACCEL_CONFIG0_FS_SEL_RESERVED |
ICM426XX_ACCEL_CONFIG0_FS_SEL_2g | 2g
ICM426XX_ACCEL_CONFIG0_FS_SEL_4g | 4g
ICM426XX_ACCEL_CONFIG0_FS_SEL_8g | 8g
ICM426XX_ACCEL_CONFIG0_FS_SEL_16g | 16g

## ◆ ICM426XX_ACCEL_CONFIG0_ODR_t

enum ICM426XX_ACCEL_CONFIG0_ODR_t

Accelerometer ODR selection.

Enumerator
ICM426XX_ACCEL_CONFIG0_ODR_500_HZ | 500 Hz (2 ms)
ICM426XX_ACCEL_CONFIG0_ODR_1_5625_HZ | 1.5625 Hz (640 ms)
ICM426XX_ACCEL_CONFIG0_ODR_3_125_HZ | 3.125 Hz (320 ms)
ICM426XX_ACCEL_CONFIG0_ODR_6_25_HZ | 6.25 Hz (160 ms)
ICM426XX_ACCEL_CONFIG0_ODR_12_5_HZ | 12.5 Hz (80 ms)
ICM426XX_ACCEL_CONFIG0_ODR_25_HZ | 25 Hz (40 ms)
ICM426XX_ACCEL_CONFIG0_ODR_50_HZ | 50 Hz (20 ms)
ICM426XX_ACCEL_CONFIG0_ODR_100_HZ | 100 Hz (10 ms)
ICM426XX_ACCEL_CONFIG0_ODR_200_HZ | 200 Hz (5 ms)
ICM426XX_ACCEL_CONFIG0_ODR_1_KHZ | 1 KHz (1 ms)
ICM426XX_ACCEL_CONFIG0_ODR_2_KHZ | 2 KHz (500 us)
ICM426XX_ACCEL_CONFIG0_ODR_4_KHZ | 4 KHz (250 us)
ICM426XX_ACCEL_CONFIG0_ODR_8_KHZ | 8 KHz (125 us)
ICM426XX_ACCEL_CONFIG0_ODR_16_KHZ | 16 KHz (62.5 us)
ICM426XX_ACCEL_CONFIG0_ODR_32_KHZ | 32 KHz (31.25 us)

## ◆ ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_t

enum ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_t

Enumerator
ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_1ST_ORDER |
ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_2ND_ORDER |
ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_3RD_ORDER |

## ◆ ICM426XX_APEX_CONFIG0_DMP_ODR_t

enum ICM426XX_APEX_CONFIG0_DMP_ODR_t

DMP ODR selection.

Enumerator
ICM426XX_APEX_CONFIG0_DMP_ODR_25Hz | 25Hz (40ms)
ICM426XX_APEX_CONFIG0_DMP_ODR_50Hz | 50Hz (20ms)
ICM426XX_APEX_CONFIG0_DMP_ODR_100Hz | 100Hz (10ms)
ICM426XX_APEX_CONFIG0_DMP_ODR_500Hz | 500Hz (40ms)

## ◆ ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_t

enum ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_t

Enumerator
ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_EN |
ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_DIS |

## ◆ ICM426XX_APEX_CONFIG0_PEDO_EN_t

enum ICM426XX_APEX_CONFIG0_PEDO_EN_t

Enumerator
ICM426XX_APEX_CONFIG0_PEDO_EN_EN |
ICM426XX_APEX_CONFIG0_PEDO_EN_DIS |

## ◆ ICM426XX_APEX_CONFIG0_R2W_EN_t

enum ICM426XX_APEX_CONFIG0_R2W_EN_t

Enumerator
ICM426XX_APEX_CONFIG0_R2W_EN_EN |
ICM426XX_APEX_CONFIG0_R2W_EN_DIS |

## ◆ ICM426XX_APEX_CONFIG0_TAP_ENABLE_t

enum ICM426XX_APEX_CONFIG0_TAP_ENABLE_t

Enumerator
ICM426XX_APEX_CONFIG0_TAP_ENABLE_EN |
ICM426XX_APEX_CONFIG0_TAP_ENABLE_DIS |

## ◆ ICM426XX_APEX_CONFIG0_TILT_EN_t

enum ICM426XX_APEX_CONFIG0_TILT_EN_t

Enumerator
ICM426XX_APEX_CONFIG0_TILT_EN_EN |
ICM426XX_APEX_CONFIG0_TILT_EN_DIS |

## ◆ ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t

enum ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t

Enumerator
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_0S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_4S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_8S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_12S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_16S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_20S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_24S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_28S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_32S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_36S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_40S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_44S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_48S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_52S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_56S |
ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_60S |

## ◆ ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t

enum ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t

Enumerator
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_30MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_35MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_40MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_45MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_50MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_55MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_60MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_65MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_70MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_75MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_80MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_85MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_90MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_95MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_100MG |
ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_105MG |

## ◆ ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_t

enum ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_t

Enumerator
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_30MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_34MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_38MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_42MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_46MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_50MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_54MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_58MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_62MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_66MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_70MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_74MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_78MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_82MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_86MG |
ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_90MG |

## ◆ ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t

enum ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t

Enumerator
ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_90 |
ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_107 |
ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_136 |
ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_159 |

## ◆ ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t

enum ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t

Enumerator
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_50_SAMPLES |
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_75_SAMPLES |
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_100_SAMPLES |
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_125_SAMPLES |
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_150_SAMPLES |
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_175_SAMPLES |
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_200_SAMPLES |
ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_225_SAMPLES |

## ◆ ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t

enum ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t

Enumerator
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_1_28S |
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_2_56S |
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_3_84S |
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_5_12S |
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_6_4S |
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_7_68S |
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_8_96S |
ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_10_24S |

## ◆ ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_t

enum ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_t

Enumerator
ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_0S |
ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_2S |
ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_4S |
ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_6S |

## ◆ ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t

enum ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t

Enumerator
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_0 |
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_1 |
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_2 |
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_3 |
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_4 |
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_5 |
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_6 |
ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_7 |

## ◆ ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t

enum ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t

Enumerator
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_32S |
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_64S |
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_96S |
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_28S |
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_6S |
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_92S |
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_24S |
ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_56S |

## ◆ ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t

enum ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t

Enumerator
ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_12 |
ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_25 |
ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_37 |
ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_50 |

## ◆ ICM426XX_APEX_CONFIG8_TAP_TAVG_t

enum ICM426XX_APEX_CONFIG8_TAP_TAVG_t

Enumerator
ICM426XX_APEX_CONFIG8_TAP_TAVG_1SAMPLE |
ICM426XX_APEX_CONFIG8_TAP_TAVG_2SAMPLE |
ICM426XX_APEX_CONFIG8_TAP_TAVG_4SAMPLE |
ICM426XX_APEX_CONFIG8_TAP_TAVG_8SAMPLE |

## ◆ ICM426XX_APEX_CONFIG8_TAP_TMAX_t

enum ICM426XX_APEX_CONFIG8_TAP_TMAX_t

Enumerator
ICM426XX_APEX_CONFIG8_TAP_TMAX_250MS |
ICM426XX_APEX_CONFIG8_TAP_TMAX_375MS |
ICM426XX_APEX_CONFIG8_TAP_TMAX_500MS |
ICM426XX_APEX_CONFIG8_TAP_TMAX_625MS |

## ◆ ICM426XX_APEX_CONFIG8_TAP_TMIN_t

enum ICM426XX_APEX_CONFIG8_TAP_TMIN_t

Enumerator
ICM426XX_APEX_CONFIG8_TAP_TMIN_125MS |
ICM426XX_APEX_CONFIG8_TAP_TMIN_140MS |
ICM426XX_APEX_CONFIG8_TAP_TMIN_156MS |
ICM426XX_APEX_CONFIG8_TAP_TMIN_171MS |
ICM426XX_APEX_CONFIG8_TAP_TMIN_187MS |
ICM426XX_APEX_CONFIG8_TAP_TMIN_203MS |
ICM426XX_APEX_CONFIG8_TAP_TMIN_218MS |
ICM426XX_APEX_CONFIG8_TAP_TMIN_234MS |

## ◆ ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_t

enum ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_t

Enumerator
ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_NORMAL |
ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_RESERVED |

## ◆ ICM426XX_APEX_DATA3_ACTIVITY_CLASS_t

enum ICM426XX_APEX_DATA3_ACTIVITY_CLASS_t

Enumerator
ICM426XX_APEX_DATA3_ACTIVITY_CLASS_OTHER |
ICM426XX_APEX_DATA3_ACTIVITY_CLASS_WALK |
ICM426XX_APEX_DATA3_ACTIVITY_CLASS_RUN |

## ◆ ICM426XX_APEX_DATA3_DMP_IDLE_OFF_t

enum ICM426XX_APEX_DATA3_DMP_IDLE_OFF_t

Enumerator
ICM426XX_APEX_DATA3_DMP_IDLE_ON |
ICM426XX_APEX_DATA3_DMP_IDLE_OFF |

## ◆ ICM426XX_APEX_DATA4_TAP_AXIS_t

enum ICM426XX_APEX_DATA4_TAP_AXIS_t

Enumerator
ICM426XX_APEX_DATA4_TAP_AXIS_Z |
ICM426XX_APEX_DATA4_TAP_AXIS_Y |
ICM426XX_APEX_DATA4_TAP_AXIS_X |

## ◆ ICM426XX_APEX_DATA4_TAP_DIR_t

enum ICM426XX_APEX_DATA4_TAP_DIR_t

Enumerator
ICM426XX_APEX_DATA4_TAP_DIR_POSITIVE |
ICM426XX_APEX_DATA4_TAP_DIR_NEGATIVE |

## ◆ ICM426XX_APEX_DATA4_TAP_NUM_t

enum ICM426XX_APEX_DATA4_TAP_NUM_t

Enumerator
ICM426XX_APEX_DATA4_TAP_NUM_DOUBLE |
ICM426XX_APEX_DATA4_TAP_NUM_SINGLE |

## ◆ ICM426XX_CHIP_CONFIG_RESET_t

enum ICM426XX_CHIP_CONFIG_RESET_t

Enumerator
ICM426XX_CHIP_CONFIG_RESET_EN |
ICM426XX_CHIP_CONFIG_RESET_NONE |

## ◆ ICM426XX_CHIP_CONFIG_SPI_MODE_t

enum ICM426XX_CHIP_CONFIG_SPI_MODE_t

Enumerator
ICM426XX_CHIP_CONFIG_SPI_MODE_1_2 |
ICM426XX_CHIP_CONFIG_SPI_MODE_0_3 |

## ◆ ICM426XX_DEVICE_CONFIG_RESET_t

enum ICM426XX_DEVICE_CONFIG_RESET_t

Enumerator
ICM426XX_DEVICE_CONFIG_RESET_EN |
ICM426XX_DEVICE_CONFIG_RESET_NONE |

## ◆ ICM426XX_DEVICE_CONFIG_SPI_MODE_t

enum ICM426XX_DEVICE_CONFIG_SPI_MODE_t

Enumerator
ICM426XX_DEVICE_CONFIG_SPI_MODE_1_2 |
ICM426XX_DEVICE_CONFIG_SPI_MODE_0_3 |

## ◆ ICM426XX_FIFO_CONFIG1_ACCEL_t

enum ICM426XX_FIFO_CONFIG1_ACCEL_t

Enumerator
ICM426XX_FIFO_CONFIG1_ACCEL_EN |
ICM426XX_FIFO_CONFIG1_ACCEL_DIS |

## ◆ ICM426XX_FIFO_CONFIG1_GYRO_t

enum ICM426XX_FIFO_CONFIG1_GYRO_t

Enumerator
ICM426XX_FIFO_CONFIG1_GYRO_EN |
ICM426XX_FIFO_CONFIG1_GYRO_DIS |

## ◆ ICM426XX_FIFO_CONFIG1_HIRES_t

enum ICM426XX_FIFO_CONFIG1_HIRES_t

Enumerator
ICM426XX_FIFO_CONFIG1_HIRES_EN |
ICM426XX_FIFO_CONFIG1_HIRES_DIS |

## ◆ ICM426XX_FIFO_CONFIG1_TEMP_t

enum ICM426XX_FIFO_CONFIG1_TEMP_t

Enumerator
ICM426XX_FIFO_CONFIG1_TEMP_EN |
ICM426XX_FIFO_CONFIG1_TEMP_DIS |

## ◆ ICM426XX_FIFO_CONFIG1_TMST_FSYNC_t

enum ICM426XX_FIFO_CONFIG1_TMST_FSYNC_t

Enumerator
ICM426XX_FIFO_CONFIG1_TMST_FSYNC_EN |
ICM426XX_FIFO_CONFIG1_TMST_FSYNC_DIS |

## ◆ ICM426XX_FIFO_CONFIG1_WM_GT_t

enum ICM426XX_FIFO_CONFIG1_WM_GT_t

Enumerator
ICM426XX_FIFO_CONFIG1_WM_GT_TH_EN |
ICM426XX_FIFO_CONFIG1_WM_GT_TH_DIS |

## ◆ ICM426XX_FIFO_CONFIG_MODE_t

enum ICM426XX_FIFO_CONFIG_MODE_t

Enumerator
ICM426XX_FIFO_CONFIG_MODE_STOP_ON_FULL |
ICM426XX_FIFO_CONFIG_MODE_STREAM |
ICM426XX_FIFO_CONFIG_MODE_BYPASS |

## ◆ ICM426XX_FSYNC_CONFIG_UI_SEL_t

enum ICM426XX_FSYNC_CONFIG_UI_SEL_t

Enumerator
ICM426XX_FSYNC_CONFIG_UI_SEL_NO |
ICM426XX_FSYNC_CONFIG_UI_SEL_TEMP |
ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_X |
ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_Y |
ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_Z |
ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_X |
ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_Y |
ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_Z |

## ◆ ICM426XX_GYRO_AAF_DIS_t

enum ICM426XX_GYRO_AAF_DIS_t

Enumerator
ICM426XX_GYRO_AAF_EN |
ICM426XX_GYRO_AAF_DIS |

## ◆ ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t

enum ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t

Enumerator
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_16 |
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_1 |

## ◆ ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t

enum ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t

Enumerator
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_40 |
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_20 |
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_16 |
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_10 |
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_8 |
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_5 |
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_4 |
ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_2 |

## ◆ ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t

enum ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t

Enumerator
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_40 |
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_20 |
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_16 |
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_10 |
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_8 |
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_5 |
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_4 |
ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_2 |

## ◆ ICM426XX_GYRO_CONFIG0_FS_SEL_t

enum ICM426XX_GYRO_CONFIG0_FS_SEL_t

Gyroscope FSR selection.

Enumerator
ICM426XX_GYRO_CONFIG0_FS_SEL_16dps | 16dps
ICM426XX_GYRO_CONFIG0_FS_SEL_31dps | 31dps
ICM426XX_GYRO_CONFIG0_FS_SEL_62dps | 62dps
ICM426XX_GYRO_CONFIG0_FS_SEL_125dps | 125dps
ICM426XX_GYRO_CONFIG0_FS_SEL_250dps | 250dps
ICM426XX_GYRO_CONFIG0_FS_SEL_500dps | 500dps
ICM426XX_GYRO_CONFIG0_FS_SEL_1000dps | 1000dps
ICM426XX_GYRO_CONFIG0_FS_SEL_2000dps | 2000dps

## ◆ ICM426XX_GYRO_CONFIG0_ODR_t

enum ICM426XX_GYRO_CONFIG0_ODR_t

Gyroscope ODR selection.

Enumerator
ICM426XX_GYRO_CONFIG0_ODR_500_HZ | 500 Hz (2 ms)
ICM426XX_GYRO_CONFIG0_ODR_12_5_HZ | 12.5 Hz (80 ms)
ICM426XX_GYRO_CONFIG0_ODR_25_HZ | 25 Hz (40 ms)
ICM426XX_GYRO_CONFIG0_ODR_50_HZ | 50 Hz (20 ms)
ICM426XX_GYRO_CONFIG0_ODR_100_HZ | 100 Hz (10 ms)
ICM426XX_GYRO_CONFIG0_ODR_200_HZ | 200 Hz (5 ms)
ICM426XX_GYRO_CONFIG0_ODR_1_KHZ | 1 KHz (1 ms)
ICM426XX_GYRO_CONFIG0_ODR_2_KHZ | 2 KHz (500 us)
ICM426XX_GYRO_CONFIG0_ODR_4_KHZ | 4 KHz (250 us)
ICM426XX_GYRO_CONFIG0_ODR_8_KHZ | 8 KHz (125 us)
ICM426XX_GYRO_CONFIG0_ODR_16_KHZ | 16 KHz (62.5 us)
ICM426XX_GYRO_CONFIG0_ODR_32_KHZ | 32 KHz (31.25 us)

## ◆ ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_t

enum ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_t

Enumerator
ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_1ST_ORDER |
ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_2ND_ORDER |
ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_3RD_ORDER |

## ◆ ICM426XX_GYRO_NF_DIS_t

enum ICM426XX_GYRO_NF_DIS_t

Enumerator
ICM426XX_GYRO_NF_EN |
ICM426XX_GYRO_NF_DIS |

## ◆ ICM426XX_INT_CONFIG1_ASY_RST_t

enum ICM426XX_INT_CONFIG1_ASY_RST_t

Enumerator
ICM426XX_INT_CONFIG1_ASY_RST_DISABLED |
ICM426XX_INT_CONFIG1_ASY_RST_ENABLED |

## ◆ ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t

enum ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t

Enumerator
ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_PP |
ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_OD |

## ◆ ICM426XX_INT_CONFIG_INT1_POLARITY_t

enum ICM426XX_INT_CONFIG_INT1_POLARITY_t

Enumerator
ICM426XX_INT_CONFIG_INT1_POLARITY_HIGH |
ICM426XX_INT_CONFIG_INT1_POLARITY_LOW |

## ◆ ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_t

enum ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_t

Enumerator
ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_PP |
ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_OD |

## ◆ ICM426XX_INT_CONFIG_INT2_POLARITY_t

enum ICM426XX_INT_CONFIG_INT2_POLARITY_t

Enumerator
ICM426XX_INT_CONFIG_INT2_POLARITY_HIGH |
ICM426XX_INT_CONFIG_INT2_POLARITY_LOW |

## ◆ ICM426XX_INT_TDEASSERT_t

enum ICM426XX_INT_TDEASSERT_t

Enumerator
ICM426XX_INT_TDEASSERT_DISABLED |
ICM426XX_INT_TDEASSERT_ENABLED |

## ◆ ICM426XX_INT_TPULSE_DURATION_t

enum ICM426XX_INT_TPULSE_DURATION_t

Enumerator
ICM426XX_INT_TPULSE_DURATION_8_US |
ICM426XX_INT_TPULSE_DURATION_100_US |

## ◆ ICM426XX_INTF_CONFIG0_DATA_ENDIAN_t

enum ICM426XX_INTF_CONFIG0_DATA_ENDIAN_t

Enumerator
ICM426XX_INTF_CONFIG0_DATA_BIG_ENDIAN |
ICM426XX_INTF_CONFIG0_DATA_LITTLE_ENDIAN |

## ◆ ICM426XX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t

enum ICM426XX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t

Enumerator
ICM426XX_INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN |
ICM426XX_INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN |

## ◆ ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_t

enum ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_t

Enumerator
ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_RECORD |
ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_BYTE |

## ◆ ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t

enum ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t

Enumerator
ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_DIS |
ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_EN |

## ◆ ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_t

enum ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_t

Enumerator
ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_1_2 |
ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_0_3 |

## ◆ ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_t

enum ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_t

Enumerator
ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_1_2 |
ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_0_3 |

## ◆ ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_t

enum ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_t

Enumerator
ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_WUOSC |
ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_RCOSC |

## ◆ ICM426XX_INTF_CONFIG1_RTC_MODE_t

enum ICM426XX_INTF_CONFIG1_RTC_MODE_t

Enumerator
ICM426XX_INTF_CONFIG1_RTC_MODE_DIS |
ICM426XX_INTF_CONFIG1_RTC_MODE_EN |

## ◆ ICM426XX_INTF_CONFIG4_AP_SPI_t

enum ICM426XX_INTF_CONFIG4_AP_SPI_t

Enumerator
ICM426XX_INTF_CONFIG4_AP_SPI4W |
ICM426XX_INTF_CONFIG4_AP_SPI3W |

## ◆ ICM426XX_INTF_CONFIG4_AUX1_SPI_t

enum ICM426XX_INTF_CONFIG4_AUX1_SPI_t

Enumerator
ICM426XX_INTF_CONFIG4_AUX1_SPI4W |
ICM426XX_INTF_CONFIG4_AUX1_SPI3W |

## ◆ ICM426XX_OIS1_CONFIG1_ACCEL_EN_t

enum ICM426XX_OIS1_CONFIG1_ACCEL_EN_t

Enumerator
ICM426XX_OIS1_CONFIG1_ACCEL_EN |
ICM426XX_OIS1_CONFIG1_ACCEL_DIS |

## ◆ ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_t

enum ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_t

Enumerator
ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC |
ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC |

## ◆ ICM426XX_OIS1_CONFIG1_DEC_t

enum ICM426XX_OIS1_CONFIG1_DEC_t

OIS1 rate selection (base clock fixed by OTP divided by decimator value)

Enumerator
ICM426XX_OIS1_CONFIG1_DEC_1 | OTP_OIS_clock / 1.
ICM426XX_OIS1_CONFIG1_DEC_2 | OTP_OIS_clock / 2.
ICM426XX_OIS1_CONFIG1_DEC_4 | OTP_OIS_clock / 4.
ICM426XX_OIS1_CONFIG1_DEC_8 | OTP_OIS_clock / 8.
ICM426XX_OIS1_CONFIG1_DEC_16 | OTP_OIS_clock / 16.
ICM426XX_OIS1_CONFIG1_DEC_32 | OTP_OIS_clock / 32.

## ◆ ICM426XX_OIS1_CONFIG1_GYRO_EN_t

enum ICM426XX_OIS1_CONFIG1_GYRO_EN_t

Enumerator
ICM426XX_OIS1_CONFIG1_GYRO_EN |
ICM426XX_OIS1_CONFIG1_GYRO_DIS |

## ◆ ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_t

enum ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_t

OIS1 accelerometer FSR selection.

Enumerator
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_RESERVED |
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_2g | 2g
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_4g | 4g
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_8g | 8g
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_16g | 16g

## ◆ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_t

enum ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_t

OIS1 gyroscope FSR selection.

Enumerator
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_16dps | 15.625 dps
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_31dps | 31.25 dps
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_62dps | 62.5 dps
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_125dps | 125 dps
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_250dps | 250 dps
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_500dps | 500 dps
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_1000dps | 1000 dps
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_2000dps | 2000 dps

## ◆ ICM426XX_OIS2_CONFIG1_ACCEL_EN_t

enum ICM426XX_OIS2_CONFIG1_ACCEL_EN_t

Enumerator
ICM426XX_OIS2_CONFIG1_ACCEL_EN |
ICM426XX_OIS2_CONFIG1_ACCEL_DIS |

## ◆ ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_t

enum ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_t

Enumerator
ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC |
ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC |

## ◆ ICM426XX_OIS2_CONFIG1_DEC_t

enum ICM426XX_OIS2_CONFIG1_DEC_t

OIS2 rate selection (base clock fixed by OTP divided by decimator value)

Enumerator
ICM426XX_OIS2_CONFIG1_DEC_1 | OTP_OIS_clock / 1.
ICM426XX_OIS2_CONFIG1_DEC_2 | OTP_OIS_clock / 2.
ICM426XX_OIS2_CONFIG1_DEC_4 | OTP_OIS_clock / 4.
ICM426XX_OIS2_CONFIG1_DEC_8 | OTP_OIS_clock / 8.
ICM426XX_OIS2_CONFIG1_DEC_16 | OTP_OIS_clock / 16.
ICM426XX_OIS2_CONFIG1_DEC_32 | OTP_OIS_clock / 32.

## ◆ ICM426XX_OIS2_CONFIG1_GYRO_EN_t

enum ICM426XX_OIS2_CONFIG1_GYRO_EN_t

Enumerator
ICM426XX_OIS2_CONFIG1_GYRO_EN |
ICM426XX_OIS2_CONFIG1_GYRO_DIS |

## ◆ ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_t

enum ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_t

OIS2 accelerometer FSR selection.

Enumerator
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_RESERVED |
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_2g | 2g
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_4g | 4g
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_8g | 8g
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_16g | 16g

## ◆ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_t

enum ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_t

OIS2 gyroscope FSR selection.

Enumerator
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_16dps | 15.625 dps
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_31dps | 31.25 dps
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_62dps | 62.5 dps
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_125dps | 125 dps
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_250dps | 250 dps
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_500dps | 500 dps
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_1000dps | 1000 dps
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_2000dps | 2000 dps

## ◆ ICM426XX_PWR_MGMT_0_ACCEL_MODE_t

enum ICM426XX_PWR_MGMT_0_ACCEL_MODE_t

Enumerator
ICM426XX_PWR_MGMT_0_ACCEL_MODE_LN |
ICM426XX_PWR_MGMT_0_ACCEL_MODE_LP |
ICM426XX_PWR_MGMT_0_ACCEL_MODE_OFF |

## ◆ ICM426XX_PWR_MGMT_0_GYRO_MODE_t

enum ICM426XX_PWR_MGMT_0_GYRO_MODE_t

Enumerator
ICM426XX_PWR_MGMT_0_GYRO_MODE_LN |
ICM426XX_PWR_MGMT_0_GYRO_MODE_STANDBY |
ICM426XX_PWR_MGMT_0_GYRO_MODE_OFF |

## ◆ ICM426XX_PWR_MGMT_0_IDLE_t

enum ICM426XX_PWR_MGMT_0_IDLE_t

Enumerator
ICM426XX_PWR_MGMT_0_IDLE_DIS |
ICM426XX_PWR_MGMT_0_IDLE_EN |

## ◆ ICM426XX_PWR_MGMT_0_TEMP_t

enum ICM426XX_PWR_MGMT_0_TEMP_t

Enumerator
ICM426XX_PWR_MGMT_0_TEMP_DIS |
ICM426XX_PWR_MGMT_0_TEMP_EN |

## ◆ ICM426XX_SENSOR_CONFIG2_OIS_MODE_t

enum ICM426XX_SENSOR_CONFIG2_OIS_MODE_t

Enumerator
ICM426XX_SENSOR_CONFIG2_OIS_MODE_32KHZ |
ICM426XX_SENSOR_CONFIG2_OIS_MODE_8KHZ |
ICM426XX_SENSOR_CONFIG2_OIS_MODE_DIS |

## ◆ ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_t

enum ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_t

Enumerator
ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_EN |
ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_DIS |

## ◆ ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_t

enum ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_t

Enumerator
ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN |
ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_DIS |

## ◆ ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_t

enum ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_t

Enumerator
ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_EN |
ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_DIS |

## ◆ ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_t

enum ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_t

Enumerator
ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_EN |
ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_DIS |

## ◆ ICM426XX_SMD_CONFIG_SMD_MODE_t

enum ICM426XX_SMD_CONFIG_SMD_MODE_t

Enumerator
ICM426XX_SMD_CONFIG_SMD_MODE_LONG |
ICM426XX_SMD_CONFIG_SMD_MODE_SHORT |
ICM426XX_SMD_CONFIG_SMD_MODE_WOM |
ICM426XX_SMD_CONFIG_SMD_MODE_DISABLED |

## ◆ ICM426XX_SMD_CONFIG_WOM_INT_MODE_t

enum ICM426XX_SMD_CONFIG_WOM_INT_MODE_t

Enumerator
ICM426XX_SMD_CONFIG_WOM_INT_MODE_ANDED |
ICM426XX_SMD_CONFIG_WOM_INT_MODE_ORED |

## ◆ ICM426XX_SMD_CONFIG_WOM_MODE_t

enum ICM426XX_SMD_CONFIG_WOM_MODE_t

Enumerator
ICM426XX_SMD_CONFIG_WOM_MODE_CMP_PREV |
ICM426XX_SMD_CONFIG_WOM_MODE_CMP_INIT |

## ◆ ICM426XX_TMST_CONFIG_RESOL_t

enum ICM426XX_TMST_CONFIG_RESOL_t

Enumerator
ICM426XX_TMST_CONFIG_RESOL_16us |
ICM426XX_TMST_CONFIG_RESOL_1us |

## ◆ ICM426XX_TMST_CONFIG_TMST_EN_t

enum ICM426XX_TMST_CONFIG_TMST_EN_t

Enumerator
ICM426XX_TMST_CONFIG_TMST_EN |
ICM426XX_TMST_CONFIG_TMST_DIS |

## ◆ ICM426XX_TMST_CONFIG_TMST_FSYNC_EN_t

enum ICM426XX_TMST_CONFIG_TMST_FSYNC_EN_t

Enumerator
ICM426XX_TMST_CONFIG_TMST_FSYNC_EN |
ICM426XX_TMST_CONFIG_TMST_FSYNC_DIS |

## ◆ ICM426XX_TMST_CONFIG_TMST_TO_REGS_EN_t

enum ICM426XX_TMST_CONFIG_TMST_TO_REGS_EN_t

Enumerator
ICM426XX_TMST_CONFIG_TMST_TO_REGS_EN |
ICM426XX_TMST_CONFIG_TMST_TO_REGS_DIS |