| ICM42688V eMD Driver 2.0.9 Documentation of the eMD Driver API

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### - b -

- BIT_ACCEL_AAF_BITSHIFT_MASK : Icm426xxDefs.h
- BIT_ACCEL_AAF_BITSHIFT_POS : Icm426xxDefs.h
- BIT_ACCEL_AAF_DELT_MASK : Icm426xxDefs.h
- BIT_ACCEL_AAF_DELT_POS : Icm426xxDefs.h
- BIT_ACCEL_AAF_DELTSQR_MASK_HI : Icm426xxDefs.h
- BIT_ACCEL_AAF_DELTSQR_MASK_LO : Icm426xxDefs.h
- BIT_ACCEL_AAF_DELTSQR_POS_HI : Icm426xxDefs.h
- BIT_ACCEL_AAF_DELTSQR_POS_LO : Icm426xxDefs.h
- BIT_ACCEL_AAF_DIS_MASK : Icm426xxDefs.h
- BIT_ACCEL_AAF_DIS_POS : Icm426xxDefs.h
- BIT_ACCEL_CONFIG0_FS_SEL_MASK : Icm426xxDefs.h
- BIT_ACCEL_CONFIG0_FS_SEL_POS : Icm426xxDefs.h
- BIT_ACCEL_CONFIG0_ODR_MASK : Icm426xxDefs.h
- BIT_ACCEL_CONFIG0_ODR_POS : Icm426xxDefs.h
- BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_MASK : Icm426xxDefs.h
- BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS : Icm426xxDefs.h
- BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_MASK : Icm426xxDefs.h
- BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS : Icm426xxDefs.h
- BIT_ACCEL_LP_CLK_SEL_MASK : Icm426xxDefs.h
- BIT_ACCEL_LP_CLK_SEL_POS : Icm426xxDefs.h
- BIT_ACCEL_X_OFFUSER_MASK_HI : Icm426xxDefs.h
- BIT_ACCEL_X_OFFUSER_MASK_LO : Icm426xxDefs.h
- BIT_ACCEL_X_OFFUSER_POS_HI : Icm426xxDefs.h
- BIT_ACCEL_X_OFFUSER_POS_LO : Icm426xxDefs.h
- BIT_ACCEL_X_ST_EN : Icm426xxDefs.h
- BIT_ACCEL_Y_OFFUSER_MASK_HI : Icm426xxDefs.h
- BIT_ACCEL_Y_OFFUSER_MASK_LO : Icm426xxDefs.h
- BIT_ACCEL_Y_OFFUSER_POS_HI : Icm426xxDefs.h
- BIT_ACCEL_Y_OFFUSER_POS_LO : Icm426xxDefs.h
- BIT_ACCEL_Y_ST_EN : Icm426xxDefs.h
- BIT_ACCEL_Z_OFFUSER_MASK_HI : Icm426xxDefs.h
- BIT_ACCEL_Z_OFFUSER_MASK_LO : Icm426xxDefs.h
- BIT_ACCEL_Z_OFFUSER_POS_HI : Icm426xxDefs.h
- BIT_ACCEL_Z_OFFUSER_POS_LO : Icm426xxDefs.h
- BIT_ACCEL_Z_ST_EN : Icm426xxDefs.h
- BIT_APEX_CONFIG0_DMP_ODR_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG0_DMP_ODR_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG0_DMP_POWER_SAVE_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG0_PEDO_EN_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG0_PEDO_EN_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG0_R2W_EN_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG0_R2W_EN_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG0_TAP_ENABLE_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG0_TAP_ENABLE_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG0_TILT_EN_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG0_TILT_EN_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG2_PEDO_AMP_TH_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG2_PEDO_AMP_TH_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG4_TILT_WAIT_TIME_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG8_TAP_TAVG_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG8_TAP_TAVG_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG8_TAP_TMAX_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG8_TAP_TMAX_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG8_TAP_TMIN_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG8_TAP_TMIN_POS : Icm426xxDefs.h
- BIT_APEX_CONFIG9_SENSITIVITY_MODE_MASK : Icm426xxDefs.h
- BIT_APEX_CONFIG9_SENSITIVITY_MODE_POS : Icm426xxDefs.h
- BIT_APEX_DATA3_ACTIVITY_CLASS_MASK : Icm426xxDefs.h
- BIT_APEX_DATA3_ACTIVITY_CLASS_POS : Icm426xxDefs.h
- BIT_APEX_DATA3_DMP_IDLE_MASK : Icm426xxDefs.h
- BIT_APEX_DATA3_DMP_IDLE_POS : Icm426xxDefs.h
- BIT_APEX_DATA4_TAP_AXIS_MASK : Icm426xxDefs.h
- BIT_APEX_DATA4_TAP_AXIS_POS : Icm426xxDefs.h
- BIT_APEX_DATA4_TAP_DIR_MASK : Icm426xxDefs.h
- BIT_APEX_DATA4_TAP_DIR_POS : Icm426xxDefs.h
- BIT_APEX_DATA4_TAP_NUM_MASK : Icm426xxDefs.h
- BIT_APEX_DATA4_TAP_NUM_POS : Icm426xxDefs.h
- BIT_APEX_DATA5_DOUBLE_TAP_TIMING_MASK : Icm426xxDefs.h
- BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS : Icm426xxDefs.h
- BIT_CHIP_CONFIG_RESET_MASK : Icm426xxDefs.h
- BIT_CHIP_CONFIG_RESET_POS : Icm426xxDefs.h
- BIT_CHIP_CONFIG_SPI_MODE_MASK : Icm426xxDefs.h
- BIT_CHIP_CONFIG_SPI_MODE_POS : Icm426xxDefs.h
- BIT_DATA_ENDIAN_MASK : Icm426xxDefs.h
- BIT_DATA_ENDIAN_POS : Icm426xxDefs.h
- BIT_DEVICE_CONFIG_RESET_MASK : Icm426xxDefs.h
- BIT_DEVICE_CONFIG_RESET_POS : Icm426xxDefs.h
- BIT_DEVICE_CONFIG_SPI_MODE_MASK : Icm426xxDefs.h
- BIT_DEVICE_CONFIG_SPI_MODE_POS : Icm426xxDefs.h
- BIT_DMP_MEM_ACCESS_EN : Icm426xxDefs.h
- BIT_FDR_CONFIG_FDR_SEL_MASK : Icm426xxDefs.h
- BIT_FDR_CONFIG_FDR_SEL_POS : Icm426xxDefs.h
- BIT_FIFO_CONFIG1_ACCEL_MASK : Icm426xxDefs.h
- BIT_FIFO_CONFIG1_ACCEL_POS : Icm426xxDefs.h
- BIT_FIFO_CONFIG1_GYRO_MASK : Icm426xxDefs.h
- BIT_FIFO_CONFIG1_GYRO_POS : Icm426xxDefs.h
- BIT_FIFO_CONFIG1_HIRES_MASK : Icm426xxDefs.h
- BIT_FIFO_CONFIG1_HIRES_POS : Icm426xxDefs.h
- BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_MASK : Icm426xxDefs.h
- BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS : Icm426xxDefs.h
- BIT_FIFO_CONFIG1_TEMP_MASK : Icm426xxDefs.h
- BIT_FIFO_CONFIG1_TEMP_POS : Icm426xxDefs.h
- BIT_FIFO_CONFIG1_TMST_FSYNC_MASK : Icm426xxDefs.h
- BIT_FIFO_CONFIG1_TMST_FSYNC_POS : Icm426xxDefs.h
- BIT_FIFO_CONFIG1_WM_GT_TH_MASK : Icm426xxDefs.h
- BIT_FIFO_CONFIG1_WM_GT_TH_POS : Icm426xxDefs.h
- BIT_FIFO_CONFIG_MODE_MASK : Icm426xxDefs.h
- BIT_FIFO_CONFIG_MODE_POS : Icm426xxDefs.h
- BIT_FIFO_COUNT_ENDIAN_MASK : Icm426xxDefs.h
- BIT_FIFO_COUNT_ENDIAN_POS : Icm426xxDefs.h
- BIT_FIFO_COUNT_REC_MASK : Icm426xxDefs.h
- BIT_FIFO_COUNT_REC_POS : Icm426xxDefs.h
- BIT_FIFO_MEM_RD_SYS : Icm426xxDefs.h
- BIT_FIFO_MEM_WR_SER : Icm426xxDefs.h
- BIT_FIFO_SREG_INVALID_IND_MASK : Icm426xxDefs.h
- BIT_FIFO_SREG_INVALID_IND_POS : Icm426xxDefs.h
- BIT_FSYNC_CONFIG_UI_SEL_MASK : Icm426xxDefs.h
- BIT_FSYNC_CONFIG_UI_SEL_POS : Icm426xxDefs.h
- BIT_GYRO_AAF_BITSHIFT_MASK : Icm426xxDefs.h
- BIT_GYRO_AAF_BITSHIFT_POS : Icm426xxDefs.h
- BIT_GYRO_AAF_DELT_MASK : Icm426xxDefs.h
- BIT_GYRO_AAF_DELT_POS : Icm426xxDefs.h
- BIT_GYRO_AAF_DELTSQR_MASK_HI : Icm426xxDefs.h
- BIT_GYRO_AAF_DELTSQR_MASK_LO : Icm426xxDefs.h
- BIT_GYRO_AAF_DELTSQR_POS_HI : Icm426xxDefs.h
- BIT_GYRO_AAF_DELTSQR_POS_LO : Icm426xxDefs.h
- BIT_GYRO_AAF_DIS_MASK : Icm426xxDefs.h
- BIT_GYRO_AAF_DIS_POS : Icm426xxDefs.h
- BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_MASK : Icm426xxDefs.h
- BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS : Icm426xxDefs.h
- BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_MASK : Icm426xxDefs.h
- BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_POS : Icm426xxDefs.h
- BIT_GYRO_CONFIG0_FS_SEL_MASK : Icm426xxDefs.h
- BIT_GYRO_CONFIG0_FS_SEL_POS : Icm426xxDefs.h
- BIT_GYRO_CONFIG0_ODR_MASK : Icm426xxDefs.h
- BIT_GYRO_CONFIG0_ODR_POS : Icm426xxDefs.h
- BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_MASK : Icm426xxDefs.h
- BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_POS : Icm426xxDefs.h
- BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_MASK : Icm426xxDefs.h
- BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS : Icm426xxDefs.h
- BIT_GYRO_CONFIG1_TEMP_FILT_BW_MASK : Icm426xxDefs.h
- BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS : Icm426xxDefs.h
- BIT_GYRO_NF_DIS_MASK : Icm426xxDefs.h
- BIT_GYRO_NF_DIS_POS : Icm426xxDefs.h
- BIT_GYRO_X_OFFUSER_MASK_HI : Icm426xxDefs.h
- BIT_GYRO_X_OFFUSER_MASK_LO : Icm426xxDefs.h
- BIT_GYRO_X_OFFUSER_POS_HI : Icm426xxDefs.h
- BIT_GYRO_X_OFFUSER_POS_LO : Icm426xxDefs.h
- BIT_GYRO_X_ST_EN : Icm426xxDefs.h
- BIT_GYRO_Y_OFFUSER_MASK_HI : Icm426xxDefs.h
- BIT_GYRO_Y_OFFUSER_MASK_LO : Icm426xxDefs.h
- BIT_GYRO_Y_OFFUSER_POS_HI : Icm426xxDefs.h
- BIT_GYRO_Y_OFFUSER_POS_LO : Icm426xxDefs.h
- BIT_GYRO_Y_ST_EN : Icm426xxDefs.h
- BIT_GYRO_Z_OFFUSER_MASK_HI : Icm426xxDefs.h
- BIT_GYRO_Z_OFFUSER_MASK_LO : Icm426xxDefs.h
- BIT_GYRO_Z_OFFUSER_POS_HI : Icm426xxDefs.h
- BIT_GYRO_Z_OFFUSER_POS_LO : Icm426xxDefs.h
- BIT_GYRO_Z_ST_EN : Icm426xxDefs.h
- BIT_INT_CONFIG1_ASY_RST_MASK : Icm426xxDefs.h
- BIT_INT_CONFIG1_ASY_RST_POS : Icm426xxDefs.h
- BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_MASK : Icm426xxDefs.h
- BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS : Icm426xxDefs.h
- BIT_INT_CONFIG_INT1_POLARITY_MASK : Icm426xxDefs.h
- BIT_INT_CONFIG_INT1_POLARITY_POS : Icm426xxDefs.h
- BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_MASK : Icm426xxDefs.h
- BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS : Icm426xxDefs.h
- BIT_INT_CONFIG_INT2_POLARITY_MASK : Icm426xxDefs.h
- BIT_INT_CONFIG_INT2_POLARITY_POS : Icm426xxDefs.h
- BIT_INT_FIFO_FULL_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_FIFO_FULL_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_FIFO_THS_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_FIFO_THS_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_OIS1_DRDY_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_PLL_RDY_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_PLL_RDY_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_RESET_DONE_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_SLEEP_DET_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_SLEEP_DET_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_SMD_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_SMD_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_SOURCE0_FIFO_FULL_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE0_FIFO_THS_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE0_PLL_RDY_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE0_RESET_DONE_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE0_UI_AGC_RDY_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE0_UI_DRDY_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE0_UI_FSYNC_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE10_SLEEP_DET_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE10_STEP_CNT_OVFL_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE10_STEP_DET_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE10_TAP_DET_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE10_TILT_DET_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE10_WAKE_DET_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE1_SMD_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE1_WOM_X_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE1_WOM_Y_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE1_WOM_Z_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE2_OIS1_AGC_RDY_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE2_OIS1_DRDY_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE2_OIS1_FSYNC_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE2_OIS2_AGC_RDY_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE2_OIS2_DRDY_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE2_OIS2_FSYNC_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE3_FIFO_FULL_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE3_FIFO_THS_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE3_PLL_RDY_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE3_RESET_DONE_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE3_UI_AGC_RDY_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE3_UI_DRDY_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE3_UI_FSYNC_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE4_SMD_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE4_WOM_X_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE4_WOM_Y_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE4_WOM_Z_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE5_OIS1_AGC_RDY_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE5_OIS1_DRDY_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE5_OIS1_FSYNC_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE5_OIS2_AGC_RDY_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE5_OIS2_DRDY_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE5_OIS2_FSYNC_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE6_SLEEP_DET_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE6_STEP_CNT_OVFL_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE6_STEP_DET_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE6_TAP_DET_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE6_TILT_DET_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE6_WAKE_DET_INT1_EN : Icm426xxDefs.h
- BIT_INT_SOURCE7_SLEEP_DET_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE7_STEP_CNT_OVFL_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE7_STEP_DET_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE7_TAP_DET_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE7_TILT_DET_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE7_WAKE_DET_INT2_EN : Icm426xxDefs.h
- BIT_INT_SOURCE8_FIFO_FULL_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE8_FIFO_THS_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE8_OIS1_DRDY_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE8_PLL_RDY_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE8_UI_AGC_RDY_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE8_UI_DRDY_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE8_UI_FSYNC_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE9_SMD_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE9_WOM_X_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE9_WOM_Y_IBI_EN : Icm426xxDefs.h
- BIT_INT_SOURCE9_WOM_Z_IBI_EN : Icm426xxDefs.h
- BIT_INT_STATUS2_SMD_INT : Icm426xxDefs.h
- BIT_INT_STATUS2_WOM_X_INT : Icm426xxDefs.h
- BIT_INT_STATUS2_WOM_Y_INT : Icm426xxDefs.h
- BIT_INT_STATUS2_WOM_Z_INT : Icm426xxDefs.h
- BIT_INT_STATUS3_SLEEP_DET : Icm426xxDefs.h
- BIT_INT_STATUS3_STEP_CNT_OVFL : Icm426xxDefs.h
- BIT_INT_STATUS3_STEP_DET : Icm426xxDefs.h
- BIT_INT_STATUS3_TAP_DET : Icm426xxDefs.h
- BIT_INT_STATUS3_TILT_DET : Icm426xxDefs.h
- BIT_INT_STATUS3_WAKE_DET : Icm426xxDefs.h
- BIT_INT_STATUS_AGC_RDY : Icm426xxDefs.h
- BIT_INT_STATUS_DRDY : Icm426xxDefs.h
- BIT_INT_STATUS_FIFO_FULL : Icm426xxDefs.h
- BIT_INT_STATUS_FIFO_THS : Icm426xxDefs.h
- BIT_INT_STATUS_OIS1_AGC_RDY : Icm426xxDefs.h
- BIT_INT_STATUS_OIS1_DRDY : Icm426xxDefs.h
- BIT_INT_STATUS_OIS1_FSYNC : Icm426xxDefs.h
- BIT_INT_STATUS_OIS2_AGC_RDY : Icm426xxDefs.h
- BIT_INT_STATUS_OIS2_DRDY : Icm426xxDefs.h
- BIT_INT_STATUS_OIS2_FSYNC : Icm426xxDefs.h
- BIT_INT_STATUS_PLL_RDY : Icm426xxDefs.h
- BIT_INT_STATUS_RESET_DONE : Icm426xxDefs.h
- BIT_INT_STATUS_UI_FSYNC : Icm426xxDefs.h
- BIT_INT_STEP_CNT_OVFL_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_STEP_CNT_OVFL_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_STEP_DET_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_STEP_DET_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_TAP_DET_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_TAP_DET_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_TDEASSERT_MASK : Icm426xxDefs.h
- BIT_INT_TDEASSERT_POS : Icm426xxDefs.h
- BIT_INT_TILT_DET_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_TILT_DET_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_TPULSE_DURATION_MASK : Icm426xxDefs.h
- BIT_INT_TPULSE_DURATION_POS : Icm426xxDefs.h
- BIT_INT_UI_AGC_RDY_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_UI_AGC_RDY_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_UI_DRDY_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_UI_DRDY_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_UI_FSYNC_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_UI_FSYNC_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_WAKE_DET_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_WAKE_DET_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_WOM_X_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_WOM_X_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_WOM_Y_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_WOM_Y_INT_EN_POS : Icm426xxDefs.h
- BIT_INT_WOM_Z_IBI_EN_POS : Icm426xxDefs.h
- BIT_INT_WOM_Z_INT_EN_POS : Icm426xxDefs.h
- BIT_INTF_CONFIG4_AP_SPI_MASK : Icm426xxDefs.h
- BIT_INTF_CONFIG4_AP_SPI_POS : Icm426xxDefs.h
- BIT_INTF_CONFIG4_AUX1_SPI_MASK : Icm426xxDefs.h
- BIT_INTF_CONFIG4_AUX1_SPI_POS : Icm426xxDefs.h
- BIT_INTF_CONFIG5_GPIO_PAD_SEL_MASK : Icm426xxDefs.h
- BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS : Icm426xxDefs.h
- BIT_INTF_CONFIG6_I3C_DDR_EN_MASK : Icm426xxDefs.h
- BIT_INTF_CONFIG6_I3C_DDR_EN_POS : Icm426xxDefs.h
- BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_MASK : Icm426xxDefs.h
- BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS : Icm426xxDefs.h
- BIT_INTF_CONFIG6_I3C_IBI_EN_MASK : Icm426xxDefs.h
- BIT_INTF_CONFIG6_I3C_IBI_EN_POS : Icm426xxDefs.h
- BIT_INTF_CONFIG6_I3C_SDR_EN_MASK : Icm426xxDefs.h
- BIT_INTF_CONFIG6_I3C_SDR_EN_POS : Icm426xxDefs.h
- BIT_MEM_OTP_ACCESS_EN : Icm426xxDefs.h
- BIT_OIS1_CONFIG1_ACCEL_EN_MASK : Icm426xxDefs.h
- BIT_OIS1_CONFIG1_ACCEL_EN_POS : Icm426xxDefs.h
- BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_MASK : Icm426xxDefs.h
- BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS : Icm426xxDefs.h
- BIT_OIS1_CONFIG1_DEC_MASK : Icm426xxDefs.h
- BIT_OIS1_CONFIG1_DEC_POS : Icm426xxDefs.h
- BIT_OIS1_CONFIG1_GYRO_EN_MASK : Icm426xxDefs.h
- BIT_OIS1_CONFIG1_GYRO_EN_POS : Icm426xxDefs.h
- BIT_OIS1_CONFIG2_ACCEL_FS_SEL_MASK : Icm426xxDefs.h
- BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS : Icm426xxDefs.h
- BIT_OIS1_CONFIG2_GYRO_FS_SEL_MASK : Icm426xxDefs.h
- BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS : Icm426xxDefs.h
- BIT_OIS2_CONFIG1_ACCEL_EN_MASK : Icm426xxDefs.h
- BIT_OIS2_CONFIG1_ACCEL_EN_POS : Icm426xxDefs.h
- BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_MASK : Icm426xxDefs.h
- BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS : Icm426xxDefs.h
- BIT_OIS2_CONFIG1_DEC_MASK : Icm426xxDefs.h
- BIT_OIS2_CONFIG1_DEC_POS : Icm426xxDefs.h
- BIT_OIS2_CONFIG1_GYRO_EN_MASK : Icm426xxDefs.h
- BIT_OIS2_CONFIG1_GYRO_EN_POS : Icm426xxDefs.h
- BIT_OIS2_CONFIG2_ACCEL_FS_SEL_MASK : Icm426xxDefs.h
- BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS : Icm426xxDefs.h
- BIT_OIS2_CONFIG2_GYRO_FS_SEL_MASK : Icm426xxDefs.h
- BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS : Icm426xxDefs.h
- BIT_PWR_MGMT_0_ACCEL_MODE_MASK : Icm426xxDefs.h
- BIT_PWR_MGMT_0_ACCEL_MODE_POS : Icm426xxDefs.h
- BIT_PWR_MGMT_0_GYRO_MODE_MASK : Icm426xxDefs.h
- BIT_PWR_MGMT_0_GYRO_MODE_POS : Icm426xxDefs.h
- BIT_PWR_MGMT_0_IDLE_MASK : Icm426xxDefs.h
- BIT_PWR_MGMT_0_IDLE_POS : Icm426xxDefs.h
- BIT_PWR_MGMT_0_TEMP_MASK : Icm426xxDefs.h
- BIT_PWR_MGMT_0_TEMP_POS : Icm426xxDefs.h
- BIT_RTC_MODE_MASK : Icm426xxDefs.h
- BIT_RTC_MODE_POS : Icm426xxDefs.h
- BIT_SENSOR_CONFIG2_OIS_MODE_MASK : Icm426xxDefs.h
- BIT_SENSOR_CONFIG2_OIS_MODE_POS : Icm426xxDefs.h
- BIT_SIGNAL_PATH_RESET_DMP_INIT_MASK : Icm426xxDefs.h
- BIT_SIGNAL_PATH_RESET_DMP_INIT_POS : Icm426xxDefs.h
- BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_MASK : Icm426xxDefs.h
- BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS : Icm426xxDefs.h
- BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_MASK : Icm426xxDefs.h
- BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS : Icm426xxDefs.h
- BIT_SIGNAL_PATH_RESET_TMST_STROBE_MASK : Icm426xxDefs.h
- BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS : Icm426xxDefs.h
- BIT_SMD_CONFIG_SMD_MODE_MASK : Icm426xxDefs.h
- BIT_SMD_CONFIG_SMD_MODE_POS : Icm426xxDefs.h
- BIT_SMD_CONFIG_WOM_INT_MODE_MASK : Icm426xxDefs.h
- BIT_SMD_CONFIG_WOM_INT_MODE_POS : Icm426xxDefs.h
- BIT_SMD_CONFIG_WOM_MODE_MASK : Icm426xxDefs.h
- BIT_SMD_CONFIG_WOM_MODE_POS : Icm426xxDefs.h
- BIT_SPI_MODE_OIS1_MASK : Icm426xxDefs.h
- BIT_SPI_MODE_OIS1_POS : Icm426xxDefs.h
- BIT_SPI_MODE_OIS2_MASK : Icm426xxDefs.h
- BIT_SPI_MODE_OIS2_POS : Icm426xxDefs.h
- BIT_ST_REGULATOR_EN : Icm426xxDefs.h
- BIT_TMST_CONFIG_RESOL_MASK : Icm426xxDefs.h
- BIT_TMST_CONFIG_RESOL_POS : Icm426xxDefs.h
- BIT_TMST_CONFIG_TMST_EN_MASK : Icm426xxDefs.h
- BIT_TMST_CONFIG_TMST_EN_POS : Icm426xxDefs.h
- BIT_TMST_CONFIG_TMST_FSYNC_MASK : Icm426xxDefs.h
- BIT_TMST_CONFIG_TMST_FSYNC_POS : Icm426xxDefs.h
- BIT_TMST_CONFIG_TMST_TO_REGS_EN_MASK : Icm426xxDefs.h
- BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS : Icm426xxDefs.h