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Classes | Macros
inv_imu_regmap_le.h File Reference

File exposing the device register map. More...

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## Classes
struct | pwr_mgmt0_t
struct | fifo_data_t
struct | int1_config0_t
struct | int1_config1_t
struct | int1_config2_t
struct | int1_status0_t
struct | int1_status1_t
struct | accel_config0_t
struct | gyro_config0_t
struct | fifo_config0_t
struct | fifo_config2_t
struct | fifo_config3_t
struct | fifo_config4_t
struct | tmst_wom_config_t
struct | fsync_config0_t
struct | fsync_config1_t
struct | rtc_config_t
struct | dmp_ext_sen_odr_cfg_t
struct | odr_decimate_config_t
struct | edmp_apex_en0_t
struct | edmp_apex_en1_t
struct | apex_buffer_mgmt_t
struct | intf_config0_t
struct | intf_config1_ovrd_t
struct | intf_aux_config_t
struct | ioc_pad_scenario_t
struct | ioc_pad_scenario_aux_ovrd_t
struct | ioc_pad_scenario_ovrd_t
struct | drive_config0_t
struct | drive_config1_t
struct | drive_config2_t
struct | reg_misc1_t
struct | int_apex_config0_t
struct | int_apex_config1_t
struct | int_apex_status0_t
struct | int_apex_status1_t
struct | intf_config_ovrd_aux1_t
struct | pwr_mgmt_aux1_t
struct | fs_sel_aux1_t
struct | int2_config0_t
struct | int2_config1_t
struct | int2_config2_t
struct | int2_status0_t
struct | int2_status1_t
struct | intf_config_ovrd_aux2_t
struct | pwr_mgmt_aux2_t
struct | fs_sel_aux2_t
struct | int_aux2_config_t
struct | int_aux2_status_t
struct | who_am_i_t
struct | reg_host_msg_t
struct | ireg_addr_15_8_t
struct | ireg_addr_7_0_t
struct | ireg_data_t
struct | reg_misc2_t
struct | i2cm_command_0_t
struct | i2cm_command_1_t
struct | i2cm_command_2_t
struct | i2cm_command_3_t
struct | i2cm_dev_profile0_t
struct | i2cm_dev_profile1_t
struct | i2cm_dev_profile2_t
struct | i2cm_dev_profile3_t
struct | i2cm_control_t
struct | i2cm_status_t
struct | i2cm_ext_dev_status_t
struct | i2cm_rd_data0_t
struct | i2cm_rd_data1_t
struct | i2cm_rd_data2_t
struct | i2cm_rd_data3_t
struct | i2cm_rd_data4_t
struct | i2cm_rd_data5_t
struct | i2cm_rd_data6_t
struct | i2cm_rd_data7_t
struct | i2cm_rd_data8_t
struct | i2cm_rd_data9_t
struct | i2cm_rd_data10_t
struct | i2cm_rd_data11_t
struct | i2cm_rd_data12_t
struct | i2cm_rd_data13_t
struct | i2cm_rd_data14_t
struct | i2cm_rd_data15_t
struct | i2cm_rd_data16_t
struct | i2cm_rd_data17_t
struct | i2cm_rd_data18_t
struct | i2cm_rd_data19_t
struct | i2cm_rd_data20_t
struct | i2cm_wr_data0_t
struct | i2cm_wr_data1_t
struct | i2cm_wr_data2_t
struct | i2cm_wr_data3_t
struct | i2cm_wr_data4_t
struct | i2cm_wr_data5_t
struct | sifs_ixc_error_status_t
struct | edmp_sp_start_addr_t
struct | smc_control_0_t
struct | smc_control_1_t
struct | stc_config_t
struct | sreg_ctrl_t
struct | sifs_i3c_stc_cfg_t
struct | int_pulse_min_on_intf0_t
struct | int_pulse_min_on_intf1_t
struct | int_pulse_min_off_intf0_t
struct | int_pulse_min_off_intf1_t
struct | isr_0_7_t
struct | isr_8_15_t
struct | isr_16_23_t
struct | status_mask_pin_0_7_t
struct | status_mask_pin_8_15_t
struct | status_mask_pin_16_23_t
struct | int_i2cm_source_t
struct | accel_wom_x_thr_t
struct | accel_wom_y_thr_t
struct | accel_wom_z_thr_t
struct | selftest_t
struct | ipreg_misc_t
struct | sw_pll1_trim_t
struct | fifo_sram_sleep_t
struct | ipreg_sys1_reg_166_t
struct | ipreg_sys1_reg_168_t
struct | ipreg_sys1_reg_170_t
struct | ipreg_sys1_reg_171_t
struct | ipreg_sys1_reg_172_t
struct | ipreg_sys1_reg_173_t
struct | ipreg_sys2_reg_123_t
struct | ipreg_sys2_reg_129_t
struct | ipreg_sys2_reg_130_t
struct | ipreg_sys2_reg_131_t
struct | ipreg_sys2_reg_132_t
struct | ipreg_bar_reg_57_t
struct | ipreg_bar_reg_58_t
struct | ipreg_bar_reg_59_t
struct | ipreg_bar_reg_60_t
struct | ipreg_bar_reg_61_t
struct | ipreg_bar_reg_62_t

## Macros
#define | ACCEL_DATA_X1_UI 0x00
#define | ACCEL_DATA_X0_UI 0x01
#define | ACCEL_DATA_Y1_UI 0x02
#define | ACCEL_DATA_Y0_UI 0x03
#define | ACCEL_DATA_Z1_UI 0x04
#define | ACCEL_DATA_Z0_UI 0x05
#define | GYRO_DATA_X1_UI 0x06
#define | GYRO_DATA_X0_UI 0x07
#define | GYRO_DATA_Y1_UI 0x08
#define | GYRO_DATA_Y0_UI 0x09
#define | GYRO_DATA_Z1_UI 0x0a
#define | GYRO_DATA_Z0_UI 0x0b
#define | TEMP_DATA1_UI 0x0c
#define | TEMP_DATA0_UI 0x0d
#define | TMST_FSYNCH 0x0e
#define | TMST_FSYNCL 0x0f
#define | PWR_MGMT0 0x10
#define | FIFO_COUNT_0 0x12
#define | FIFO_COUNT_1 0x13
#define | FIFO_DATA 0x14
#define | INT1_CONFIG0 0x16
#define | INT1_CONFIG1 0x17
#define | INT1_CONFIG2 0x18
#define | INT1_STATUS0 0x19
#define | INT1_STATUS1 0x1a
#define | ACCEL_CONFIG0 0x1b
#define | GYRO_CONFIG0 0x1c
#define | FIFO_CONFIG0 0x1d
#define | FIFO_CONFIG1_0 0x1e
#define | FIFO_CONFIG1_1 0x1f
#define | FIFO_CONFIG2 0x20
#define | FIFO_CONFIG3 0x21
#define | FIFO_CONFIG4 0x22
#define | TMST_WOM_CONFIG 0x23
#define | FSYNC_CONFIG0 0x24
#define | FSYNC_CONFIG1 0x25
#define | RTC_CONFIG 0x26
#define | DMP_EXT_SEN_ODR_CFG 0x27
#define | ODR_DECIMATE_CONFIG 0x28
#define | EDMP_APEX_EN0 0x29
#define | EDMP_APEX_EN1 0x2a
#define | APEX_BUFFER_MGMT 0x2b
#define | INTF_CONFIG0 0x2c
#define | INTF_CONFIG1_OVRD 0x2d
#define | INTF_AUX_CONFIG 0x2e
#define | IOC_PAD_SCENARIO 0x2f
#define | IOC_PAD_SCENARIO_AUX_OVRD 0x30
#define | IOC_PAD_SCENARIO_OVRD 0x31
#define | DRIVE_CONFIG0 0x32
#define | DRIVE_CONFIG1 0x33
#define | DRIVE_CONFIG2 0x34
#define | REG_MISC1 0x35
#define | INT_APEX_CONFIG0 0x39
#define | INT_APEX_CONFIG1 0x3a
#define | INT_APEX_STATUS0 0x3b
#define | INT_APEX_STATUS1 0x3c
#define | INTF_CONFIG_OVRD_AUX1 0x42
#define | ACCEL_DATA_X1_AUX1 0x44
#define | ACCEL_DATA_X0_AUX1 0x45
#define | ACCEL_DATA_Y1_AUX1 0x46
#define | ACCEL_DATA_Y0_AUX1 0x47
#define | ACCEL_DATA_Z1_AUX1 0x48
#define | ACCEL_DATA_Z0_AUX1 0x49
#define | GYRO_DATA_X1_AUX1 0x4a
#define | GYRO_DATA_X0_AUX1 0x4b
#define | GYRO_DATA_Y1_AUX1 0x4c
#define | GYRO_DATA_Y0_AUX1 0x4d
#define | GYRO_DATA_Z1_AUX1 0x4e
#define | GYRO_DATA_Z0_AUX1 0x4f
#define | TEMP_DATA1_AUX1 0x50
#define | TEMP_DATA0_AUX1 0x51
#define | TMST_FSYNCH_AUX1 0x52
#define | TMST_FSYNCL_AUX1 0x53
#define | PWR_MGMT_AUX1 0x54
#define | FS_SEL_AUX1 0x55
#define | INT2_CONFIG0 0x56
#define | INT2_CONFIG1 0x57
#define | INT2_CONFIG2 0x58
#define | INT2_STATUS0 0x59
#define | INT2_STATUS1 0x5a
#define | INTF_CONFIG_OVRD_AUX2 0x5c
#define | ACCEL_DATA_X1_AUX2 0x5e
#define | ACCEL_DATA_X0_AUX2 0x5f
#define | ACCEL_DATA_Y1_AUX2 0x60
#define | ACCEL_DATA_Y0_AUX2 0x61
#define | ACCEL_DATA_Z1_AUX2 0x62
#define | ACCEL_DATA_Z0_AUX2 0x63
#define | GYRO_DATA_X1_AUX2 0x64
#define | GYRO_DATA_X0_AUX2 0x65
#define | GYRO_DATA_Y1_AUX2 0x66
#define | GYRO_DATA_Y0_AUX2 0x67
#define | GYRO_DATA_Z1_AUX2 0x68
#define | GYRO_DATA_Z0_AUX2 0x69
#define | TEMP_DATA1_AUX2 0x6a
#define | TEMP_DATA0_AUX2 0x6b
#define | TMST_FSYNCH_AUX2 0x6c
#define | TMST_FSYNCL_AUX2 0x6d
#define | PWR_MGMT_AUX2 0x6e
#define | FS_SEL_AUX2 0x6f
#define | INT_AUX2_CONFIG 0x70
#define | INT_AUX2_STATUS 0x71
#define | WHO_AM_I 0x72
#define | REG_HOST_MSG 0x73
#define | IREG_ADDR_15_8 0x7c
#define | IREG_ADDR_7_0 0x7d
#define | IREG_DATA 0x7e
#define | REG_MISC2 0x7f
#define | I2CM_COMMAND_0 0xa206
#define | I2CM_COMMAND_1 0xa207
#define | I2CM_COMMAND_2 0xa208
#define | I2CM_COMMAND_3 0xa209
#define | I2CM_DEV_PROFILE0 0xa20e
#define | I2CM_DEV_PROFILE1 0xa20f
#define | I2CM_DEV_PROFILE2 0xa210
#define | I2CM_DEV_PROFILE3 0xa211
#define | I2CM_CONTROL 0xa216
#define | I2CM_STATUS 0xa218
#define | I2CM_EXT_DEV_STATUS 0xa21a
#define | I2CM_RD_DATA0 0xa21b
#define | I2CM_RD_DATA1 0xa21c
#define | I2CM_RD_DATA2 0xa21d
#define | I2CM_RD_DATA3 0xa21e
#define | I2CM_RD_DATA4 0xa21f
#define | I2CM_RD_DATA5 0xa220
#define | I2CM_RD_DATA6 0xa221
#define | I2CM_RD_DATA7 0xa222
#define | I2CM_RD_DATA8 0xa223
#define | I2CM_RD_DATA9 0xa224
#define | I2CM_RD_DATA10 0xa225
#define | I2CM_RD_DATA11 0xa226
#define | I2CM_RD_DATA12 0xa227
#define | I2CM_RD_DATA13 0xa228
#define | I2CM_RD_DATA14 0xa229
#define | I2CM_RD_DATA15 0xa22a
#define | I2CM_RD_DATA16 0xa22b
#define | I2CM_RD_DATA17 0xa22c
#define | I2CM_RD_DATA18 0xa22d
#define | I2CM_RD_DATA19 0xa22e
#define | I2CM_RD_DATA20 0xa22f
#define | I2CM_WR_DATA0 0xa233
#define | I2CM_WR_DATA1 0xa234
#define | I2CM_WR_DATA2 0xa235
#define | I2CM_WR_DATA3 0xa236
#define | I2CM_WR_DATA4 0xa237
#define | I2CM_WR_DATA5 0xa238
#define | SIFS_IXC_ERROR_STATUS 0xa24b
#define | EDMP_PRGRM_IRQ0_0 0xa24f
#define | EDMP_PRGRM_IRQ0_1 0xa250
#define | EDMP_PRGRM_IRQ1_0 0xa251
#define | EDMP_PRGRM_IRQ1_1 0xa252
#define | EDMP_PRGRM_IRQ2_0 0xa253
#define | EDMP_PRGRM_IRQ2_1 0xa254
#define | EDMP_SP_START_ADDR 0xa255
#define | SMC_CONTROL_0 0xa258
#define | SMC_CONTROL_1 0xa259
#define | STC_CONFIG 0xa263
#define | SREG_CTRL 0xa267
#define | SIFS_I3C_STC_CFG 0xa268
#define | INT_PULSE_MIN_ON_INTF0 0xa269
#define | INT_PULSE_MIN_ON_INTF1 0xa26a
#define | INT_PULSE_MIN_OFF_INTF0 0xa26b
#define | INT_PULSE_MIN_OFF_INTF1 0xa26c
#define | ISR_0_7 0xa26e
#define | ISR_8_15 0xa26f
#define | ISR_16_23 0xa270
#define | STATUS_MASK_PIN_0_7 0xa271
#define | STATUS_MASK_PIN_8_15 0xa272
#define | STATUS_MASK_PIN_16_23 0xa273
#define | INT_I2CM_SOURCE 0xa274
#define | ACCEL_WOM_X_THR 0xa27e
#define | ACCEL_WOM_Y_THR 0xa27f
#define | ACCEL_WOM_Z_THR 0xa280
#define | SELFTEST 0xa290
#define | IPREG_MISC 0xa297
#define | SW_PLL1_TRIM 0xa2a2
#define | FIFO_SRAM_SLEEP 0xa2a7
#define | IPREG_SYS1_REG_42 0xa42a
#define | IPREG_SYS1_REG_43 0xa42b
#define | IPREG_SYS1_REG_56 0xa438
#define | IPREG_SYS1_REG_57 0xa439
#define | IPREG_SYS1_REG_70 0xa446
#define | IPREG_SYS1_REG_71 0xa447
#define | IPREG_SYS1_REG_166 0xa4a6
#define | IPREG_SYS1_REG_168 0xa4a8
#define | IPREG_SYS1_REG_170 0xa4aa
#define | IPREG_SYS1_REG_171 0xa4ab
#define | IPREG_SYS1_REG_172 0xa4ac
#define | IPREG_SYS1_REG_173 0xa4ad
#define | IPREG_SYS2_REG_24 0xa518
#define | IPREG_SYS2_REG_25 0xa519
#define | IPREG_SYS2_REG_32 0xa520
#define | IPREG_SYS2_REG_33 0xa521
#define | IPREG_SYS2_REG_40 0xa528
#define | IPREG_SYS2_REG_41 0xa529
#define | IPREG_SYS2_REG_123 0xa57b
#define | IPREG_SYS2_REG_129 0xa581
#define | IPREG_SYS2_REG_130 0xa582
#define | IPREG_SYS2_REG_131 0xa583
#define | IPREG_SYS2_REG_132 0xa584
#define | IPREG_BAR_REG_57 0xa039
#define | IPREG_BAR_REG_58 0xa03a
#define | IPREG_BAR_REG_59 0xa03b
#define | IPREG_BAR_REG_60 0xa03c
#define | IPREG_BAR_REG_61 0xa03d
#define | IPREG_BAR_REG_62 0xa03e

## Detailed Description

File exposing the device register map.

## Macro Definition Documentation

## ◆ ACCEL_CONFIG0

#define ACCEL_CONFIG0 0x1b

## ◆ ACCEL_DATA_X0_AUX1

#define ACCEL_DATA_X0_AUX1 0x45

## ◆ ACCEL_DATA_X0_AUX2

#define ACCEL_DATA_X0_AUX2 0x5f

## ◆ ACCEL_DATA_X0_UI

#define ACCEL_DATA_X0_UI 0x01

## ◆ ACCEL_DATA_X1_AUX1

#define ACCEL_DATA_X1_AUX1 0x44

## ◆ ACCEL_DATA_X1_AUX2

#define ACCEL_DATA_X1_AUX2 0x5e

## ◆ ACCEL_DATA_X1_UI

#define ACCEL_DATA_X1_UI 0x00

## ◆ ACCEL_DATA_Y0_AUX1

#define ACCEL_DATA_Y0_AUX1 0x47

## ◆ ACCEL_DATA_Y0_AUX2

#define ACCEL_DATA_Y0_AUX2 0x61

## ◆ ACCEL_DATA_Y0_UI

#define ACCEL_DATA_Y0_UI 0x03

## ◆ ACCEL_DATA_Y1_AUX1

#define ACCEL_DATA_Y1_AUX1 0x46

## ◆ ACCEL_DATA_Y1_AUX2

#define ACCEL_DATA_Y1_AUX2 0x60

## ◆ ACCEL_DATA_Y1_UI

#define ACCEL_DATA_Y1_UI 0x02

## ◆ ACCEL_DATA_Z0_AUX1

#define ACCEL_DATA_Z0_AUX1 0x49

## ◆ ACCEL_DATA_Z0_AUX2

#define ACCEL_DATA_Z0_AUX2 0x63

## ◆ ACCEL_DATA_Z0_UI

#define ACCEL_DATA_Z0_UI 0x05

## ◆ ACCEL_DATA_Z1_AUX1

#define ACCEL_DATA_Z1_AUX1 0x48

## ◆ ACCEL_DATA_Z1_AUX2

#define ACCEL_DATA_Z1_AUX2 0x62

## ◆ ACCEL_DATA_Z1_UI

#define ACCEL_DATA_Z1_UI 0x04

## ◆ ACCEL_WOM_X_THR

#define ACCEL_WOM_X_THR 0xa27e

## ◆ ACCEL_WOM_Y_THR

#define ACCEL_WOM_Y_THR 0xa27f

## ◆ ACCEL_WOM_Z_THR

#define ACCEL_WOM_Z_THR 0xa280

## ◆ APEX_BUFFER_MGMT

#define APEX_BUFFER_MGMT 0x2b

## ◆ DMP_EXT_SEN_ODR_CFG

#define DMP_EXT_SEN_ODR_CFG 0x27

## ◆ DRIVE_CONFIG0

#define DRIVE_CONFIG0 0x32

## ◆ DRIVE_CONFIG1

#define DRIVE_CONFIG1 0x33

## ◆ DRIVE_CONFIG2

#define DRIVE_CONFIG2 0x34

## ◆ EDMP_APEX_EN0

#define EDMP_APEX_EN0 0x29

## ◆ EDMP_APEX_EN1

#define EDMP_APEX_EN1 0x2a

## ◆ EDMP_PRGRM_IRQ0_0

#define EDMP_PRGRM_IRQ0_0 0xa24f

## ◆ EDMP_PRGRM_IRQ0_1

#define EDMP_PRGRM_IRQ0_1 0xa250

## ◆ EDMP_PRGRM_IRQ1_0

#define EDMP_PRGRM_IRQ1_0 0xa251

## ◆ EDMP_PRGRM_IRQ1_1

#define EDMP_PRGRM_IRQ1_1 0xa252

## ◆ EDMP_PRGRM_IRQ2_0

#define EDMP_PRGRM_IRQ2_0 0xa253

## ◆ EDMP_PRGRM_IRQ2_1

#define EDMP_PRGRM_IRQ2_1 0xa254

## ◆ EDMP_SP_START_ADDR

#define EDMP_SP_START_ADDR 0xa255

## ◆ FIFO_CONFIG0

#define FIFO_CONFIG0 0x1d

## ◆ FIFO_CONFIG1_0

#define FIFO_CONFIG1_0 0x1e

## ◆ FIFO_CONFIG1_1

#define FIFO_CONFIG1_1 0x1f

## ◆ FIFO_CONFIG2

#define FIFO_CONFIG2 0x20

## ◆ FIFO_CONFIG3

#define FIFO_CONFIG3 0x21

## ◆ FIFO_CONFIG4

#define FIFO_CONFIG4 0x22

## ◆ FIFO_COUNT_0

#define FIFO_COUNT_0 0x12

## ◆ FIFO_COUNT_1

#define FIFO_COUNT_1 0x13

## ◆ FIFO_DATA

#define FIFO_DATA 0x14

## ◆ FIFO_SRAM_SLEEP

#define FIFO_SRAM_SLEEP 0xa2a7

## ◆ FS_SEL_AUX1

#define FS_SEL_AUX1 0x55

## ◆ FS_SEL_AUX2

#define FS_SEL_AUX2 0x6f

## ◆ FSYNC_CONFIG0

#define FSYNC_CONFIG0 0x24

## ◆ FSYNC_CONFIG1

#define FSYNC_CONFIG1 0x25

## ◆ GYRO_CONFIG0

#define GYRO_CONFIG0 0x1c

## ◆ GYRO_DATA_X0_AUX1

#define GYRO_DATA_X0_AUX1 0x4b

## ◆ GYRO_DATA_X0_AUX2

#define GYRO_DATA_X0_AUX2 0x65

## ◆ GYRO_DATA_X0_UI

#define GYRO_DATA_X0_UI 0x07

## ◆ GYRO_DATA_X1_AUX1

#define GYRO_DATA_X1_AUX1 0x4a

## ◆ GYRO_DATA_X1_AUX2

#define GYRO_DATA_X1_AUX2 0x64

## ◆ GYRO_DATA_X1_UI

#define GYRO_DATA_X1_UI 0x06

## ◆ GYRO_DATA_Y0_AUX1

#define GYRO_DATA_Y0_AUX1 0x4d

## ◆ GYRO_DATA_Y0_AUX2

#define GYRO_DATA_Y0_AUX2 0x67

## ◆ GYRO_DATA_Y0_UI

#define GYRO_DATA_Y0_UI 0x09

## ◆ GYRO_DATA_Y1_AUX1

#define GYRO_DATA_Y1_AUX1 0x4c

## ◆ GYRO_DATA_Y1_AUX2

#define GYRO_DATA_Y1_AUX2 0x66

## ◆ GYRO_DATA_Y1_UI

#define GYRO_DATA_Y1_UI 0x08

## ◆ GYRO_DATA_Z0_AUX1

#define GYRO_DATA_Z0_AUX1 0x4f

## ◆ GYRO_DATA_Z0_AUX2

#define GYRO_DATA_Z0_AUX2 0x69

## ◆ GYRO_DATA_Z0_UI

#define GYRO_DATA_Z0_UI 0x0b

## ◆ GYRO_DATA_Z1_AUX1

#define GYRO_DATA_Z1_AUX1 0x4e

## ◆ GYRO_DATA_Z1_AUX2

#define GYRO_DATA_Z1_AUX2 0x68

## ◆ GYRO_DATA_Z1_UI

#define GYRO_DATA_Z1_UI 0x0a

## ◆ I2CM_COMMAND_0

#define I2CM_COMMAND_0 0xa206

## ◆ I2CM_COMMAND_1

#define I2CM_COMMAND_1 0xa207

## ◆ I2CM_COMMAND_2

#define I2CM_COMMAND_2 0xa208

## ◆ I2CM_COMMAND_3

#define I2CM_COMMAND_3 0xa209

## ◆ I2CM_CONTROL

#define I2CM_CONTROL 0xa216

## ◆ I2CM_DEV_PROFILE0

#define I2CM_DEV_PROFILE0 0xa20e

## ◆ I2CM_DEV_PROFILE1

#define I2CM_DEV_PROFILE1 0xa20f

## ◆ I2CM_DEV_PROFILE2

#define I2CM_DEV_PROFILE2 0xa210

## ◆ I2CM_DEV_PROFILE3

#define I2CM_DEV_PROFILE3 0xa211

## ◆ I2CM_EXT_DEV_STATUS

#define I2CM_EXT_DEV_STATUS 0xa21a

## ◆ I2CM_RD_DATA0

#define I2CM_RD_DATA0 0xa21b

## ◆ I2CM_RD_DATA1

#define I2CM_RD_DATA1 0xa21c

## ◆ I2CM_RD_DATA10

#define I2CM_RD_DATA10 0xa225

## ◆ I2CM_RD_DATA11

#define I2CM_RD_DATA11 0xa226

## ◆ I2CM_RD_DATA12

#define I2CM_RD_DATA12 0xa227

## ◆ I2CM_RD_DATA13

#define I2CM_RD_DATA13 0xa228

## ◆ I2CM_RD_DATA14

#define I2CM_RD_DATA14 0xa229

## ◆ I2CM_RD_DATA15

#define I2CM_RD_DATA15 0xa22a

## ◆ I2CM_RD_DATA16

#define I2CM_RD_DATA16 0xa22b

## ◆ I2CM_RD_DATA17

#define I2CM_RD_DATA17 0xa22c

## ◆ I2CM_RD_DATA18

#define I2CM_RD_DATA18 0xa22d

## ◆ I2CM_RD_DATA19

#define I2CM_RD_DATA19 0xa22e

## ◆ I2CM_RD_DATA2

#define I2CM_RD_DATA2 0xa21d

## ◆ I2CM_RD_DATA20

#define I2CM_RD_DATA20 0xa22f

## ◆ I2CM_RD_DATA3

#define I2CM_RD_DATA3 0xa21e

## ◆ I2CM_RD_DATA4

#define I2CM_RD_DATA4 0xa21f

## ◆ I2CM_RD_DATA5

#define I2CM_RD_DATA5 0xa220

## ◆ I2CM_RD_DATA6

#define I2CM_RD_DATA6 0xa221

## ◆ I2CM_RD_DATA7

#define I2CM_RD_DATA7 0xa222

## ◆ I2CM_RD_DATA8

#define I2CM_RD_DATA8 0xa223

## ◆ I2CM_RD_DATA9

#define I2CM_RD_DATA9 0xa224

## ◆ I2CM_STATUS

#define I2CM_STATUS 0xa218

## ◆ I2CM_WR_DATA0

#define I2CM_WR_DATA0 0xa233

## ◆ I2CM_WR_DATA1

#define I2CM_WR_DATA1 0xa234

## ◆ I2CM_WR_DATA2

#define I2CM_WR_DATA2 0xa235

## ◆ I2CM_WR_DATA3

#define I2CM_WR_DATA3 0xa236

## ◆ I2CM_WR_DATA4

#define I2CM_WR_DATA4 0xa237

## ◆ I2CM_WR_DATA5

#define I2CM_WR_DATA5 0xa238

## ◆ INT1_CONFIG0

#define INT1_CONFIG0 0x16

## ◆ INT1_CONFIG1

#define INT1_CONFIG1 0x17

## ◆ INT1_CONFIG2

#define INT1_CONFIG2 0x18

## ◆ INT1_STATUS0

#define INT1_STATUS0 0x19

## ◆ INT1_STATUS1

#define INT1_STATUS1 0x1a

## ◆ INT2_CONFIG0

#define INT2_CONFIG0 0x56

## ◆ INT2_CONFIG1

#define INT2_CONFIG1 0x57

## ◆ INT2_CONFIG2

#define INT2_CONFIG2 0x58

## ◆ INT2_STATUS0

#define INT2_STATUS0 0x59

## ◆ INT2_STATUS1

#define INT2_STATUS1 0x5a

## ◆ INT_APEX_CONFIG0

#define INT_APEX_CONFIG0 0x39

## ◆ INT_APEX_CONFIG1

#define INT_APEX_CONFIG1 0x3a

## ◆ INT_APEX_STATUS0

#define INT_APEX_STATUS0 0x3b

## ◆ INT_APEX_STATUS1

#define INT_APEX_STATUS1 0x3c

## ◆ INT_AUX2_CONFIG

#define INT_AUX2_CONFIG 0x70

## ◆ INT_AUX2_STATUS

#define INT_AUX2_STATUS 0x71

## ◆ INT_I2CM_SOURCE

#define INT_I2CM_SOURCE 0xa274

## ◆ INT_PULSE_MIN_OFF_INTF0

#define INT_PULSE_MIN_OFF_INTF0 0xa26b

## ◆ INT_PULSE_MIN_OFF_INTF1

#define INT_PULSE_MIN_OFF_INTF1 0xa26c

## ◆ INT_PULSE_MIN_ON_INTF0

#define INT_PULSE_MIN_ON_INTF0 0xa269

## ◆ INT_PULSE_MIN_ON_INTF1

#define INT_PULSE_MIN_ON_INTF1 0xa26a

## ◆ INTF_AUX_CONFIG

#define INTF_AUX_CONFIG 0x2e

## ◆ INTF_CONFIG0

#define INTF_CONFIG0 0x2c

## ◆ INTF_CONFIG1_OVRD

#define INTF_CONFIG1_OVRD 0x2d

## ◆ INTF_CONFIG_OVRD_AUX1

#define INTF_CONFIG_OVRD_AUX1 0x42

## ◆ INTF_CONFIG_OVRD_AUX2

#define INTF_CONFIG_OVRD_AUX2 0x5c

## ◆ IOC_PAD_SCENARIO

#define IOC_PAD_SCENARIO 0x2f

## ◆ IOC_PAD_SCENARIO_AUX_OVRD

#define IOC_PAD_SCENARIO_AUX_OVRD 0x30

## ◆ IOC_PAD_SCENARIO_OVRD

#define IOC_PAD_SCENARIO_OVRD 0x31

## ◆ IPREG_BAR_REG_57

#define IPREG_BAR_REG_57 0xa039

## ◆ IPREG_BAR_REG_58

#define IPREG_BAR_REG_58 0xa03a

## ◆ IPREG_BAR_REG_59

#define IPREG_BAR_REG_59 0xa03b

## ◆ IPREG_BAR_REG_60

#define IPREG_BAR_REG_60 0xa03c

## ◆ IPREG_BAR_REG_61

#define IPREG_BAR_REG_61 0xa03d

## ◆ IPREG_BAR_REG_62

#define IPREG_BAR_REG_62 0xa03e

## ◆ IPREG_MISC

#define IPREG_MISC 0xa297

## ◆ IPREG_SYS1_REG_166

#define IPREG_SYS1_REG_166 0xa4a6

## ◆ IPREG_SYS1_REG_168

#define IPREG_SYS1_REG_168 0xa4a8

## ◆ IPREG_SYS1_REG_170

#define IPREG_SYS1_REG_170 0xa4aa

## ◆ IPREG_SYS1_REG_171

#define IPREG_SYS1_REG_171 0xa4ab

## ◆ IPREG_SYS1_REG_172

#define IPREG_SYS1_REG_172 0xa4ac

## ◆ IPREG_SYS1_REG_173

#define IPREG_SYS1_REG_173 0xa4ad

## ◆ IPREG_SYS1_REG_42

#define IPREG_SYS1_REG_42 0xa42a

## ◆ IPREG_SYS1_REG_43

#define IPREG_SYS1_REG_43 0xa42b

## ◆ IPREG_SYS1_REG_56

#define IPREG_SYS1_REG_56 0xa438

## ◆ IPREG_SYS1_REG_57

#define IPREG_SYS1_REG_57 0xa439

## ◆ IPREG_SYS1_REG_70

#define IPREG_SYS1_REG_70 0xa446

## ◆ IPREG_SYS1_REG_71

#define IPREG_SYS1_REG_71 0xa447

## ◆ IPREG_SYS2_REG_123

#define IPREG_SYS2_REG_123 0xa57b

## ◆ IPREG_SYS2_REG_129

#define IPREG_SYS2_REG_129 0xa581

## ◆ IPREG_SYS2_REG_130

#define IPREG_SYS2_REG_130 0xa582

## ◆ IPREG_SYS2_REG_131

#define IPREG_SYS2_REG_131 0xa583

## ◆ IPREG_SYS2_REG_132

#define IPREG_SYS2_REG_132 0xa584

## ◆ IPREG_SYS2_REG_24

#define IPREG_SYS2_REG_24 0xa518

## ◆ IPREG_SYS2_REG_25

#define IPREG_SYS2_REG_25 0xa519

## ◆ IPREG_SYS2_REG_32

#define IPREG_SYS2_REG_32 0xa520

## ◆ IPREG_SYS2_REG_33

#define IPREG_SYS2_REG_33 0xa521

## ◆ IPREG_SYS2_REG_40

#define IPREG_SYS2_REG_40 0xa528

## ◆ IPREG_SYS2_REG_41

#define IPREG_SYS2_REG_41 0xa529

## ◆ IREG_ADDR_15_8

#define IREG_ADDR_15_8 0x7c

## ◆ IREG_ADDR_7_0

#define IREG_ADDR_7_0 0x7d

## ◆ IREG_DATA

#define IREG_DATA 0x7e

## ◆ ISR_0_7

#define ISR_0_7 0xa26e

## ◆ ISR_16_23

#define ISR_16_23 0xa270

## ◆ ISR_8_15

#define ISR_8_15 0xa26f

## ◆ ODR_DECIMATE_CONFIG

#define ODR_DECIMATE_CONFIG 0x28

## ◆ PWR_MGMT0

#define PWR_MGMT0 0x10

## ◆ PWR_MGMT_AUX1

#define PWR_MGMT_AUX1 0x54

## ◆ PWR_MGMT_AUX2

#define PWR_MGMT_AUX2 0x6e

## ◆ REG_HOST_MSG

#define REG_HOST_MSG 0x73

## ◆ REG_MISC1

#define REG_MISC1 0x35

## ◆ REG_MISC2

#define REG_MISC2 0x7f

## ◆ RTC_CONFIG

#define RTC_CONFIG 0x26

## ◆ SELFTEST

#define SELFTEST 0xa290

## ◆ SIFS_I3C_STC_CFG

#define SIFS_I3C_STC_CFG 0xa268

## ◆ SIFS_IXC_ERROR_STATUS

#define SIFS_IXC_ERROR_STATUS 0xa24b

## ◆ SMC_CONTROL_0

#define SMC_CONTROL_0 0xa258

## ◆ SMC_CONTROL_1

#define SMC_CONTROL_1 0xa259

## ◆ SREG_CTRL

#define SREG_CTRL 0xa267

## ◆ STATUS_MASK_PIN_0_7

#define STATUS_MASK_PIN_0_7 0xa271

## ◆ STATUS_MASK_PIN_16_23

#define STATUS_MASK_PIN_16_23 0xa273

## ◆ STATUS_MASK_PIN_8_15

#define STATUS_MASK_PIN_8_15 0xa272

## ◆ STC_CONFIG

#define STC_CONFIG 0xa263

## ◆ SW_PLL1_TRIM

#define SW_PLL1_TRIM 0xa2a2

## ◆ TEMP_DATA0_AUX1

#define TEMP_DATA0_AUX1 0x51

## ◆ TEMP_DATA0_AUX2

#define TEMP_DATA0_AUX2 0x6b

## ◆ TEMP_DATA0_UI

#define TEMP_DATA0_UI 0x0d

## ◆ TEMP_DATA1_AUX1

#define TEMP_DATA1_AUX1 0x50

## ◆ TEMP_DATA1_AUX2

#define TEMP_DATA1_AUX2 0x6a

## ◆ TEMP_DATA1_UI

#define TEMP_DATA1_UI 0x0c

## ◆ TMST_FSYNCH

#define TMST_FSYNCH 0x0e

## ◆ TMST_FSYNCH_AUX1

#define TMST_FSYNCH_AUX1 0x52

## ◆ TMST_FSYNCH_AUX2

#define TMST_FSYNCH_AUX2 0x6c

## ◆ TMST_FSYNCL

#define TMST_FSYNCL 0x0f

## ◆ TMST_FSYNCL_AUX1

#define TMST_FSYNCL_AUX1 0x53

## ◆ TMST_FSYNCL_AUX2

#define TMST_FSYNCL_AUX2 0x6d

## ◆ TMST_WOM_CONFIG

#define TMST_WOM_CONFIG 0x23

## ◆ WHO_AM_I

#define WHO_AM_I 0x72