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inv_imu_regmap_le.h
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1 /*
2 *
3 * Copyright (c) [2020] by InvenSense, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 */
17
18 #ifndef _INV_IMU_REGMAP_LE_H_
19 #define _INV_IMU_REGMAP_LE_H_
20
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24
30 /* DREG_BANK1 */
31 #define ACCEL_DATA_X1_UI 0x00
32 #define ACCEL_DATA_X0_UI 0x01
33 #define ACCEL_DATA_Y1_UI 0x02
34 #define ACCEL_DATA_Y0_UI 0x03
35 #define ACCEL_DATA_Z1_UI 0x04
36 #define ACCEL_DATA_Z0_UI 0x05
37 #define GYRO_DATA_X1_UI 0x06
38 #define GYRO_DATA_X0_UI 0x07
39 #define GYRO_DATA_Y1_UI 0x08
40 #define GYRO_DATA_Y0_UI 0x09
41 #define GYRO_DATA_Z1_UI 0x0a
42 #define GYRO_DATA_Z0_UI 0x0b
43 #define TEMP_DATA1_UI 0x0c
44 #define TEMP_DATA0_UI 0x0d
45 #define TMST_FSYNCH 0x0e
46 #define TMST_FSYNCL 0x0f
47 #define PWR_MGMT0 0x10
48 typedef struct {
49 uint8_t accel_mode : 2;
50 uint8_t gyro_mode : 2;
51 uint8_t resv_1 : 4;
52 } pwr_mgmt0_t;
53
54 #define FIFO_COUNT_0 0x12
55 #define FIFO_COUNT_1 0x13
56 #define FIFO_DATA 0x14
57 typedef struct {
58 uint8_t fifo_data : 8;
59 } fifo_data_t;
60
61 #define INT1_CONFIG0 0x16
62 typedef struct {
63 uint8_t int1_status_en_fifo_full : 1;
64 uint8_t int1_status_en_fifo_ths : 1;
65 uint8_t int1_status_en_drdy : 1;
66 uint8_t int1_status_en_aux1_drdy : 1;
67 uint8_t int1_status_en_ap_fsync : 1;
68 uint8_t int1_status_en_ap_agc_rdy : 1;
69 uint8_t int1_status_en_aux1_agc_rdy : 1;
70 uint8_t int1_status_en_reset_done : 1;
71 } int1_config0_t;
72
73 #define INT1_CONFIG1 0x17
74 typedef struct {
75 uint8_t int1_status_en_pll_rdy : 1;
76 uint8_t int1_status_en_wom_x : 1;
77 uint8_t int1_status_en_wom_y : 1;
78 uint8_t int1_status_en_wom_z : 1;
79 uint8_t int1_status_en_i3c_protocol_err : 1;
80 uint8_t int1_status_en_i2cm_done : 1;
81 uint8_t int1_status_en_apex_event : 1;
82 uint8_t resv_1 : 1;
83 } int1_config1_t;
84
85 #define INT1_CONFIG2 0x18
86 typedef struct {
87 uint8_t int1_polarity : 1;
88 uint8_t int1_mode : 1;
89 uint8_t int1_drive : 1;
90 uint8_t resv_1 : 5;
91 } int1_config2_t;
92
93 #define INT1_STATUS0 0x19
94 typedef struct {
95 uint8_t int1_status_fifo_full : 1;
96 uint8_t int1_status_fifo_ths : 1;
97 uint8_t int1_status_drdy : 1;
98 uint8_t int1_status_aux1_drdy : 1;
99 uint8_t int1_status_ap_fsync : 1;
100 uint8_t int1_status_ap_agc_rdy : 1;
101 uint8_t int1_status_aux1_agc_rdy : 1;
102 uint8_t int1_status_reset_done : 1;
103 } int1_status0_t;
104
105 #define INT1_STATUS1 0x1a
106 typedef struct {
107 uint8_t int1_status_pll_rdy : 1;
108 uint8_t int1_status_wom_x : 1;
109 uint8_t int1_status_wom_y : 1;
110 uint8_t int1_status_wom_z : 1;
111 uint8_t int1_status_i3c_protocol_err : 1;
112 uint8_t int1_status_i2cm_done : 1;
113 uint8_t int1_status_apex_event : 1;
114 uint8_t resv_1 : 1;
115 } int1_status1_t;
116
117 #define ACCEL_CONFIG0 0x1b
118 typedef struct {
119 uint8_t accel_odr : 4;
120 uint8_t accel_ui_fs_sel : 3;
121 uint8_t resv_1 : 1;
122 } accel_config0_t;
123
124 #define GYRO_CONFIG0 0x1c
125 typedef struct {
126 uint8_t gyro_odr : 4;
127 uint8_t gyro_ui_fs_sel : 4;
128 } gyro_config0_t;
129
130 #define FIFO_CONFIG0 0x1d
131 typedef struct {
132 uint8_t fifo_depth : 6;
133 uint8_t fifo_mode : 2;
134 } fifo_config0_t;
135
136 #define FIFO_CONFIG1_0 0x1e
137 #define FIFO_CONFIG1_1 0x1f
138 #define FIFO_CONFIG2 0x20
139 typedef struct {
140 uint8_t resv_1 : 3;
141 uint8_t fifo_wr_wm_gt_th : 1;
142 uint8_t resv_2 : 3;
143 uint8_t fifo_flush : 1;
144 } fifo_config2_t;
145
146 #define FIFO_CONFIG3 0x21
147 typedef struct {
148 uint8_t fifo_if_en : 1;
149 uint8_t fifo_accel_en : 1;
150 uint8_t fifo_gyro_en : 1;
151 uint8_t fifo_hires_en : 1;
152 uint8_t fifo_es0_en : 1;
153 uint8_t fifo_es1_en : 1;
154 uint8_t resv_1 : 2;
155 } fifo_config3_t;
156
157 #define FIFO_CONFIG4 0x22
158 typedef struct {
159 uint8_t fifo_es0_6b_9b : 1;
160 uint8_t fifo_tmst_fsync_en : 1;
161 uint8_t fifo_comp_en : 1;
162 uint8_t fifo_comp_nc_flow_cfg : 3;
163 uint8_t resv_1 : 2;
164 } fifo_config4_t;
165
166 #define TMST_WOM_CONFIG 0x23
167 typedef struct {
168 uint8_t wom_int_dur : 2;
169 uint8_t wom_int_mode : 1;
170 uint8_t wom_mode : 1;
171 uint8_t wom_en : 1;
172 uint8_t tmst_resol : 1;
173 uint8_t tmst_delta_en : 1;
174 uint8_t resv_1 : 1;
175 } tmst_wom_config_t;
176
177 #define FSYNC_CONFIG0 0x24
178 typedef struct {
179 uint8_t ap_fsync_sel : 3;
180 uint8_t ap_fsync_flag_clear_sel : 1;
181 uint8_t resv_1 : 4;
182 } fsync_config0_t;
183
184 #define FSYNC_CONFIG1 0x25
185 typedef struct {
186 uint8_t aux1_fsync_sel : 3;
187 uint8_t aux1_fsync_flag_clear_sel : 1;
188 uint8_t resv_1 : 4;
189 } fsync_config1_t;
190
191 #define RTC_CONFIG 0x26
192 typedef struct {
193 uint8_t resv_1 : 5;
194 uint8_t rtc_mode : 1;
195 uint8_t rtc_align : 1;
196 uint8_t resv_2 : 1;
197 } rtc_config_t;
198
199 #define DMP_EXT_SEN_ODR_CFG 0x27
200 typedef struct {
201 uint8_t apex_odr : 3;
202 uint8_t ext_odr : 3;
203 uint8_t ext_sensor_en : 1;
204 uint8_t resv_1 : 1;
205 } dmp_ext_sen_odr_cfg_t;
206
207 #define ODR_DECIMATE_CONFIG 0x28
208 typedef struct {
209 uint8_t accel_fifo_odr_dec : 4;
210 uint8_t gyro_fifo_odr_dec : 4;
211 } odr_decimate_config_t;
212
213 #define EDMP_APEX_EN0 0x29
214 typedef struct {
215 uint8_t tap_en : 1;
216 uint8_t reserved0 : 1;
217 uint8_t reserved1 : 1;
218 uint8_t tilt_en : 1;
219 uint8_t pedo_en : 1;
220 uint8_t ff_en : 1;
221 uint8_t r2w_en : 1;
222 uint8_t smd_en : 1;
223 } edmp_apex_en0_t;
224
225 #define EDMP_APEX_EN1 0x2a
226 typedef struct {
227 uint8_t soft_hard_iron_corr_en : 1;
228 uint8_t init_en : 1;
229 uint8_t power_save_en : 1;
230 uint8_t basic_smd_en : 1;
231 uint8_t resv_1 : 1;
232 uint8_t feature3_en : 1;
233 uint8_t edmp_enable : 1;
234 uint8_t resv_2 : 1;
235 } edmp_apex_en1_t;
236
237 #define APEX_BUFFER_MGMT 0x2b
238 typedef struct {
239 uint8_t step_count_edmp_wptr : 2;
240 uint8_t step_count_host_rptr : 2;
241 uint8_t ff_duration_edmp_wptr : 2;
242 uint8_t ff_duration_host_rptr : 2;
243 } apex_buffer_mgmt_t;
244
245 #define INTF_CONFIG0 0x2c
246 typedef struct {
247 uint8_t ap_spi_mode : 1;
248 uint8_t ap_spi_34_mode : 1;
249 uint8_t resv_1 : 3;
250 uint8_t virtual_access_aux1_en : 1;
251 uint8_t resv_2 : 2;
252 } intf_config0_t;
253
254 #define INTF_CONFIG1_OVRD 0x2d
255 typedef struct {
256 uint8_t ap_spi_mode_ovrd_val : 1;
257 uint8_t ap_spi_mode_ovrd : 1;
258 uint8_t ap_spi_34_mode_ovrd_val : 1;
259 uint8_t ap_spi_34_mode_ovrd : 1;
260 uint8_t resv_1 : 4;
261 } intf_config1_ovrd_t;
262
263 #define INTF_AUX_CONFIG 0x2e
264 typedef struct {
265 uint8_t aux1_spi_mode : 1;
266 uint8_t aux1_spi_34_mode : 1;
267 uint8_t aux2_spi_mode : 1;
268 uint8_t resv_1 : 5;
269 } intf_aux_config_t;
270
271 #define IOC_PAD_SCENARIO 0x2f
272 typedef struct {
273 uint8_t aux1_enable : 1;
274 uint8_t aux1_mode : 2;
275 uint8_t aux2_enable : 1;
276 uint8_t pads_int2_cfg : 2;
277 uint8_t resv_1 : 2;
278 } ioc_pad_scenario_t;
279
280 #define IOC_PAD_SCENARIO_AUX_OVRD 0x30
281 typedef struct {
282 uint8_t aux1_enable_ovrd_val : 1;
283 uint8_t aux1_enable_ovrd : 1;
284 uint8_t aux1_mode_ovrd_val : 2;
285 uint8_t aux1_mode_ovrd : 1;
286 uint8_t aux2_enable_ovrd_val : 1;
287 uint8_t aux2_enable_ovrd : 1;
288 uint8_t resv_1 : 1;
289 } ioc_pad_scenario_aux_ovrd_t;
290
291 #define IOC_PAD_SCENARIO_OVRD 0x31
292 typedef struct {
293 uint8_t pads_int2_cfg_ovrd_val : 2;
294 uint8_t pads_int2_cfg_ovrd : 1;
295 uint8_t resv_1 : 5;
296 } ioc_pad_scenario_ovrd_t;
297
298 #define DRIVE_CONFIG0 0x32
299 typedef struct {
300 uint8_t virtual_access_aux2_en : 1;
301 uint8_t pads_spi_slew : 3;
302 uint8_t pads_i2c_slew : 3;
303 uint8_t resv_1 : 1;
304 } drive_config0_t;
305
306 #define DRIVE_CONFIG1 0x33
307 typedef struct {
308 uint8_t pads_i3c_sdr_slew : 3;
309 uint8_t pads_i3c_ddr_slew : 3;
310 uint8_t resv_1 : 2;
311 } drive_config1_t;
312
313 #define DRIVE_CONFIG2 0x34
314 typedef struct {
315 uint8_t pads_slew : 3;
316 uint8_t resv_1 : 5;
317 } drive_config2_t;
318
319 #define REG_MISC1 0x35
320 typedef struct {
321 uint8_t osc_id_ovrd : 4;
322 uint8_t resv_1 : 4;
323 } reg_misc1_t;
324
325 #define INT_APEX_CONFIG0 0x39
326 typedef struct {
327 uint8_t int_status_mask_pin_tap_detect : 1;
328 uint8_t int_status_mask_pin_high_g_det : 1;
329 uint8_t int_status_mask_pin_low_g_det : 1;
330 uint8_t int_status_mask_pin_tilt_det : 1;
331 uint8_t int_status_mask_pin_step_cnt_ovfl : 1;
332 uint8_t int_status_mask_pin_step_det : 1;
333 uint8_t int_status_mask_pin_ff_det : 1;
334 uint8_t int_status_mask_pin_r2w_wake_det : 1;
335 } int_apex_config0_t;
336
337 #define INT_APEX_CONFIG1 0x3a
338 typedef struct {
339 uint8_t int_status_mask_pin_r2w_sleep_det : 1;
340 uint8_t int_status_mask_pin_smd_det : 1;
341 uint8_t int_status_mask_pin_selftest_done : 1;
342 uint8_t resv_1 : 1;
343 uint8_t int_status_mask_pin_sa_done : 1;
344 uint8_t int_status_mask_pin_basic_smd : 1;
345 uint8_t resv_2 : 2;
346 } int_apex_config1_t;
347
348 #define INT_APEX_STATUS0 0x3b
349 typedef struct {
350 uint8_t int_status_tap_det : 1;
351 uint8_t int_status_high_g_det : 1;
352 uint8_t int_status_low_g_det : 1;
353 uint8_t int_status_tilt_det : 1;
354 uint8_t int_status_step_cnt_ovfl : 1;
355 uint8_t int_status_step_det : 1;
356 uint8_t int_status_ff_det : 1;
357 uint8_t int_status_r2w_wake_det : 1;
358 } int_apex_status0_t;
359
360 #define INT_APEX_STATUS1 0x3c
361 typedef struct {
362 uint8_t int_status_r2w_sleep_det : 1;
363 uint8_t int_status_smd_det : 1;
364 uint8_t int_status_selftest_done : 1;
365 uint8_t resv_1 : 1;
366 uint8_t int_status_sa_done : 1;
367 uint8_t int_status_basic_smd : 1;
368 uint8_t resv_2 : 2;
369 } int_apex_status1_t;
370
371 #define INTF_CONFIG_OVRD_AUX1 0x42
372 typedef struct {
373 uint8_t aux1_spi_mode_ovrd_val : 1;
374 uint8_t aux1_spi_mode_ovrd : 1;
375 uint8_t aux1_spi_34_mode_ovrd_val : 1;
376 uint8_t aux1_spi_34_mode_ovrd : 1;
377 uint8_t aux1_ireg_auto_addr_inc_dis : 1;
378 uint8_t resv_1 : 3;
379 } intf_config_ovrd_aux1_t;
380
381 #define ACCEL_DATA_X1_AUX1 0x44
382 #define ACCEL_DATA_X0_AUX1 0x45
383 #define ACCEL_DATA_Y1_AUX1 0x46
384 #define ACCEL_DATA_Y0_AUX1 0x47
385 #define ACCEL_DATA_Z1_AUX1 0x48
386 #define ACCEL_DATA_Z0_AUX1 0x49
387 #define GYRO_DATA_X1_AUX1 0x4a
388 #define GYRO_DATA_X0_AUX1 0x4b
389 #define GYRO_DATA_Y1_AUX1 0x4c
390 #define GYRO_DATA_Y0_AUX1 0x4d
391 #define GYRO_DATA_Z1_AUX1 0x4e
392 #define GYRO_DATA_Z0_AUX1 0x4f
393 #define TEMP_DATA1_AUX1 0x50
394 #define TEMP_DATA0_AUX1 0x51
395 #define TMST_FSYNCH_AUX1 0x52
396 #define TMST_FSYNCL_AUX1 0x53
397 #define PWR_MGMT_AUX1 0x54
398 typedef struct {
399 uint8_t accel_aux1_en : 1;
400 uint8_t gyro_aux1_en : 1;
401 uint8_t resv_1 : 6;
402 } pwr_mgmt_aux1_t;
403
404 #define FS_SEL_AUX1 0x55
405 typedef struct {
406 uint8_t accel_aux1_fs_sel : 3;
407 uint8_t gyro_aux1_fs_sel : 4;
408 uint8_t resv_1 : 1;
409 } fs_sel_aux1_t;
410
411 #define INT2_CONFIG0 0x56
412 typedef struct {
413 uint8_t int2_status_en_fifo_full : 1;
414 uint8_t int2_status_en_fifo_ths : 1;
415 uint8_t int2_status_en_drdy : 1;
416 uint8_t int2_status_en_aux1_drdy : 1;
417 uint8_t int2_status_en_ap_fsync : 1;
418 uint8_t int2_status_en_ap_agc_rdy : 1;
419 uint8_t int2_status_en_aux1_agc_rdy : 1;
420 uint8_t int2_status_en_reset_done : 1;
421 } int2_config0_t;
422
423 #define INT2_CONFIG1 0x57
424 typedef struct {
425 uint8_t int2_status_en_pll_rdy : 1;
426 uint8_t int2_status_en_wom_x : 1;
427 uint8_t int2_status_en_wom_y : 1;
428 uint8_t int2_status_en_wom_z : 1;
429 uint8_t int2_status_en_i3c_protocol_err : 1;
430 uint8_t int2_status_en_i2cm_done : 1;
431 uint8_t int2_status_en_apex_event : 1;
432 uint8_t resv_1 : 1;
433 } int2_config1_t;
434
435 #define INT2_CONFIG2 0x58
436 typedef struct {
437 uint8_t int2_polarity : 1;
438 uint8_t int2_mode : 1;
439 uint8_t int2_drive : 1;
440 uint8_t resv_1 : 5;
441 } int2_config2_t;
442
443 #define INT2_STATUS0 0x59
444 typedef struct {
445 uint8_t int2_status_fifo_full : 1;
446 uint8_t int2_status_fifo_ths : 1;
447 uint8_t int2_status_drdy : 1;
448 uint8_t int2_status_aux1_drdy : 1;
449 uint8_t int2_status_ap_fsync : 1;
450 uint8_t int2_status_ap_agc_rdy : 1;
451 uint8_t int2_status_aux1_agc_rdy : 1;
452 uint8_t int2_status_reset_done : 1;
453 } int2_status0_t;
454
455 #define INT2_STATUS1 0x5a
456 typedef struct {
457 uint8_t int2_status_pll_rdy : 1;
458 uint8_t int2_status_wom_x : 1;
459 uint8_t int2_status_wom_y : 1;
460 uint8_t int2_status_wom_z : 1;
461 uint8_t int2_status_i3c_protocol_err : 1;
462 uint8_t int2_status_i2cm_done : 1;
463 uint8_t int2_status_apex_event : 1;
464 uint8_t resv_1 : 1;
465 } int2_status1_t;
466
467 #define INTF_CONFIG_OVRD_AUX2 0x5c
468 typedef struct {
469 uint8_t aux2_spi_mode_ovrd_val : 1;
470 uint8_t aux2_spi_mode_ovrd : 1;
471 uint8_t aux2_ireg_auto_addr_inc_dis : 1;
472 uint8_t resv_1 : 5;
473 } intf_config_ovrd_aux2_t;
474
475 #define ACCEL_DATA_X1_AUX2 0x5e
476 #define ACCEL_DATA_X0_AUX2 0x5f
477 #define ACCEL_DATA_Y1_AUX2 0x60
478 #define ACCEL_DATA_Y0_AUX2 0x61
479 #define ACCEL_DATA_Z1_AUX2 0x62
480 #define ACCEL_DATA_Z0_AUX2 0x63
481 #define GYRO_DATA_X1_AUX2 0x64
482 #define GYRO_DATA_X0_AUX2 0x65
483 #define GYRO_DATA_Y1_AUX2 0x66
484 #define GYRO_DATA_Y0_AUX2 0x67
485 #define GYRO_DATA_Z1_AUX2 0x68
486 #define GYRO_DATA_Z0_AUX2 0x69
487 #define TEMP_DATA1_AUX2 0x6a
488 #define TEMP_DATA0_AUX2 0x6b
489 #define TMST_FSYNCH_AUX2 0x6c
490 #define TMST_FSYNCL_AUX2 0x6d
491 #define PWR_MGMT_AUX2 0x6e
492 typedef struct {
493 uint8_t accel_aux2_en : 1;
494 uint8_t gyro_aux2_en : 1;
495 uint8_t resv_1 : 6;
496 } pwr_mgmt_aux2_t;
497
498 #define FS_SEL_AUX2 0x6f
499 typedef struct {
500 uint8_t accel_aux2_fs_sel : 3;
501 uint8_t gyro_aux2_fs_sel : 4;
502 uint8_t resv_1 : 1;
503 } fs_sel_aux2_t;
504
505 #define INT_AUX2_CONFIG 0x70
506 typedef struct {
507 uint8_t int_en_aux2_agc_rdy : 1;
508 uint8_t int_en_aux2_reset_done : 1;
509 uint8_t int_en_aux2_pll_rdy : 1;
510 uint8_t int_en_aux2_drdy : 1;
511 uint8_t resv_1 : 4;
512 } int_aux2_config_t;
513
514 #define INT_AUX2_STATUS 0x71
515 typedef struct {
516 uint8_t int_status_aux2_agc_rdy : 1;
517 uint8_t int_status_aux2_reset_done : 1;
518 uint8_t int_status_aux2_pll_rdy : 1;
519 uint8_t int_status_aux2_drdy : 1;
520 uint8_t resv_1 : 4;
521 } int_aux2_status_t;
522
523 #define WHO_AM_I 0x72
524 typedef struct {
525 uint8_t who_am_i : 8;
526 } who_am_i_t;
527
528 #define REG_HOST_MSG 0x73
529 typedef struct {
530 uint8_t testopenable : 1;
531 uint8_t resv_1 : 4;
532 uint8_t edmp_on_demand_en : 1;
533 uint8_t resv_2 : 2;
534 } reg_host_msg_t;
535
536 #define IREG_ADDR_15_8 0x7c
537 typedef struct {
538 uint8_t ireg_addr_15_8 : 8;
539 } ireg_addr_15_8_t;
540
541 #define IREG_ADDR_7_0 0x7d
542 typedef struct {
543 uint8_t ireg_addr_7_0 : 8;
544 } ireg_addr_7_0_t;
545
546 #define IREG_DATA 0x7e
547 typedef struct {
548 uint8_t ireg_data : 8;
549 } ireg_data_t;
550
551 #define REG_MISC2 0x7f
552 typedef struct {
553 uint8_t ireg_done : 1;
554 uint8_t soft_rst : 1;
555 uint8_t resv_1 : 6;
556 } reg_misc2_t;
557
558
559 /* DREG_BANK2 */
560
561 /* IPREG_TOP1 */
562 #define I2CM_COMMAND_0 0xa206
563 typedef struct {
564 uint8_t burstlen_0 : 4;
565 uint8_t r_w_0 : 2;
566 uint8_t ch_sel_0 : 1;
567 uint8_t endflag_0 : 1;
568 } i2cm_command_0_t;
569
570 #define I2CM_COMMAND_1 0xa207
571 typedef struct {
572 uint8_t burstlen_1 : 4;
573 uint8_t r_w_1 : 2;
574 uint8_t ch_sel_1 : 1;
575 uint8_t endflag_1 : 1;
576 } i2cm_command_1_t;
577
578 #define I2CM_COMMAND_2 0xa208
579 typedef struct {
580 uint8_t burstlen_2 : 4;
581 uint8_t r_w_2 : 2;
582 uint8_t ch_sel_2 : 1;
583 uint8_t endflag_2 : 1;
584 } i2cm_command_2_t;
585
586 #define I2CM_COMMAND_3 0xa209
587 typedef struct {
588 uint8_t burstlen_3 : 4;
589 uint8_t r_w_3 : 2;
590 uint8_t ch_sel_3 : 1;
591 uint8_t endflag_3 : 1;
592 } i2cm_command_3_t;
593
594 #define I2CM_DEV_PROFILE0 0xa20e
595 typedef struct {
596 uint8_t rd_address_0 : 8;
597 } i2cm_dev_profile0_t;
598
599 #define I2CM_DEV_PROFILE1 0xa20f
600 typedef struct {
601 uint8_t dev_id_0 : 7;
602 uint8_t resv_1 : 1;
603 } i2cm_dev_profile1_t;
604
605 #define I2CM_DEV_PROFILE2 0xa210
606 typedef struct {
607 uint8_t rd_address_1 : 8;
608 } i2cm_dev_profile2_t;
609
610 #define I2CM_DEV_PROFILE3 0xa211
611 typedef struct {
612 uint8_t dev_id_1 : 7;
613 uint8_t resv_1 : 1;
614 } i2cm_dev_profile3_t;
615
616 #define I2CM_CONTROL 0xa216
617 typedef struct {
618 uint8_t i2cm_go : 1;
619 uint8_t resv_1 : 2;
620 uint8_t i2cm_speed : 1;
621 uint8_t resv_2 : 2;
622 uint8_t i2cm_restart_en : 1;
623 uint8_t resv_3 : 1;
624 } i2cm_control_t;
625
626 #define I2CM_STATUS 0xa218
627 typedef struct {
628 uint8_t i2cm_busy : 1;
629 uint8_t i2cm_done : 1;
630 uint8_t i2cm_timeout_err : 1;
631 uint8_t i2cm_srst_err : 1;
632 uint8_t i2cm_scl_err : 1;
633 uint8_t i2cm_sda_err : 1;
634 uint8_t resv_1 : 2;
635 } i2cm_status_t;
636
637 #define I2CM_EXT_DEV_STATUS 0xa21a
638 typedef struct {
639 uint8_t i2cm_ext_dev_status : 4;
640 uint8_t resv_1 : 4;
641 } i2cm_ext_dev_status_t;
642
643 #define I2CM_RD_DATA0 0xa21b
644 typedef struct {
645 uint8_t i2cm_rd_data0 : 8;
646 } i2cm_rd_data0_t;
647
648 #define I2CM_RD_DATA1 0xa21c
649 typedef struct {
650 uint8_t i2cm_rd_data1 : 8;
651 } i2cm_rd_data1_t;
652
653 #define I2CM_RD_DATA2 0xa21d
654 typedef struct {
655 uint8_t i2cm_rd_data2 : 8;
656 } i2cm_rd_data2_t;
657
658 #define I2CM_RD_DATA3 0xa21e
659 typedef struct {
660 uint8_t i2cm_rd_data3 : 8;
661 } i2cm_rd_data3_t;
662
663 #define I2CM_RD_DATA4 0xa21f
664 typedef struct {
665 uint8_t i2cm_rd_data4 : 8;
666 } i2cm_rd_data4_t;
667
668 #define I2CM_RD_DATA5 0xa220
669 typedef struct {
670 uint8_t i2cm_rd_data5 : 8;
671 } i2cm_rd_data5_t;
672
673 #define I2CM_RD_DATA6 0xa221
674 typedef struct {
675 uint8_t i2cm_rd_data6 : 8;
676 } i2cm_rd_data6_t;
677
678 #define I2CM_RD_DATA7 0xa222
679 typedef struct {
680 uint8_t i2cm_rd_data7 : 8;
681 } i2cm_rd_data7_t;
682
683 #define I2CM_RD_DATA8 0xa223
684 typedef struct {
685 uint8_t i2cm_rd_data8 : 8;
686 } i2cm_rd_data8_t;
687
688 #define I2CM_RD_DATA9 0xa224
689 typedef struct {
690 uint8_t i2cm_rd_data9 : 8;
691 } i2cm_rd_data9_t;
692
693 #define I2CM_RD_DATA10 0xa225
694 typedef struct {
695 uint8_t i2cm_rd_data10 : 8;
696 } i2cm_rd_data10_t;
697
698 #define I2CM_RD_DATA11 0xa226
699 typedef struct {
700 uint8_t i2cm_rd_data11 : 8;
701 } i2cm_rd_data11_t;
702
703 #define I2CM_RD_DATA12 0xa227
704 typedef struct {
705 uint8_t i2cm_rd_data12 : 8;
706 } i2cm_rd_data12_t;
707
708 #define I2CM_RD_DATA13 0xa228
709 typedef struct {
710 uint8_t i2cm_rd_data13 : 8;
711 } i2cm_rd_data13_t;
712
713 #define I2CM_RD_DATA14 0xa229
714 typedef struct {
715 uint8_t i2cm_rd_data14 : 8;
716 } i2cm_rd_data14_t;
717
718 #define I2CM_RD_DATA15 0xa22a
719 typedef struct {
720 uint8_t i2cm_rd_data15 : 8;
721 } i2cm_rd_data15_t;
722
723 #define I2CM_RD_DATA16 0xa22b
724 typedef struct {
725 uint8_t i2cm_rd_data16 : 8;
726 } i2cm_rd_data16_t;
727
728 #define I2CM_RD_DATA17 0xa22c
729 typedef struct {
730 uint8_t i2cm_rd_data17 : 8;
731 } i2cm_rd_data17_t;
732
733 #define I2CM_RD_DATA18 0xa22d
734 typedef struct {
735 uint8_t i2cm_rd_data18 : 8;
736 } i2cm_rd_data18_t;
737
738 #define I2CM_RD_DATA19 0xa22e
739 typedef struct {
740 uint8_t i2cm_rd_data19 : 8;
741 } i2cm_rd_data19_t;
742
743 #define I2CM_RD_DATA20 0xa22f
744 typedef struct {
745 uint8_t i2cm_rd_data20 : 8;
746 } i2cm_rd_data20_t;
747
748 #define I2CM_WR_DATA0 0xa233
749 typedef struct {
750 uint8_t i2cm_wr_data0 : 8;
751 } i2cm_wr_data0_t;
752
753 #define I2CM_WR_DATA1 0xa234
754 typedef struct {
755 uint8_t i2cm_wr_data1 : 8;
756 } i2cm_wr_data1_t;
757
758 #define I2CM_WR_DATA2 0xa235
759 typedef struct {
760 uint8_t i2cm_wr_data2 : 8;
761 } i2cm_wr_data2_t;
762
763 #define I2CM_WR_DATA3 0xa236
764 typedef struct {
765 uint8_t i2cm_wr_data3 : 8;
766 } i2cm_wr_data3_t;
767
768 #define I2CM_WR_DATA4 0xa237
769 typedef struct {
770 uint8_t i2cm_wr_data4 : 8;
771 } i2cm_wr_data4_t;
772
773 #define I2CM_WR_DATA5 0xa238
774 typedef struct {
775 uint8_t i2cm_wr_data5 : 8;
776 } i2cm_wr_data5_t;
777
778 #define SIFS_IXC_ERROR_STATUS 0xa24b
779 typedef struct {
780 uint8_t sifs_ixc_timeout_err : 1;
781 uint8_t aux1_sifs_ixc_timeout_err : 1;
782 uint8_t resv_1 : 6;
783 } sifs_ixc_error_status_t;
784
785 #define EDMP_PRGRM_IRQ0_0 0xa24f
786 #define EDMP_PRGRM_IRQ0_1 0xa250
787 #define EDMP_PRGRM_IRQ1_0 0xa251
788 #define EDMP_PRGRM_IRQ1_1 0xa252
789 #define EDMP_PRGRM_IRQ2_0 0xa253
790 #define EDMP_PRGRM_IRQ2_1 0xa254
791 #define EDMP_SP_START_ADDR 0xa255
792 typedef struct {
793 uint8_t edmp_sp_start_addr : 8;
794 } edmp_sp_start_addr_t;
795
796 #define SMC_CONTROL_0 0xa258
797 typedef struct {
798 uint8_t tmst_en : 1;
799 uint8_t tmst_fsync_en : 1;
800 uint8_t tmst_force_aux_fine_en : 1;
801 uint8_t temp_dis : 1;
802 uint8_t accel_lp_clk_sel : 1;
803 uint8_t resv_1 : 3;
804 } smc_control_0_t;
805
806 #define SMC_CONTROL_1 0xa259
807 typedef struct {
808 uint8_t resv_1 : 3;
809 uint8_t sreg_aux_accel_only_en : 1;
810 uint8_t resv_2 : 4;
811 } smc_control_1_t;
812
813 #define STC_CONFIG 0xa263
814 typedef struct {
815 uint8_t resv_1 : 2;
816 uint8_t stc_sensor_sel : 2;
817 uint8_t resv_2 : 4;
818 } stc_config_t;
819
820 #define SREG_CTRL 0xa267
821 typedef struct {
822 uint8_t resv_1 : 1;
823 uint8_t sreg_data_endian_sel : 1;
824 uint8_t resv_2 : 6;
825 } sreg_ctrl_t;
826
827 #define SIFS_I3C_STC_CFG 0xa268
828 typedef struct {
829 uint8_t resv_1 : 2;
830 uint8_t i3c_stc_mode : 1;
831 uint8_t resv_2 : 5;
832 } sifs_i3c_stc_cfg_t;
833
834 #define INT_PULSE_MIN_ON_INTF0 0xa269
835 typedef struct {
836 uint8_t int0_tpulse_duration : 3;
837 uint8_t resv_1 : 5;
838 } int_pulse_min_on_intf0_t;
839
840 #define INT_PULSE_MIN_ON_INTF1 0xa26a
841 typedef struct {
842 uint8_t int1_tpulse_duration : 3;
843 uint8_t resv_1 : 5;
844 } int_pulse_min_on_intf1_t;
845
846 #define INT_PULSE_MIN_OFF_INTF0 0xa26b
847 typedef struct {
848 uint8_t int0_tdeassert_disable : 3;
849 uint8_t resv_1 : 5;
850 } int_pulse_min_off_intf0_t;
851
852 #define INT_PULSE_MIN_OFF_INTF1 0xa26c
853 typedef struct {
854 uint8_t int1_tdeassert_disable : 3;
855 uint8_t resv_1 : 5;
856 } int_pulse_min_off_intf1_t;
857
858 #define ISR_0_7 0xa26e
859 typedef struct {
860 uint8_t int_status_accel_drdy_pin_0 : 1;
861 uint8_t resv_1 : 2;
862 uint8_t int_status_ext_odr_drdy_pin_0 : 1;
863 uint8_t resv_2 : 1;
864 uint8_t int_status_on_demand_pin_0 : 1;
865 uint8_t resv_3 : 2;
866 } isr_0_7_t;
867
868 #define ISR_8_15 0xa26f
869 typedef struct {
870 uint8_t int_status_accel_drdy_pin_1 : 1;
871 uint8_t resv_1 : 2;
872 uint8_t int_status_ext_odr_drdy_pin_1 : 1;
873 uint8_t resv_2 : 1;
874 uint8_t int_status_on_demand_pin_1 : 1;
875 uint8_t resv_3 : 2;
876 } isr_8_15_t;
877
878 #define ISR_16_23 0xa270
879 typedef struct {
880 uint8_t int_status_accel_drdy_pin_2 : 1;
881 uint8_t resv_1 : 2;
882 uint8_t int_status_ext_odr_drdy_pin_2 : 1;
883 uint8_t resv_2 : 1;
884 uint8_t int_status_on_demand_pin_2 : 1;
885 uint8_t resv_3 : 2;
886 } isr_16_23_t;
887
888 #define STATUS_MASK_PIN_0_7 0xa271
889 typedef struct {
890 uint8_t int_accel_drdy_pin_0_dis : 1;
891 uint8_t resv_1 : 2;
892 uint8_t int_ext_odr_drdy_pin_0_dis : 1;
893 uint8_t resv_2 : 1;
894 uint8_t int_on_demand_pin_0_dis : 1;
895 uint8_t resv_3 : 2;
896 } status_mask_pin_0_7_t;
897
898 #define STATUS_MASK_PIN_8_15 0xa272
899 typedef struct {
900 uint8_t int_accel_drdy_pin_1_dis : 1;
901 uint8_t resv_1 : 2;
902 uint8_t int_ext_odr_drdy_pin_1_dis : 1;
903 uint8_t resv_2 : 1;
904 uint8_t int_on_demand_pin_1_dis : 1;
905 uint8_t resv_3 : 2;
906 } status_mask_pin_8_15_t;
907
908 #define STATUS_MASK_PIN_16_23 0xa273
909 typedef struct {
910 uint8_t int_accel_drdy_pin_2_dis : 1;
911 uint8_t resv_1 : 2;
912 uint8_t int_ext_odr_drdy_pin_2_dis : 1;
913 uint8_t resv_2 : 1;
914 uint8_t int_on_demand_pin_2_dis : 1;
915 uint8_t resv_3 : 2;
916 } status_mask_pin_16_23_t;
917
918 #define INT_I2CM_SOURCE 0xa274
919 typedef struct {
920 uint8_t int_status_i2cm_ioc_ext_trig_en : 1;
921 uint8_t int_status_i2cm_smc_ext_odr_en : 1;
922 uint8_t resv_1 : 6;
923 } int_i2cm_source_t;
924
925 #define ACCEL_WOM_X_THR 0xa27e
926 typedef struct {
927 uint8_t wom_x_th : 8;
928 } accel_wom_x_thr_t;
929
930 #define ACCEL_WOM_Y_THR 0xa27f
931 typedef struct {
932 uint8_t wom_y_th : 8;
933 } accel_wom_y_thr_t;
934
935 #define ACCEL_WOM_Z_THR 0xa280
936 typedef struct {
937 uint8_t wom_z_th : 8;
938 } accel_wom_z_thr_t;
939
940 #define SELFTEST 0xa290
941 typedef struct {
942 uint8_t en_ax_st : 1;
943 uint8_t en_ay_st : 1;
944 uint8_t en_az_st : 1;
945 uint8_t en_gx_st : 1;
946 uint8_t en_gy_st : 1;
947 uint8_t en_gz_st : 1;
948 uint8_t resv_1 : 2;
949 } selftest_t;
950
951 #define IPREG_MISC 0xa297
952 typedef struct {
953 uint8_t resv_1 : 1;
954 uint8_t edmp_idle : 1;
955 uint8_t resv_2 : 6;
956 } ipreg_misc_t;
957
958 #define SW_PLL1_TRIM 0xa2a2
959 typedef struct {
960 uint8_t sw_pll1_trim : 8;
961 } sw_pll1_trim_t;
962
963 #define FIFO_SRAM_SLEEP 0xa2a7
964 typedef struct {
965 uint8_t fifo_gsleep_shared_sram : 2;
966 uint8_t resv_1 : 6;
967 } fifo_sram_sleep_t;
968
969
970 /* IPREG_SYS1 */
971 #define IPREG_SYS1_REG_42 0xa42a
972 #define IPREG_SYS1_REG_43 0xa42b
973 #define IPREG_SYS1_REG_56 0xa438
974 #define IPREG_SYS1_REG_57 0xa439
975 #define IPREG_SYS1_REG_70 0xa446
976 #define IPREG_SYS1_REG_71 0xa447
977 #define IPREG_SYS1_REG_166 0xa4a6
978 typedef struct {
979 uint8_t resv_1 : 3;
980 uint8_t gyro_afsr_mode : 2;
981 uint8_t gyro_src_ctrl : 2;
982 uint8_t resv_2 : 1;
983 } ipreg_sys1_reg_166_t;
984
985 #define IPREG_SYS1_REG_168 0xa4a8
986 typedef struct {
987 uint8_t gyro_afsr_shared : 1;
988 uint8_t gyro_ois_m6_byp : 1;
989 uint8_t resv_1 : 6;
990 } ipreg_sys1_reg_168_t;
991
992 #define IPREG_SYS1_REG_170 0xa4aa
993 typedef struct {
994 uint8_t resv_1 : 1;
995 uint8_t gyro_lp_avg_sel : 4;
996 uint8_t gyro_ois_hpfbw_sel : 3;
997 } ipreg_sys1_reg_170_t;
998
999 #define IPREG_SYS1_REG_171 0xa4ab
1000 typedef struct {
1001 uint8_t gyro_ois_lpf1bw_sel : 3;
1002 uint8_t gyro_ois_lpf2bw_sel : 3;
1003 uint8_t resv_1 : 2;
1004 } ipreg_sys1_reg_171_t;
1005
1006 #define IPREG_SYS1_REG_172 0xa4ac
1007 typedef struct {
1008 uint8_t gyro_ui_lpfbw_sel : 3;
1009 uint8_t resv_1 : 4;
1010 uint8_t gyro_ois_hpf1_byp : 1;
1011 } ipreg_sys1_reg_172_t;
1012
1013 #define IPREG_SYS1_REG_173 0xa4ad
1014 typedef struct {
1015 uint8_t gyro_ois_hpf2_byp : 1;
1016 uint8_t resv_1 : 7;
1017 } ipreg_sys1_reg_173_t;
1018
1019
1020 /* IPREG_SYS2 */
1021 #define IPREG_SYS2_REG_24 0xa518
1022 #define IPREG_SYS2_REG_25 0xa519
1023 #define IPREG_SYS2_REG_32 0xa520
1024 #define IPREG_SYS2_REG_33 0xa521
1025 #define IPREG_SYS2_REG_40 0xa528
1026 #define IPREG_SYS2_REG_41 0xa529
1027 #define IPREG_SYS2_REG_123 0xa57b
1028 typedef struct {
1029 uint8_t accel_src_ctrl : 2;
1030 uint8_t resv_1 : 6;
1031 } ipreg_sys2_reg_123_t;
1032
1033 #define IPREG_SYS2_REG_129 0xa581
1034 typedef struct {
1035 uint8_t accel_lp_avg_sel : 4;
1036 uint8_t accel_ois_hpfbw_sel : 3;
1037 uint8_t resv_1 : 1;
1038 } ipreg_sys2_reg_129_t;
1039
1040 #define IPREG_SYS2_REG_130 0xa582
1041 typedef struct {
1042 uint8_t accel_ois_lpf1bw_sel : 3;
1043 uint8_t accel_ois_lpf2bw_sel : 3;
1044 uint8_t resv_1 : 2;
1045 } ipreg_sys2_reg_130_t;
1046
1047 #define IPREG_SYS2_REG_131 0xa583
1048 typedef struct {
1049 uint8_t accel_ui_lpfbw_sel : 3;
1050 uint8_t resv_1 : 5;
1051 } ipreg_sys2_reg_131_t;
1052
1053 #define IPREG_SYS2_REG_132 0xa584
1054 typedef struct {
1055 uint8_t accel_ois_hpf1_byp : 1;
1056 uint8_t accel_ois_hpf2_byp : 1;
1057 uint8_t accel_ois_m6_byp : 1;
1058 uint8_t resv_1 : 5;
1059 } ipreg_sys2_reg_132_t;
1060
1061
1062 /* IPREG_OTP */
1063
1064 /* IPREG_BAR */
1065 #define IPREG_BAR_REG_57 0xa039
1066 typedef struct {
1067 uint8_t resv_1 : 5;
1068 uint8_t io_opt1 : 1;
1069 uint8_t io_opt0 : 1;
1070 uint8_t resv_2 : 1;
1071 } ipreg_bar_reg_57_t;
1072
1073 #define IPREG_BAR_REG_58 0xa03a
1074 typedef struct {
1075 uint8_t io_opt2 : 1;
1076 uint8_t resv_1 : 2;
1077 uint8_t pads_ap_cs_pe_trim_d2a : 1;
1078 uint8_t pads_ap_cs_pud_trim_d2a : 1;
1079 uint8_t resv_2 : 1;
1080 uint8_t pads_ap_sclk_pe_trim_d2a : 1;
1081 uint8_t pads_ap_sclk_pud_trim_d2a : 1;
1082 } ipreg_bar_reg_58_t;
1083
1084 #define IPREG_BAR_REG_59 0xa03b
1085 typedef struct {
1086 uint8_t resv_1 : 1;
1087 uint8_t pads_ap_sdi_pe_trim_d2a : 1;
1088 uint8_t pads_ap_sdi_pud_trim_d2a : 1;
1089 uint8_t resv_2 : 1;
1090 uint8_t pads_ap_sdo_pe_trim_d2a : 1;
1091 uint8_t pads_ap_sdo_pud_trim_d2a : 1;
1092 uint8_t resv_3 : 1;
1093 uint8_t pads_pin7_pe_trim_d2a : 1;
1094 } ipreg_bar_reg_59_t;
1095
1096 #define IPREG_BAR_REG_60 0xa03c
1097 typedef struct {
1098 uint8_t pads_pin7_cs_pud_trim_d2a : 1;
1099 uint8_t resv_1 : 1;
1100 uint8_t pads_aux1_cs_pe_trim_d2a : 1;
1101 uint8_t pads_aux1_cs_pud_trim_d2a : 1;
1102 uint8_t pads_aux_sclk_tp2_from_pad_disable_trim_d2a : 1;
1103 uint8_t pads_aux1_sclk_pe_trim_d2a : 1;
1104 uint8_t pads_aux1_sclk_pud_trim_d2a : 1;
1105 uint8_t resv_2 : 1;
1106 } ipreg_bar_reg_60_t;
1107
1108 #define IPREG_BAR_REG_61 0xa03d
1109 typedef struct {
1110 uint8_t pads_aux1_sdi_pe_trim_d2a : 1;
1111 uint8_t pads_aux1_sdi_pud_trim_d2a : 1;
1112 uint8_t resv_1 : 1;
1113 uint8_t pads_aux1_sdo_pe_trim_d2a : 1;
1114 uint8_t pads_aux1_sdo_pud_trim_d2a : 1;
1115 uint8_t resv_2 : 1;
1116 uint8_t pads_int1_pe_trim_d2a : 1;
1117 uint8_t pads_int1_pud_trim_d2a : 1;
1118 } ipreg_bar_reg_61_t;
1119
1120 #define IPREG_BAR_REG_62 0xa03e
1121 typedef struct {
1122 uint8_t resv_1 : 1;
1123 uint8_t pads_int2_pe_trim_d2a : 1;
1124 uint8_t pads_int2_pud_trim_d2a : 1;
1125 uint8_t resv_2 : 5;
1126 } ipreg_bar_reg_62_t;
1127
1128
1129
1130 #ifdef __cplusplus
1131 }
1132 #endif
1133
1134 #endif /*#ifndef _INV_IMU_REGMAP_LE_H_*/
pwr_mgmt0_t
Definition: inv_imu_regmap_le.h:48
pwr_mgmt0_t::accel_mode
uint8_t accel_mode
Definition: inv_imu_regmap_le.h:49
pwr_mgmt0_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:51
pwr_mgmt0_t::gyro_mode
uint8_t gyro_mode
Definition: inv_imu_regmap_le.h:50
fifo_data_t
Definition: inv_imu_regmap_le.h:57
fifo_data_t::fifo_data
uint8_t fifo_data
Definition: inv_imu_regmap_le.h:58
int1_config0_t
Definition: inv_imu_regmap_le.h:62
int1_config0_t::int1_status_en_aux1_drdy
uint8_t int1_status_en_aux1_drdy
Definition: inv_imu_regmap_le.h:66
int1_config0_t::int1_status_en_fifo_ths
uint8_t int1_status_en_fifo_ths
Definition: inv_imu_regmap_le.h:64
int1_config0_t::int1_status_en_aux1_agc_rdy
uint8_t int1_status_en_aux1_agc_rdy
Definition: inv_imu_regmap_le.h:69
int1_config0_t::int1_status_en_ap_agc_rdy
uint8_t int1_status_en_ap_agc_rdy
Definition: inv_imu_regmap_le.h:68
int1_config0_t::int1_status_en_fifo_full
uint8_t int1_status_en_fifo_full
Definition: inv_imu_regmap_le.h:63
int1_config0_t::int1_status_en_ap_fsync
uint8_t int1_status_en_ap_fsync
Definition: inv_imu_regmap_le.h:67
int1_config0_t::int1_status_en_reset_done
uint8_t int1_status_en_reset_done
Definition: inv_imu_regmap_le.h:70
int1_config0_t::int1_status_en_drdy
uint8_t int1_status_en_drdy
Definition: inv_imu_regmap_le.h:65
int1_config1_t
Definition: inv_imu_regmap_le.h:74
int1_config1_t::int1_status_en_wom_y
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Definition: inv_imu_regmap_le.h:180
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rtc_config_t::rtc_align
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dmp_ext_sen_odr_cfg_t
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edmp_apex_en0_t
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edmp_apex_en0_t::r2w_en
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edmp_apex_en1_t
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apex_buffer_mgmt_t
Definition: inv_imu_regmap_le.h:238
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Definition: inv_imu_regmap_le.h:264
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Definition: inv_imu_regmap_le.h:510
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i2cm_rd_data11_t
Definition: inv_imu_regmap_le.h:699
i2cm_rd_data11_t::i2cm_rd_data11
uint8_t i2cm_rd_data11
Definition: inv_imu_regmap_le.h:700
i2cm_rd_data12_t
Definition: inv_imu_regmap_le.h:704
i2cm_rd_data12_t::i2cm_rd_data12
uint8_t i2cm_rd_data12
Definition: inv_imu_regmap_le.h:705
i2cm_rd_data13_t
Definition: inv_imu_regmap_le.h:709
i2cm_rd_data13_t::i2cm_rd_data13
uint8_t i2cm_rd_data13
Definition: inv_imu_regmap_le.h:710
i2cm_rd_data14_t
Definition: inv_imu_regmap_le.h:714
i2cm_rd_data14_t::i2cm_rd_data14
uint8_t i2cm_rd_data14
Definition: inv_imu_regmap_le.h:715
i2cm_rd_data15_t
Definition: inv_imu_regmap_le.h:719
i2cm_rd_data15_t::i2cm_rd_data15
uint8_t i2cm_rd_data15
Definition: inv_imu_regmap_le.h:720
i2cm_rd_data16_t
Definition: inv_imu_regmap_le.h:724
i2cm_rd_data16_t::i2cm_rd_data16
uint8_t i2cm_rd_data16
Definition: inv_imu_regmap_le.h:725
i2cm_rd_data17_t
Definition: inv_imu_regmap_le.h:729
i2cm_rd_data17_t::i2cm_rd_data17
uint8_t i2cm_rd_data17
Definition: inv_imu_regmap_le.h:730
i2cm_rd_data18_t
Definition: inv_imu_regmap_le.h:734
i2cm_rd_data18_t::i2cm_rd_data18
uint8_t i2cm_rd_data18
Definition: inv_imu_regmap_le.h:735
i2cm_rd_data19_t
Definition: inv_imu_regmap_le.h:739
i2cm_rd_data19_t::i2cm_rd_data19
uint8_t i2cm_rd_data19
Definition: inv_imu_regmap_le.h:740
i2cm_rd_data20_t
Definition: inv_imu_regmap_le.h:744
i2cm_rd_data20_t::i2cm_rd_data20
uint8_t i2cm_rd_data20
Definition: inv_imu_regmap_le.h:745
i2cm_wr_data0_t
Definition: inv_imu_regmap_le.h:749
i2cm_wr_data0_t::i2cm_wr_data0
uint8_t i2cm_wr_data0
Definition: inv_imu_regmap_le.h:750
i2cm_wr_data1_t
Definition: inv_imu_regmap_le.h:754
i2cm_wr_data1_t::i2cm_wr_data1
uint8_t i2cm_wr_data1
Definition: inv_imu_regmap_le.h:755
i2cm_wr_data2_t
Definition: inv_imu_regmap_le.h:759
i2cm_wr_data2_t::i2cm_wr_data2
uint8_t i2cm_wr_data2
Definition: inv_imu_regmap_le.h:760
i2cm_wr_data3_t
Definition: inv_imu_regmap_le.h:764
i2cm_wr_data3_t::i2cm_wr_data3
uint8_t i2cm_wr_data3
Definition: inv_imu_regmap_le.h:765
i2cm_wr_data4_t
Definition: inv_imu_regmap_le.h:769
i2cm_wr_data4_t::i2cm_wr_data4
uint8_t i2cm_wr_data4
Definition: inv_imu_regmap_le.h:770
i2cm_wr_data5_t
Definition: inv_imu_regmap_le.h:774
i2cm_wr_data5_t::i2cm_wr_data5
uint8_t i2cm_wr_data5
Definition: inv_imu_regmap_le.h:775
sifs_ixc_error_status_t
Definition: inv_imu_regmap_le.h:779
sifs_ixc_error_status_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:782
sifs_ixc_error_status_t::aux1_sifs_ixc_timeout_err
uint8_t aux1_sifs_ixc_timeout_err
Definition: inv_imu_regmap_le.h:781
sifs_ixc_error_status_t::sifs_ixc_timeout_err
uint8_t sifs_ixc_timeout_err
Definition: inv_imu_regmap_le.h:780
edmp_sp_start_addr_t
Definition: inv_imu_regmap_le.h:792
edmp_sp_start_addr_t::edmp_sp_start_addr
uint8_t edmp_sp_start_addr
Definition: inv_imu_regmap_le.h:793
smc_control_0_t
Definition: inv_imu_regmap_le.h:797
smc_control_0_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:803
smc_control_0_t::accel_lp_clk_sel
uint8_t accel_lp_clk_sel
Definition: inv_imu_regmap_le.h:802
smc_control_0_t::tmst_en
uint8_t tmst_en
Definition: inv_imu_regmap_le.h:798
smc_control_0_t::temp_dis
uint8_t temp_dis
Definition: inv_imu_regmap_le.h:801
smc_control_0_t::tmst_force_aux_fine_en
uint8_t tmst_force_aux_fine_en
Definition: inv_imu_regmap_le.h:800
smc_control_0_t::tmst_fsync_en
uint8_t tmst_fsync_en
Definition: inv_imu_regmap_le.h:799
smc_control_1_t
Definition: inv_imu_regmap_le.h:807
smc_control_1_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:808
smc_control_1_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:810
smc_control_1_t::sreg_aux_accel_only_en
uint8_t sreg_aux_accel_only_en
Definition: inv_imu_regmap_le.h:809
stc_config_t
Definition: inv_imu_regmap_le.h:814
stc_config_t::stc_sensor_sel
uint8_t stc_sensor_sel
Definition: inv_imu_regmap_le.h:816
stc_config_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:817
stc_config_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:815
sreg_ctrl_t
Definition: inv_imu_regmap_le.h:821
sreg_ctrl_t::sreg_data_endian_sel
uint8_t sreg_data_endian_sel
Definition: inv_imu_regmap_le.h:823
sreg_ctrl_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:824
sreg_ctrl_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:822
sifs_i3c_stc_cfg_t
Definition: inv_imu_regmap_le.h:828
sifs_i3c_stc_cfg_t::i3c_stc_mode
uint8_t i3c_stc_mode
Definition: inv_imu_regmap_le.h:830
sifs_i3c_stc_cfg_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:831
sifs_i3c_stc_cfg_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:829
int_pulse_min_on_intf0_t
Definition: inv_imu_regmap_le.h:835
int_pulse_min_on_intf0_t::int0_tpulse_duration
uint8_t int0_tpulse_duration
Definition: inv_imu_regmap_le.h:836
int_pulse_min_on_intf0_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:837
int_pulse_min_on_intf1_t
Definition: inv_imu_regmap_le.h:841
int_pulse_min_on_intf1_t::int1_tpulse_duration
uint8_t int1_tpulse_duration
Definition: inv_imu_regmap_le.h:842
int_pulse_min_on_intf1_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:843
int_pulse_min_off_intf0_t
Definition: inv_imu_regmap_le.h:847
int_pulse_min_off_intf0_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:849
int_pulse_min_off_intf0_t::int0_tdeassert_disable
uint8_t int0_tdeassert_disable
Definition: inv_imu_regmap_le.h:848
int_pulse_min_off_intf1_t
Definition: inv_imu_regmap_le.h:853
int_pulse_min_off_intf1_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:855
int_pulse_min_off_intf1_t::int1_tdeassert_disable
uint8_t int1_tdeassert_disable
Definition: inv_imu_regmap_le.h:854
isr_0_7_t
Definition: inv_imu_regmap_le.h:859
isr_0_7_t::int_status_on_demand_pin_0
uint8_t int_status_on_demand_pin_0
Definition: inv_imu_regmap_le.h:864
isr_0_7_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:863
isr_0_7_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:861
isr_0_7_t::resv_3
uint8_t resv_3
Definition: inv_imu_regmap_le.h:865
isr_0_7_t::int_status_ext_odr_drdy_pin_0
uint8_t int_status_ext_odr_drdy_pin_0
Definition: inv_imu_regmap_le.h:862
isr_0_7_t::int_status_accel_drdy_pin_0
uint8_t int_status_accel_drdy_pin_0
Definition: inv_imu_regmap_le.h:860
isr_8_15_t
Definition: inv_imu_regmap_le.h:869
isr_8_15_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:873
isr_8_15_t::int_status_on_demand_pin_1
uint8_t int_status_on_demand_pin_1
Definition: inv_imu_regmap_le.h:874
isr_8_15_t::resv_3
uint8_t resv_3
Definition: inv_imu_regmap_le.h:875
isr_8_15_t::int_status_ext_odr_drdy_pin_1
uint8_t int_status_ext_odr_drdy_pin_1
Definition: inv_imu_regmap_le.h:872
isr_8_15_t::int_status_accel_drdy_pin_1
uint8_t int_status_accel_drdy_pin_1
Definition: inv_imu_regmap_le.h:870
isr_8_15_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:871
isr_16_23_t
Definition: inv_imu_regmap_le.h:879
isr_16_23_t::int_status_accel_drdy_pin_2
uint8_t int_status_accel_drdy_pin_2
Definition: inv_imu_regmap_le.h:880
isr_16_23_t::int_status_ext_odr_drdy_pin_2
uint8_t int_status_ext_odr_drdy_pin_2
Definition: inv_imu_regmap_le.h:882
isr_16_23_t::int_status_on_demand_pin_2
uint8_t int_status_on_demand_pin_2
Definition: inv_imu_regmap_le.h:884
isr_16_23_t::resv_3
uint8_t resv_3
Definition: inv_imu_regmap_le.h:885
isr_16_23_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:881
isr_16_23_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:883
status_mask_pin_0_7_t
Definition: inv_imu_regmap_le.h:889
status_mask_pin_0_7_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:891
status_mask_pin_0_7_t::resv_3
uint8_t resv_3
Definition: inv_imu_regmap_le.h:895
status_mask_pin_0_7_t::int_accel_drdy_pin_0_dis
uint8_t int_accel_drdy_pin_0_dis
Definition: inv_imu_regmap_le.h:890
status_mask_pin_0_7_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:893
status_mask_pin_0_7_t::int_ext_odr_drdy_pin_0_dis
uint8_t int_ext_odr_drdy_pin_0_dis
Definition: inv_imu_regmap_le.h:892
status_mask_pin_0_7_t::int_on_demand_pin_0_dis
uint8_t int_on_demand_pin_0_dis
Definition: inv_imu_regmap_le.h:894
status_mask_pin_8_15_t
Definition: inv_imu_regmap_le.h:899
status_mask_pin_8_15_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:901
status_mask_pin_8_15_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:903
status_mask_pin_8_15_t::int_on_demand_pin_1_dis
uint8_t int_on_demand_pin_1_dis
Definition: inv_imu_regmap_le.h:904
status_mask_pin_8_15_t::int_accel_drdy_pin_1_dis
uint8_t int_accel_drdy_pin_1_dis
Definition: inv_imu_regmap_le.h:900
status_mask_pin_8_15_t::int_ext_odr_drdy_pin_1_dis
uint8_t int_ext_odr_drdy_pin_1_dis
Definition: inv_imu_regmap_le.h:902
status_mask_pin_8_15_t::resv_3
uint8_t resv_3
Definition: inv_imu_regmap_le.h:905
status_mask_pin_16_23_t
Definition: inv_imu_regmap_le.h:909
status_mask_pin_16_23_t::resv_3
uint8_t resv_3
Definition: inv_imu_regmap_le.h:915
status_mask_pin_16_23_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:913
status_mask_pin_16_23_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:911
status_mask_pin_16_23_t::int_on_demand_pin_2_dis
uint8_t int_on_demand_pin_2_dis
Definition: inv_imu_regmap_le.h:914
status_mask_pin_16_23_t::int_ext_odr_drdy_pin_2_dis
uint8_t int_ext_odr_drdy_pin_2_dis
Definition: inv_imu_regmap_le.h:912
status_mask_pin_16_23_t::int_accel_drdy_pin_2_dis
uint8_t int_accel_drdy_pin_2_dis
Definition: inv_imu_regmap_le.h:910
int_i2cm_source_t
Definition: inv_imu_regmap_le.h:919
int_i2cm_source_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:922
int_i2cm_source_t::int_status_i2cm_smc_ext_odr_en
uint8_t int_status_i2cm_smc_ext_odr_en
Definition: inv_imu_regmap_le.h:921
int_i2cm_source_t::int_status_i2cm_ioc_ext_trig_en
uint8_t int_status_i2cm_ioc_ext_trig_en
Definition: inv_imu_regmap_le.h:920
accel_wom_x_thr_t
Definition: inv_imu_regmap_le.h:926
accel_wom_x_thr_t::wom_x_th
uint8_t wom_x_th
Definition: inv_imu_regmap_le.h:927
accel_wom_y_thr_t
Definition: inv_imu_regmap_le.h:931
accel_wom_y_thr_t::wom_y_th
uint8_t wom_y_th
Definition: inv_imu_regmap_le.h:932
accel_wom_z_thr_t
Definition: inv_imu_regmap_le.h:936
accel_wom_z_thr_t::wom_z_th
uint8_t wom_z_th
Definition: inv_imu_regmap_le.h:937
selftest_t
Definition: inv_imu_regmap_le.h:941
selftest_t::en_ay_st
uint8_t en_ay_st
Definition: inv_imu_regmap_le.h:943
selftest_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:948
selftest_t::en_ax_st
uint8_t en_ax_st
Definition: inv_imu_regmap_le.h:942
selftest_t::en_az_st
uint8_t en_az_st
Definition: inv_imu_regmap_le.h:944
selftest_t::en_gy_st
uint8_t en_gy_st
Definition: inv_imu_regmap_le.h:946
selftest_t::en_gx_st
uint8_t en_gx_st
Definition: inv_imu_regmap_le.h:945
selftest_t::en_gz_st
uint8_t en_gz_st
Definition: inv_imu_regmap_le.h:947
ipreg_misc_t
Definition: inv_imu_regmap_le.h:952
ipreg_misc_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:953
ipreg_misc_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:955
ipreg_misc_t::edmp_idle
uint8_t edmp_idle
Definition: inv_imu_regmap_le.h:954
sw_pll1_trim_t
Definition: inv_imu_regmap_le.h:959
sw_pll1_trim_t::sw_pll1_trim
uint8_t sw_pll1_trim
Definition: inv_imu_regmap_le.h:960
fifo_sram_sleep_t
Definition: inv_imu_regmap_le.h:964
fifo_sram_sleep_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:966
fifo_sram_sleep_t::fifo_gsleep_shared_sram
uint8_t fifo_gsleep_shared_sram
Definition: inv_imu_regmap_le.h:965
ipreg_sys1_reg_166_t
Definition: inv_imu_regmap_le.h:978
ipreg_sys1_reg_166_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:979
ipreg_sys1_reg_166_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:982
ipreg_sys1_reg_166_t::gyro_src_ctrl
uint8_t gyro_src_ctrl
Definition: inv_imu_regmap_le.h:981
ipreg_sys1_reg_166_t::gyro_afsr_mode
uint8_t gyro_afsr_mode
Definition: inv_imu_regmap_le.h:980
ipreg_sys1_reg_168_t
Definition: inv_imu_regmap_le.h:986
ipreg_sys1_reg_168_t::gyro_afsr_shared
uint8_t gyro_afsr_shared
Definition: inv_imu_regmap_le.h:987
ipreg_sys1_reg_168_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:989
ipreg_sys1_reg_168_t::gyro_ois_m6_byp
uint8_t gyro_ois_m6_byp
Definition: inv_imu_regmap_le.h:988
ipreg_sys1_reg_170_t
Definition: inv_imu_regmap_le.h:993
ipreg_sys1_reg_170_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:994
ipreg_sys1_reg_170_t::gyro_ois_hpfbw_sel
uint8_t gyro_ois_hpfbw_sel
Definition: inv_imu_regmap_le.h:996
ipreg_sys1_reg_170_t::gyro_lp_avg_sel
uint8_t gyro_lp_avg_sel
Definition: inv_imu_regmap_le.h:995
ipreg_sys1_reg_171_t
Definition: inv_imu_regmap_le.h:1000
ipreg_sys1_reg_171_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:1003
ipreg_sys1_reg_171_t::gyro_ois_lpf1bw_sel
uint8_t gyro_ois_lpf1bw_sel
Definition: inv_imu_regmap_le.h:1001
ipreg_sys1_reg_171_t::gyro_ois_lpf2bw_sel
uint8_t gyro_ois_lpf2bw_sel
Definition: inv_imu_regmap_le.h:1002
ipreg_sys1_reg_172_t
Definition: inv_imu_regmap_le.h:1007
ipreg_sys1_reg_172_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:1009
ipreg_sys1_reg_172_t::gyro_ois_hpf1_byp
uint8_t gyro_ois_hpf1_byp
Definition: inv_imu_regmap_le.h:1010
ipreg_sys1_reg_172_t::gyro_ui_lpfbw_sel
uint8_t gyro_ui_lpfbw_sel
Definition: inv_imu_regmap_le.h:1008
ipreg_sys1_reg_173_t
Definition: inv_imu_regmap_le.h:1014
ipreg_sys1_reg_173_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:1016
ipreg_sys1_reg_173_t::gyro_ois_hpf2_byp
uint8_t gyro_ois_hpf2_byp
Definition: inv_imu_regmap_le.h:1015
ipreg_sys2_reg_123_t
Definition: inv_imu_regmap_le.h:1028
ipreg_sys2_reg_123_t::accel_src_ctrl
uint8_t accel_src_ctrl
Definition: inv_imu_regmap_le.h:1029
ipreg_sys2_reg_123_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:1030
ipreg_sys2_reg_129_t
Definition: inv_imu_regmap_le.h:1034
ipreg_sys2_reg_129_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:1037
ipreg_sys2_reg_129_t::accel_lp_avg_sel
uint8_t accel_lp_avg_sel
Definition: inv_imu_regmap_le.h:1035
ipreg_sys2_reg_129_t::accel_ois_hpfbw_sel
uint8_t accel_ois_hpfbw_sel
Definition: inv_imu_regmap_le.h:1036
ipreg_sys2_reg_130_t
Definition: inv_imu_regmap_le.h:1041
ipreg_sys2_reg_130_t::accel_ois_lpf2bw_sel
uint8_t accel_ois_lpf2bw_sel
Definition: inv_imu_regmap_le.h:1043
ipreg_sys2_reg_130_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:1044
ipreg_sys2_reg_130_t::accel_ois_lpf1bw_sel
uint8_t accel_ois_lpf1bw_sel
Definition: inv_imu_regmap_le.h:1042
ipreg_sys2_reg_131_t
Definition: inv_imu_regmap_le.h:1048
ipreg_sys2_reg_131_t::accel_ui_lpfbw_sel
uint8_t accel_ui_lpfbw_sel
Definition: inv_imu_regmap_le.h:1049
ipreg_sys2_reg_131_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:1050
ipreg_sys2_reg_132_t
Definition: inv_imu_regmap_le.h:1054
ipreg_sys2_reg_132_t::accel_ois_hpf2_byp
uint8_t accel_ois_hpf2_byp
Definition: inv_imu_regmap_le.h:1056
ipreg_sys2_reg_132_t::accel_ois_m6_byp
uint8_t accel_ois_m6_byp
Definition: inv_imu_regmap_le.h:1057
ipreg_sys2_reg_132_t::accel_ois_hpf1_byp
uint8_t accel_ois_hpf1_byp
Definition: inv_imu_regmap_le.h:1055
ipreg_sys2_reg_132_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:1058
ipreg_bar_reg_57_t
Definition: inv_imu_regmap_le.h:1066
ipreg_bar_reg_57_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:1070
ipreg_bar_reg_57_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:1067
ipreg_bar_reg_57_t::io_opt0
uint8_t io_opt0
Definition: inv_imu_regmap_le.h:1069
ipreg_bar_reg_57_t::io_opt1
uint8_t io_opt1
Definition: inv_imu_regmap_le.h:1068
ipreg_bar_reg_58_t
Definition: inv_imu_regmap_le.h:1074
ipreg_bar_reg_58_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:1079
ipreg_bar_reg_58_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:1076
ipreg_bar_reg_58_t::pads_ap_sclk_pud_trim_d2a
uint8_t pads_ap_sclk_pud_trim_d2a
Definition: inv_imu_regmap_le.h:1081
ipreg_bar_reg_58_t::pads_ap_cs_pe_trim_d2a
uint8_t pads_ap_cs_pe_trim_d2a
Definition: inv_imu_regmap_le.h:1077
ipreg_bar_reg_58_t::pads_ap_sclk_pe_trim_d2a
uint8_t pads_ap_sclk_pe_trim_d2a
Definition: inv_imu_regmap_le.h:1080
ipreg_bar_reg_58_t::io_opt2
uint8_t io_opt2
Definition: inv_imu_regmap_le.h:1075
ipreg_bar_reg_58_t::pads_ap_cs_pud_trim_d2a
uint8_t pads_ap_cs_pud_trim_d2a
Definition: inv_imu_regmap_le.h:1078
ipreg_bar_reg_59_t
Definition: inv_imu_regmap_le.h:1085
ipreg_bar_reg_59_t::resv_3
uint8_t resv_3
Definition: inv_imu_regmap_le.h:1092
ipreg_bar_reg_59_t::pads_ap_sdi_pe_trim_d2a
uint8_t pads_ap_sdi_pe_trim_d2a
Definition: inv_imu_regmap_le.h:1087
ipreg_bar_reg_59_t::pads_pin7_pe_trim_d2a
uint8_t pads_pin7_pe_trim_d2a
Definition: inv_imu_regmap_le.h:1093
ipreg_bar_reg_59_t::pads_ap_sdo_pe_trim_d2a
uint8_t pads_ap_sdo_pe_trim_d2a
Definition: inv_imu_regmap_le.h:1090
ipreg_bar_reg_59_t::pads_ap_sdo_pud_trim_d2a
uint8_t pads_ap_sdo_pud_trim_d2a
Definition: inv_imu_regmap_le.h:1091
ipreg_bar_reg_59_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:1086
ipreg_bar_reg_59_t::pads_ap_sdi_pud_trim_d2a
uint8_t pads_ap_sdi_pud_trim_d2a
Definition: inv_imu_regmap_le.h:1088
ipreg_bar_reg_59_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:1089
ipreg_bar_reg_60_t
Definition: inv_imu_regmap_le.h:1097
ipreg_bar_reg_60_t::pads_aux1_sclk_pud_trim_d2a
uint8_t pads_aux1_sclk_pud_trim_d2a
Definition: inv_imu_regmap_le.h:1104
ipreg_bar_reg_60_t::pads_aux1_cs_pud_trim_d2a
uint8_t pads_aux1_cs_pud_trim_d2a
Definition: inv_imu_regmap_le.h:1101
ipreg_bar_reg_60_t::pads_aux_sclk_tp2_from_pad_disable_trim_d2a
uint8_t pads_aux_sclk_tp2_from_pad_disable_trim_d2a
Definition: inv_imu_regmap_le.h:1102
ipreg_bar_reg_60_t::pads_aux1_sclk_pe_trim_d2a
uint8_t pads_aux1_sclk_pe_trim_d2a
Definition: inv_imu_regmap_le.h:1103
ipreg_bar_reg_60_t::pads_aux1_cs_pe_trim_d2a
uint8_t pads_aux1_cs_pe_trim_d2a
Definition: inv_imu_regmap_le.h:1100
ipreg_bar_reg_60_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:1105
ipreg_bar_reg_60_t::pads_pin7_cs_pud_trim_d2a
uint8_t pads_pin7_cs_pud_trim_d2a
Definition: inv_imu_regmap_le.h:1098
ipreg_bar_reg_60_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:1099
ipreg_bar_reg_61_t
Definition: inv_imu_regmap_le.h:1109
ipreg_bar_reg_61_t::pads_aux1_sdo_pe_trim_d2a
uint8_t pads_aux1_sdo_pe_trim_d2a
Definition: inv_imu_regmap_le.h:1113
ipreg_bar_reg_61_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:1112
ipreg_bar_reg_61_t::pads_int1_pud_trim_d2a
uint8_t pads_int1_pud_trim_d2a
Definition: inv_imu_regmap_le.h:1117
ipreg_bar_reg_61_t::pads_aux1_sdi_pud_trim_d2a
uint8_t pads_aux1_sdi_pud_trim_d2a
Definition: inv_imu_regmap_le.h:1111
ipreg_bar_reg_61_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:1115
ipreg_bar_reg_61_t::pads_int1_pe_trim_d2a
uint8_t pads_int1_pe_trim_d2a
Definition: inv_imu_regmap_le.h:1116
ipreg_bar_reg_61_t::pads_aux1_sdi_pe_trim_d2a
uint8_t pads_aux1_sdi_pe_trim_d2a
Definition: inv_imu_regmap_le.h:1110
ipreg_bar_reg_61_t::pads_aux1_sdo_pud_trim_d2a
uint8_t pads_aux1_sdo_pud_trim_d2a
Definition: inv_imu_regmap_le.h:1114
ipreg_bar_reg_62_t
Definition: inv_imu_regmap_le.h:1121
ipreg_bar_reg_62_t::resv_1
uint8_t resv_1
Definition: inv_imu_regmap_le.h:1122
ipreg_bar_reg_62_t::pads_int2_pud_trim_d2a
uint8_t pads_int2_pud_trim_d2a
Definition: inv_imu_regmap_le.h:1124
ipreg_bar_reg_62_t::pads_int2_pe_trim_d2a
uint8_t pads_int2_pe_trim_d2a
Definition: inv_imu_regmap_le.h:1123
ipreg_bar_reg_62_t::resv_2
uint8_t resv_2
Definition: inv_imu_regmap_le.h:1125