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inv_imu_defs.h
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1 /*
2 *
3 * Copyright (c) [2020] by InvenSense, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 */
17
18 #ifndef _INV_IMU_DEFS_H_
19 #define _INV_IMU_DEFS_H_
20
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24
32 #include <stdint.h>
33
34 /* Include device definition */
35 #include "imu/inv_imu.h"
36
37 /* Include regmap (le = little endian, be = big endian) */
38 #include "imu/inv_imu_regmap_le.h"
39 /* #include "imu/inv_imu_regmap_be.h" */
40
41 /* Error/Success codes */
42 #define INV_IMU_OK 0
43 #define INV_IMU_ERROR -1
44 #define INV_IMU_ERROR_TRANSPORT -3
45 #define INV_IMU_ERROR_TIMEOUT -4
46 #define INV_IMU_ERROR_BAD_ARG -11
47 #define INV_IMU_ERROR_EDMP_ODR -126
48 #define INV_IMU_ERROR_EDMP_BUF_EMPTY -127
50 /* Enable and Disable state */
51 #define INV_IMU_DISABLE (0U)
52 #define INV_IMU_ENABLE (1U)
53
54 /* Startup times */
55 #define ACC_STARTUP_TIME_US 10000
56 #define GYR_STARTUP_TIME_US 70000
57
58 /* FIFO: Data size */
59 #define ACCEL_DATA_SIZE 6
60 #define GYRO_DATA_SIZE 6
61 #define TEMP_DATA_SIZE 2
62 #define FIFO_HEADER_SIZE 1
63 #define FIFO_TEMP_DATA_SIZE 1
64 #define FIFO_TS_FSYNC_SIZE 2
65 #define FIFO_TEMP_HIGH_RES_SIZE 1
66 #define FIFO_ACCEL_GYRO_HIGH_RES_SIZE 3
67 #define FIFO_ES0_6B_DATA_SIZE 6
68 #define FIFO_ES0_9B_DATA_SIZE 9
69 #define FIFO_ES1_DATA_SIZE 6
70
71 /* FIFO: Special values */
72 #define INVALID_VALUE_FIFO ((int16_t)0x8000)
73 #define INVALID_VALUE_FIFO_1B ((int8_t)0x80)
74 #define OUT_OF_BOUND_TEMP_NEG_FIFO_1B ((int8_t)0x81)
75 #define OUT_OF_BOUND_TEMP_POS_FIFO_1B ((int8_t)0x7F)
76
77 /* FIFO: Compression ratio */
78 #define FIFO_COMP_X2_COMPRESSION 0
79 #define FIFO_COMP_X3_COMPRESSION 1
80 #define FIFO_COMP_X4_COMPRESSION 2
81
82 /* FIFO: Total number of sample in the frame */
83 #define FIFO_COMP_1_SAMPLE_IN_FRAME 0
84 #define FIFO_COMP_2_SAMPLES_IN_FRAME 1
85 #define FIFO_COMP_3_SAMPLES_IN_FRAME 2
86 #define FIFO_COMP_4_SAMPLES_IN_FRAME 3
87
89 #define INT5_TO_INT8(in) (((in) < 16) ? ((int8_t)(in)) : ((int8_t)(in)-32))
90
92 #define INT4_TO_INT8(in) (((in) < 8) ? ((int8_t)(in)) : ((int8_t)(in)-16))
93
95 typedef struct {
96 int16_t accel_data[3];
97 int16_t gyro_data[3];
98 int16_t temp_data;
99 } inv_imu_sensor_data_t;
100
102 typedef enum {
103 INV_IMU_INT1,
104 INV_IMU_INT2,
105 } inv_imu_int_num_t;
106
108 typedef union {
109 uint8_t Byte;
110 struct {
111 uint8_t gyro_odr_different : 1;
112 uint8_t accel_odr_different : 1;
113 uint8_t fsync_bit : 1;
114 uint8_t timestamp_bit : 1;
115 uint8_t twentybits_bit : 1;
116 uint8_t gyro_bit : 1;
117 uint8_t accel_bit : 1;
118 uint8_t ext_header : 1;
119 } bits;
120 } fifo_header_t;
121
123 typedef union {
124 uint8_t Byte;
125 struct {
126 uint8_t tot_sample : 2;
127 uint8_t comp_ratio : 2;
128 uint8_t comp_frame : 1;
129 uint8_t gyro_bit : 1;
130 uint8_t accel_bit : 1;
131 uint8_t ext_header : 1;
132 } bits;
133 } fifo_comp_header_t;
134
136 typedef union {
137 uint8_t Byte;
138 struct {
139 uint8_t es0_en : 1;
140 uint8_t es1_en : 1;
141 uint8_t es0_vld : 1;
142 uint8_t es1_vld : 1;
143 uint8_t es0_6b_9b : 1;
144 uint8_t unused1 : 1;
145 uint8_t unused2 : 1;
146 uint8_t unused3 : 1;
147 } bits;
148 } fifo_header2_t;
149
151 typedef union {
152 uint8_t Byte;
153 struct {
154 uint8_t valid_samples_a : 4;
155 uint8_t valid_samples_g : 4;
156 } bits;
157 } fifo_comp_decode_t;
158
160 typedef struct {
161 fifo_config0_t fifo_config0;
162 uint8_t fifo_config1_0;
163 uint8_t fifo_config1_1;
164 fifo_config2_t fifo_config2;
165 fifo_config3_t fifo_config3;
166 fifo_config4_t fifo_config4;
167 } fifo_configx_t;
168
172 typedef struct {
173 int1_config0_t int1_config0;
174 int1_config1_t int1_config1;
175 } intx_configx_t;
176
180 typedef struct {
181 int1_status0_t int1_status0;
182 int1_status1_t int1_status1;
183 } intx_statusx_t;
184
185 /*
186 * Registers description
187 */
188
189 /* ---------------------------------------------------------------------------
190 * Bank DREG_BANK1
191 * ---------------------------------------------------------------------------*/
192
193 /*
194 * PWR_MGMT0
195 */
196
197 /* gyro_mode */
198 typedef enum {
199 PWR_MGMT0_GYRO_MODE_LN = 0x03,
200 PWR_MGMT0_GYRO_MODE_LP = 0x02,
201 PWR_MGMT0_GYRO_MODE_STANDBY = 0x01,
202 PWR_MGMT0_GYRO_MODE_OFF = 0x00,
203 } pwr_mgmt0_gyro_mode_t;
204
205 /* accel_mode */
206 typedef enum {
207 PWR_MGMT0_ACCEL_MODE_LN = 0x03,
208 PWR_MGMT0_ACCEL_MODE_LP = 0x02,
209 PWR_MGMT0_ACCEL_MODE_OFF = 0x00,
210 } pwr_mgmt0_accel_mode_t;
211
212 /*
213 * INTX_CONFIG2
214 * Applies to both INT1_CONFIG2 and INT2_CONFIG2 (bits are located at the
215 * same position on two different registers)
216 */
217
218 /* intX_drive */
219 typedef enum {
220 INTX_CONFIG2_INTX_DRIVE_PP = 0x00,
221 INTX_CONFIG2_INTX_DRIVE_OD = 0x01,
222 } intx_config2_intx_drive_t;
223
224 /* intX_mode */
225 typedef enum {
226 INTX_CONFIG2_INTX_MODE_PULSE = 0x00,
227 INTX_CONFIG2_INTX_MODE_LATCH = 0x01,
228 } intx_config2_intx_mode_t;
229
230 /* intX_polarity */
231 typedef enum {
232 INTX_CONFIG2_INTX_POLARITY_LOW = 0x00,
233 INTX_CONFIG2_INTX_POLARITY_HIGH = 0x01,
234 } intx_config2_intx_polarity_t;
235
237 typedef struct {
238 intx_config2_intx_polarity_t int_polarity;
239 intx_config2_intx_mode_t int_mode;
240 intx_config2_intx_drive_t int_drive;
241 } inv_imu_int_pin_config_t;
242
243 /*
244 * ACCEL_CONFIG0
245 */
246
247 /* accel_ui_fs_sel */
248 typedef enum {
249 ACCEL_CONFIG0_ACCEL_UI_FS_SEL_2_G = 0x4,
250 ACCEL_CONFIG0_ACCEL_UI_FS_SEL_4_G = 0x3,
251 ACCEL_CONFIG0_ACCEL_UI_FS_SEL_8_G = 0x2,
252 ACCEL_CONFIG0_ACCEL_UI_FS_SEL_16_G = 0x1,
253 #if INV_IMU_HIGH_FSR_SUPPORTED
254 ACCEL_CONFIG0_ACCEL_UI_FS_SEL_32_G = 0x0,
255 #endif
256 } accel_config0_accel_ui_fs_sel_t;
257
258 /* accel_odr */
259 typedef enum {
260 ACCEL_CONFIG0_ACCEL_ODR_1_5625_HZ = 0xF,
261 ACCEL_CONFIG0_ACCEL_ODR_3_125_HZ = 0xE,
262 ACCEL_CONFIG0_ACCEL_ODR_6_25_HZ = 0xD,
263 ACCEL_CONFIG0_ACCEL_ODR_12_5_HZ = 0xC,
264 ACCEL_CONFIG0_ACCEL_ODR_25_HZ = 0xB,
265 ACCEL_CONFIG0_ACCEL_ODR_50_HZ = 0xA,
266 ACCEL_CONFIG0_ACCEL_ODR_100_HZ = 0x9,
267 ACCEL_CONFIG0_ACCEL_ODR_200_HZ = 0x8,
268 ACCEL_CONFIG0_ACCEL_ODR_400_HZ = 0x7,
269 ACCEL_CONFIG0_ACCEL_ODR_800_HZ = 0x6,
270 ACCEL_CONFIG0_ACCEL_ODR_1600_HZ = 0x5,
271 ACCEL_CONFIG0_ACCEL_ODR_3200_HZ = 0x4,
272 ACCEL_CONFIG0_ACCEL_ODR_6400_HZ = 0x3,
273 } accel_config0_accel_odr_t;
274
275 /*
276 * GYRO_CONFIG0
277 */
278
279 /* gyro_ui_fs_sel */
280 typedef enum {
281 GYRO_CONFIG0_GYRO_UI_FS_SEL_15_625_DPS = 8,
282 GYRO_CONFIG0_GYRO_UI_FS_SEL_31_25_DPS = 7,
283 GYRO_CONFIG0_GYRO_UI_FS_SEL_62_5_DPS = 6,
284 GYRO_CONFIG0_GYRO_UI_FS_SEL_125_DPS = 5,
285 GYRO_CONFIG0_GYRO_UI_FS_SEL_250_DPS = 4,
286 GYRO_CONFIG0_GYRO_UI_FS_SEL_500_DPS = 3,
287 GYRO_CONFIG0_GYRO_UI_FS_SEL_1000_DPS = 2,
288 GYRO_CONFIG0_GYRO_UI_FS_SEL_2000_DPS = 1,
289 #if INV_IMU_HIGH_FSR_SUPPORTED
290 GYRO_CONFIG0_GYRO_UI_FS_SEL_4000_DPS = 0,
291 #endif
292 } gyro_config0_gyro_ui_fs_sel_t;
293
294 /* gyro_odr */
295 typedef enum {
296 GYRO_CONFIG0_GYRO_ODR_1_5625_HZ = 0xF,
297 GYRO_CONFIG0_GYRO_ODR_3_125_HZ = 0xE,
298 GYRO_CONFIG0_GYRO_ODR_6_25_HZ = 0xD,
299 GYRO_CONFIG0_GYRO_ODR_12_5_HZ = 0xC,
300 GYRO_CONFIG0_GYRO_ODR_25_HZ = 0xB,
301 GYRO_CONFIG0_GYRO_ODR_50_HZ = 0xA,
302 GYRO_CONFIG0_GYRO_ODR_100_HZ = 0x9,
303 GYRO_CONFIG0_GYRO_ODR_200_HZ = 0x8,
304 GYRO_CONFIG0_GYRO_ODR_400_HZ = 0x7,
305 GYRO_CONFIG0_GYRO_ODR_800_HZ = 0x6,
306 GYRO_CONFIG0_GYRO_ODR_1600_HZ = 0x5,
307 GYRO_CONFIG0_GYRO_ODR_3200_HZ = 0x4,
308 GYRO_CONFIG0_GYRO_ODR_6400_HZ = 0x3,
309 } gyro_config0_gyro_odr_t;
310
311 /*
312 * FIFO_CONFIG0
313 */
314
315 /* fifo_mode */
316 typedef enum {
317 FIFO_CONFIG0_FIFO_MODE_SNAPSHOT = 0x02,
318 FIFO_CONFIG0_FIFO_MODE_STREAM = 0x01,
319 FIFO_CONFIG0_FIFO_MODE_BYPASS = 0x00,
320 } fifo_config0_fifo_mode_t;
321
322 /* fifo_depth */
323 typedef enum {
324 FIFO_CONFIG0_FIFO_DEPTH_MAX = 0x1E, /* Errata AN-000364 */
325 #if defined(ICM45632M)
326 FIFO_CONFIG0_FIFO_DEPTH_APEX = 0x0B,
327 #else
328 FIFO_CONFIG0_FIFO_DEPTH_APEX = 0x07,
329 #endif
330 FIFO_CONFIG0_FIFO_DEPTH_GAF = 0x04,
331 } fifo_config0_fifo_depth_t;
332
333 /*
334 * FIFO_CONFIG2
335 */
336
337 /* fifo_wr_wm_gt_th */
338 typedef enum {
339 FIFO_CONFIG2_FIFO_WR_WM_EQ_OR_GT_TH = 0x1,
340 FIFO_CONFIG2_FIFO_WR_WM_EQ_TH = 0x0,
341 } fifo_config2_fifo_wr_wm_gt_th_t;
342
343 /*
344 * FIFO_CONFIG4
345 */
346
347 /* fifo_comp_nc_flow_cfg */
348 typedef enum {
349 FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_128_FR = 0x5,
350 FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_64_FR = 0x4,
351 FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_32_FR = 0x3,
352 FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_16_FR = 0x2,
353 FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_8_FR = 0x1,
354 FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_DIS = 0x0,
355 } fifo_config4_fifo_comp_nc_flow_cfg_t;
356
357 /* fifo_es0_6b_9b */
358 typedef enum {
359 FIFO_CONFIG4_FIFO_ES0_9B = 0x1,
360 FIFO_CONFIG4_FIFO_ES0_6B = 0x0,
361 } fifo_config4_fifo_es0_6b_9b_t;
362
363 /*
364 * TMST_WOM_CONFIG
365 */
366
367 /* tmst_resol */
368 typedef enum {
369 TMST_WOM_CONFIG_TMST_RESOL_16_US = 0x01,
370 TMST_WOM_CONFIG_TMST_RESOL_1_US = 0x00,
371 } tmst_wom_config_tmst_resol_t;
372
373 /* wom_mode */
374 typedef enum {
375 TMST_WOM_CONFIG_WOM_MODE_CMP_PREV = 0x01,
376 TMST_WOM_CONFIG_WOM_MODE_CMP_INIT = 0x00,
377 } tmst_wom_config_wom_mode_t;
378
379 /* wom_int_mode*/
380 typedef enum {
381 TMST_WOM_CONFIG_WOM_INT_MODE_ANDED = 0x01,
382 TMST_WOM_CONFIG_WOM_INT_MODE_ORED = 0x00,
383 } tmst_wom_config_wom_int_mode_t;
384
385 /* wom_int_dur */
386 typedef enum {
387 TMST_WOM_CONFIG_WOM_INT_DUR_1_SMPL = 0x00,
388 TMST_WOM_CONFIG_WOM_INT_DUR_2_SMPL = 0x01,
389 TMST_WOM_CONFIG_WOM_INT_DUR_3_SMPL = 0x02,
390 TMST_WOM_CONFIG_WOM_INT_DUR_4_SMPL = 0x03,
391 } tmst_wom_config_wom_int_dur_t;
392
393 /*
394 * FSYNC_CONFIG0
395 */
396
397 /* ap_fsync_sel */
398 typedef enum {
399 FSYNC_CONFIG0_AP_FSYNC_NO = 0x0,
400 FSYNC_CONFIG0_AP_FSYNC_TEMP = 0x1,
401 FSYNC_CONFIG0_AP_FSYNC_GYRO_X = 0x2,
402 FSYNC_CONFIG0_AP_FSYNC_GYRO_Y = 0x3,
403 FSYNC_CONFIG0_AP_FSYNC_GYRO_Z = 0x4,
404 FSYNC_CONFIG0_AP_FSYNC_ACCEL_X = 0x5,
405 FSYNC_CONFIG0_AP_FSYNC_ACCEL_Y = 0x6,
406 FSYNC_CONFIG0_AP_FSYNC_ACCEL_Z = 0x7,
407 } fsync_config0_ap_fsync_sel_t;
408
409 /*
410 * DMP_EXT_SEN_ODR_CFG
411 */
412
413 /* ext_odr */
414 typedef enum {
415 DMP_EXT_SEN_ODR_CFG_EXT_ODR_3_25_HZ = 0x00,
416 DMP_EXT_SEN_ODR_CFG_EXT_ODR_6_25_HZ = 0x01,
417 DMP_EXT_SEN_ODR_CFG_EXT_ODR_12_5_HZ = 0x02,
418 DMP_EXT_SEN_ODR_CFG_EXT_ODR_25_HZ = 0x03,
419 DMP_EXT_SEN_ODR_CFG_EXT_ODR_50_HZ = 0x04,
420 DMP_EXT_SEN_ODR_CFG_EXT_ODR_100_HZ = 0x05,
421 DMP_EXT_SEN_ODR_CFG_EXT_ODR_200_HZ = 0x06,
422 DMP_EXT_SEN_ODR_CFG_EXT_ODR_400_HZ = 0x07,
423 } dmp_ext_sen_odr_cfg_ext_odr_t;
424
425 /* apex_odr */
426 typedef enum {
427 DMP_EXT_SEN_ODR_CFG_APEX_ODR_25_HZ = 0x00,
428 DMP_EXT_SEN_ODR_CFG_APEX_ODR_50_HZ = 0x01,
429 DMP_EXT_SEN_ODR_CFG_APEX_ODR_100_HZ = 0x02,
430 DMP_EXT_SEN_ODR_CFG_APEX_ODR_200_HZ = 0x03,
431 DMP_EXT_SEN_ODR_CFG_APEX_ODR_400_HZ = 0x04,
432 DMP_EXT_SEN_ODR_CFG_APEX_ODR_800_HZ = 0x05,
433 } dmp_ext_sen_odr_cfg_apex_odr_t;
434
435 /*
436 * ODR_DECIMATE_CONFIG
437 */
438
439 /* gyro_fifo_odr_dec */
440 typedef enum {
441 ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_1 = 0x0,
442 ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_2 = 0x1,
443 ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_4 = 0x2,
444 ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_8 = 0x3,
445 ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_16 = 0x4,
446 ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_32 = 0x5,
447 ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_64 = 0x6,
448 ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_128 = 0x7,
449 ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_256 = 0x8,
450 ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_512 = 0x9,
451 ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_1024 = 0xA,
452 ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_2048 = 0xB,
453 ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_4096 = 0xC,
454 } odr_decimate_config_gyro_fifo_odr_dec_t;
455
456 /* accel_fifo_odr_dec */
457 typedef enum {
458 ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_1 = 0x0,
459 ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_2 = 0x1,
460 ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_4 = 0x2,
461 ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_8 = 0x3,
462 ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_16 = 0x4,
463 ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_32 = 0x5,
464 ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_64 = 0x6,
465 ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_128 = 0x7,
466 ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_256 = 0x8,
467 ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_512 = 0x9,
468 ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_1024 = 0xA,
469 ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_2048 = 0xB,
470 ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_4096 = 0xC,
471 } odr_decimate_config_accel_fifo_odr_dec_t;
472
473 /*
474 * INTF_CONFIG1_OVRD
475 */
476
477 /* ap_spi_34_mode_ovrd_val */
478 typedef enum {
479 INTF_CONFIG1_OVRD_AP_SPI_34_MODE_OVRD_VAL_3_WIRE = 0x0,
480 INTF_CONFIG1_OVRD_AP_SPI_34_MODE_OVRD_VAL_4_WIRE = 0x1,
481 } intf_config1_ovrd_ap_spi_34_mode_ovrd_val_t;
482
483 /* ap_spi_mode_ovrd_val */
484 typedef enum {
485 INTF_CONFIG1_OVRD_AP_SPI_MODE_OVRD_VAL_0_OR_3 = 0x0,
486 INTF_CONFIG1_OVRD_AP_SPI_MODE_OVRD_VAL_1_OR_2 = 0x1,
487 } intf_config1_ovrd_ap_spi_mode_ovrd_val_t;
488
489 /*
490 * DRIVE_CONFIG0
491 */
492
493 /* pads_i2c_slew */
494 typedef enum {
495 DRIVE_CONFIG0_PADS_I2C_SLEW_TYP_20NS = 0x0,
496 DRIVE_CONFIG0_PADS_I2C_SLEW_TYP_7NS = 0x2,
497 } drive_config0_pads_i2c_slew_t;
498
499 /* pads_spi_slew */
500 typedef enum {
501 DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_38NS = 0x0,
502 DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_14NS = 0x1,
503 DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_10NS = 0x2,
504 DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_7NS = 0x3,
505 DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_5NS = 0x4,
506 DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_4NS = 0x5,
507 DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_0_5NS = 0x6,
508 } drive_config0_pads_spi_slew_t;
509
510 /*
511 * IOC_PAD_SCENARIO_OVRD
512 */
513
514 /* pads_int2_cfg_ovrd_val */
515 typedef enum {
516 IOC_PAD_SCENARIO_OVRD_INT2_CFG_OVRD_VAL_INT2 = 0,
517 #if INV_IMU_FSYNC_SUPPORTED
518 IOC_PAD_SCENARIO_OVRD_INT2_CFG_OVRD_VAL_FSYNC = 1,
519 #endif
520 #if INV_IMU_CLKIN_SUPPORTED
521 IOC_PAD_SCENARIO_OVRD_INT2_CFG_OVRD_VAL_CLKIN = 2,
522 #endif
523 IOC_PAD_SCENARIO_OVRD_INT2_CFG_OVRD_VAL_DRDY_INTR = 3,
524 } ioc_pad_scenario_ovrd_pads_int2_cfg_ovrd_val_t;
525
526 /*
527 * REG_MISC1
528 */
529
530 /* osc_id_ovrd */
531 typedef enum {
532 REG_MISC1_OSC_ID_OVRD_OFF = 0x0,
533 REG_MISC1_OSC_ID_OVRD_EDOSC = 0x1,
534 REG_MISC1_OSC_ID_OVRD_RCOSC = 0x2,
535 REG_MISC1_OSC_ID_OVRD_PLL = 0x4,
536 REG_MISC1_OSC_ID_OVRD_EXT_CLK = 0x8,
537 } reg_misc1_osc_id_ovrd_t;
538
539 /*
540 * FS_SEL_AUX{1|2}
541 */
542
543 /* aux_gyro_fs_sel */
544 typedef enum {
545 FS_SEL_AUX_GYRO_FS_SEL_15_625_DPS = 8,
546 FS_SEL_AUX_GYRO_FS_SEL_31_25_DPS = 7,
547 FS_SEL_AUX_GYRO_FS_SEL_62_5_DPS = 6,
548 FS_SEL_AUX_GYRO_FS_SEL_125_DPS = 5,
549 FS_SEL_AUX_GYRO_FS_SEL_250_DPS = 4,
550 FS_SEL_AUX_GYRO_FS_SEL_500_DPS = 3,
551 FS_SEL_AUX_GYRO_FS_SEL_1000_DPS = 2,
552 FS_SEL_AUX_GYRO_FS_SEL_2000_DPS = 1,
553 #if INV_IMU_HIGH_FSR_SUPPORTED
554 FS_SEL_AUX_GYRO_FS_SEL_4000_DPS = 0,
555 #endif
556 } fs_sel_aux_gyro_fs_sel_t;
557
558 /* aux_accel_fs_sel */
559 typedef enum {
560 FS_SEL_AUX_ACCEL_FS_SEL_2_G = 0x4,
561 FS_SEL_AUX_ACCEL_FS_SEL_4_G = 0x3,
562 FS_SEL_AUX_ACCEL_FS_SEL_8_G = 0x2,
563 FS_SEL_AUX_ACCEL_FS_SEL_16_G = 0x1,
564 #if INV_IMU_HIGH_FSR_SUPPORTED
565 FS_SEL_AUX_ACCEL_FS_SEL_32_G = 0x0,
566 #endif
567 } fs_sel_aux_accel_fs_sel_t;
568
569 /* ---------------------------------------------------------------------------
570 * Bank IPREG_TOP1
571 * ---------------------------------------------------------------------------*/
572
573 /*
574 * SMC_CONTROL_0
575 */
576
577 /* accel_lp_clk_sel */
578 typedef enum {
579 SMC_CONTROL_0_ACCEL_LP_CLK_RCOSC = 0x01,
580 SMC_CONTROL_0_ACCEL_LP_CLK_WUOSC = 0x00,
581 } smc_control_0_accel_lp_clk_sel_t;
582
583 /*
584 * SREG_CTRL
585 */
586
587 /* sreg_data_endian_sel */
588 typedef enum {
589 SREG_CTRL_SREG_DATA_BIG_ENDIAN = 0x01,
590 SREG_CTRL_SREG_DATA_LITTLE_ENDIAN = 0x00,
591 } sreg_ctrl_sreg_data_endian_sel_t;
592
593 /*
594 * STATUS_MASK_PIN_X_Y
595 * Applies to STATUS_MASK_PIN_0_7_IPREG_TOP1, STATUS_MASK_PIN_8_15_IPREG_TOP1 and
596 * STATUS_MASK_PIN_16_23_IPREG_TOP1.
597 */
598 #define EDMP_INT_SRC_ACCEL_DRDY_MASK 0x01
599 #define EDMP_INT_SRC_GYRO_DRDY_MASK 0x02
600 #define EDMP_INT_SRC_EXT_INT_DRDY_MASK 0x04
601 #define EDMP_INT_SRC_EXT_ODR_DRDY_MASK 0x08
602 #define EDMP_INT_SRC_WOM_DRDY_MASK 0x10
603 #define EDMP_INT_SRC_ON_DEMAND_MASK 0x20
604
605 /* ---------------------------------------------------------------------------
606 * Bank IPREG_SYS1
607 * ---------------------------------------------------------------------------*/
608
609 /*
610 * IPREG_SYS1_REG_166
611 */
612
613 /* gyro_src_ctrl */
614 typedef enum {
615 IPREG_SYS1_REG_166_GYRO_SRC_CTRL_INTERPOLATOR_ON_FIR_ON = 0x2,
616 IPREG_SYS1_REG_166_GYRO_SRC_CTRL_INTERPOLATOR_OFF_FIR_ON = 0x1,
617 IPREG_SYS1_REG_166_GYRO_SRC_CTRL_INTERPOLATOR_OFF_FIR_OFF = 0x0,
618 } ipreg_sys1_reg_166_gyro_src_ctrl_sel_t;
619
620 /*
621 * IPREG_SYS1_REG_170
622 */
623
624 /* gyro_lp_avg_sel */
625 typedef enum {
626 IPREG_SYS1_REG_170_GYRO_LP_AVG_64 = 0xC,
627 IPREG_SYS1_REG_170_GYRO_LP_AVG_32 = 0xB,
628 IPREG_SYS1_REG_170_GYRO_LP_AVG_20 = 0xA,
629 IPREG_SYS1_REG_170_GYRO_LP_AVG_18 = 0x9,
630 IPREG_SYS1_REG_170_GYRO_LP_AVG_16 = 0x8,
631 IPREG_SYS1_REG_170_GYRO_LP_AVG_11 = 0x7,
632 IPREG_SYS1_REG_170_GYRO_LP_AVG_10 = 0x6,
633 IPREG_SYS1_REG_170_GYRO_LP_AVG_8 = 0x5,
634 IPREG_SYS1_REG_170_GYRO_LP_AVG_7 = 0x4,
635 IPREG_SYS1_REG_170_GYRO_LP_AVG_5 = 0x3,
636 IPREG_SYS1_REG_170_GYRO_LP_AVG_4 = 0x2,
637 IPREG_SYS1_REG_170_GYRO_LP_AVG_2 = 0x1,
638 IPREG_SYS1_REG_170_GYRO_LP_AVG_1 = 0x0,
639 } ipreg_sys1_reg_170_gyro_lp_avg_sel_t;
640
641 /*
642 * IPREG_SYS1_REG_172
643 */
644
645 /* gyro_ui_lpfbw_sel */
646 typedef enum {
647 IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_128 = 0x06,
648 IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_64 = 0x05,
649 IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_32 = 0x04,
650 IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_16 = 0x03,
651 IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_8 = 0x02,
652 IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_4 = 0x01,
653 IPREG_SYS1_REG_172_GYRO_UI_LPFBW_NO_FILTER = 0x00,
654 } ipreg_sys1_reg_172_gyro_ui_lpfbw_sel_t;
655
656 /* ---------------------------------------------------------------------------
657 * Bank IPREG_SYS2
658 * ---------------------------------------------------------------------------*/
659
660 /*
661 * IPREG_SYS2_REG_123
662 */
663
664 /* accel_src_ctrl */
665 typedef enum {
666 IPREG_SYS2_REG_123_ACCEL_SRC_CTRL_INTERPOLATOR_ON_FIR_ON = 0x2,
667 IPREG_SYS2_REG_123_ACCEL_SRC_CTRL_INTERPOLATOR_OFF_FIR_ON = 0x1,
668 IPREG_SYS2_REG_123_ACCEL_SRC_CTRL_INTERPOLATOR_OFF_FIR_OFF = 0x0,
669 } ipreg_sys2_reg_123_accel_src_ctrl_sel_t;
670
671 /*
672 * IPREG_SYS2_REG_129
673 */
674
675 /* accel_lp_avg_sel */
676 typedef enum {
677 IPREG_SYS2_REG_129_ACCEL_LP_AVG_64 = 0xC,
678 IPREG_SYS2_REG_129_ACCEL_LP_AVG_32 = 0xB,
679 IPREG_SYS2_REG_129_ACCEL_LP_AVG_20 = 0xA,
680 IPREG_SYS2_REG_129_ACCEL_LP_AVG_18 = 0x9,
681 IPREG_SYS2_REG_129_ACCEL_LP_AVG_16 = 0x8,
682 IPREG_SYS2_REG_129_ACCEL_LP_AVG_11 = 0x7,
683 IPREG_SYS2_REG_129_ACCEL_LP_AVG_10 = 0x6,
684 IPREG_SYS2_REG_129_ACCEL_LP_AVG_8 = 0x5,
685 IPREG_SYS2_REG_129_ACCEL_LP_AVG_7 = 0x4,
686 IPREG_SYS2_REG_129_ACCEL_LP_AVG_5 = 0x3,
687 IPREG_SYS2_REG_129_ACCEL_LP_AVG_4 = 0x2,
688 IPREG_SYS2_REG_129_ACCEL_LP_AVG_2 = 0x1,
689 IPREG_SYS2_REG_129_ACCEL_LP_AVG_1 = 0x0,
690 } ipreg_sys2_reg_129_accel_lp_avg_sel_t;
691
692 /*
693 * IPREG_SYS2_REG_131
694 */
695
696 /* accel_ui_lpfbw_sel */
697 typedef enum {
698 IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_128 = 0x06,
699 IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_64 = 0x05,
700 IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_32 = 0x04,
701 IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_16 = 0x03,
702 IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_8 = 0x02,
703 IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_4 = 0x01,
704 IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_NO_FILTER = 0x00,
705 } ipreg_sys2_reg_131_accel_ui_lpfbw_t;
706
707 /* ---------------------------------------------------------------------------
708 * Bank IMEM_SRAM
709 * ---------------------------------------------------------------------------*/
710
711 /*
712 * EDMP_TAP_TMAX
713 */
714
715 /* equivalent to 0.5 seconds in sample count at 400Hz */
716 #define TAP_TMAX_400HZ 198
717 /* equivalent to 0.5 seconds in sample count at 800Hz */
718 #define TAP_TMAX_800HZ 396
719
720 /*
721 * EDMP_TAP_TMIN
722 */
723
724 /* equivalent to 0.165 seconds in sample count at 400Hz */
725 #define TAP_TMIN_400HZ 66
726 /* equivalent to 0.165 seconds in sample count at 800Hz */
727 #define TAP_TMIN_800HZ 132
728
729 /*
730 * EDMP_TAP_SMUDGE_REJECT_THR
731 */
732
733 /* equivalent to 0.085 seconds in sample count at 400Hz */
734 #define TAP_SMUDGE_REJECT_THR_400HZ 34
735 /* equivalent to 0.085 seconds in sample count at 800Hz */
736 #define TAP_SMUDGE_REJECT_THR_800HZ 68
737
738 /*
739 * EDMP_STC_RESULTS
740 */
741
742 #define STC_RESULTS_ACCEL_X_MASK 0x0001
743 #define STC_RESULTS_ACCEL_Y_MASK 0x0002
744 #define STC_RESULTS_ACCEL_Z_MASK 0x0004
745 #define STC_RESULTS_GYRO_X_MASK 0x0008
746 #define STC_RESULTS_GYRO_Y_MASK 0x0010
747 #define STC_RESULTS_GYRO_Z_MASK 0x0020
748 #define STC_RESULTS_ST_STATUS_MASK 0x00C0
749 #define STC_RESULTS_ACCEL_SC_MASK 0x0300
750 #define STC_RESULTS_GYRO_SC_MASK 0x0C00
751
752 /*
753 * EDMP_STC_CONFIGPARAMS
754 */
755
756 #define SELFTESTCAL_INIT_EN_MASK 0x0001
757 #define SELFTESTCAL_INIT_EN 0x0001
758 #define SELFTESTCAL_INIT_DIS 0x0000
759 #define SELFTEST_ACCEL_EN_MASK 0x0002
760 #define SELFTEST_ACCEL_EN 0x0002
761 #define SELFTEST_ACCEL_DIS 0x0000
762 #define SELFTEST_GYRO_EN_MASK 0x0004
763 #define SELFTEST_GYRO_EN 0x0004
764 #define SELFTEST_GYRO_DIS 0x0000
765 #define SELFTEST_AVERAGE_TIME_MASK 0x0380
766 #define SELFTEST_ACCEL_THRESH_MASK 0x1C00
767 #define SELFTEST_GYRO_THRESH_MASK 0xE000
768
769 typedef enum {
770 SELFTEST_AVG_TIME_10_MS = 0x0000,
771 SELFTEST_AVG_TIME_20_MS = 0x0080,
772 SELFTEST_AVG_TIME_40_MS = 0x0100,
773 SELFTEST_AVG_TIME_80_MS = 0x0180,
774 SELFTEST_AVG_TIME_160_MS = 0x0200,
775 SELFTEST_AVG_TIME_320_MS = 0x0280
776 } selftest_average_time_t;
777
778 typedef enum {
779 SELFTEST_ACCEL_THRESHOLD_5_PERCENT = 0x0000,
780 SELFTEST_ACCEL_THRESHOLD_10_PERCENT = 0x0400,
781 SELFTEST_ACCEL_THRESHOLD_15_PERCENT = 0x0800,
782 SELFTEST_ACCEL_THRESHOLD_20_PERCENT = 0x0c00,
783 SELFTEST_ACCEL_THRESHOLD_25_PERCENT = 0x1000,
784 SELFTEST_ACCEL_THRESHOLD_30_PERCENT = 0x1400,
785 SELFTEST_ACCEL_THRESHOLD_40_PERCENT = 0x1800,
786 SELFTEST_ACCEL_THRESHOLD_50_PERCENT = 0x1c00
787 } selftest_accel_threshold_t;
788
789 typedef enum {
790 SELFTEST_GYRO_THRESHOLD_5_PERCENT = 0x0000,
791 SELFTEST_GYRO_THRESHOLD_10_PERCENT = 0x2000,
792 SELFTEST_GYRO_THRESHOLD_15_PERCENT = 0x4000,
793 SELFTEST_GYRO_THRESHOLD_20_PERCENT = 0x6000,
794 SELFTEST_GYRO_THRESHOLD_25_PERCENT = 0x8000,
795 SELFTEST_GYRO_THRESHOLD_30_PERCENT = 0xa000,
796 SELFTEST_GYRO_THRESHOLD_40_PERCENT = 0xc000,
797 SELFTEST_GYRO_THRESHOLD_50_PERCENT = 0xe000
798 } selftest_gyro_threshold_t;
799
800 /*
801 * EDMP_STC_PATCH_EN
802 */
803
804 typedef enum {
805 SELFTEST_PATCH_EN_ACCEL_PHASE1 = 0x0001,
806 SELFTEST_PATCH_EN_ACCEL_PHASE2 = 0x0002,
807 SELFTEST_PATCH_EN_GYRO1_PHASE1 = 0x0004,
808 SELFTEST_PATCH_EN_GYRO1_PHASE2 = 0x0008
809 } stc_patch_params_t;
810
811 #ifdef __cplusplus
812 }
813 #endif
814
815 #endif /* #ifndef _INV_IMU_DEFS_H_ */
816
inv_imu_regmap_le.h
File exposing the device register map.
odr_decimate_config_gyro_fifo_odr_dec_t
odr_decimate_config_gyro_fifo_odr_dec_t
Definition: inv_imu_defs.h:440
fifo_config0_fifo_mode_t
fifo_config0_fifo_mode_t
Definition: inv_imu_defs.h:316
odr_decimate_config_accel_fifo_odr_dec_t
odr_decimate_config_accel_fifo_odr_dec_t
Definition: inv_imu_defs.h:457
smc_control_0_accel_lp_clk_sel_t
smc_control_0_accel_lp_clk_sel_t
Definition: inv_imu_defs.h:578
ipreg_sys2_reg_123_accel_src_ctrl_sel_t
ipreg_sys2_reg_123_accel_src_ctrl_sel_t
Definition: inv_imu_defs.h:665
reg_misc1_osc_id_ovrd_t
reg_misc1_osc_id_ovrd_t
Definition: inv_imu_defs.h:531
accel_config0_accel_odr_t
accel_config0_accel_odr_t
Definition: inv_imu_defs.h:259
intx_config2_intx_mode_t
intx_config2_intx_mode_t
Definition: inv_imu_defs.h:225
ipreg_sys1_reg_170_gyro_lp_avg_sel_t
ipreg_sys1_reg_170_gyro_lp_avg_sel_t
Definition: inv_imu_defs.h:625
ipreg_sys2_reg_129_accel_lp_avg_sel_t
ipreg_sys2_reg_129_accel_lp_avg_sel_t
Definition: inv_imu_defs.h:676
dmp_ext_sen_odr_cfg_ext_odr_t
dmp_ext_sen_odr_cfg_ext_odr_t
Definition: inv_imu_defs.h:414
fifo_config2_fifo_wr_wm_gt_th_t
fifo_config2_fifo_wr_wm_gt_th_t
Definition: inv_imu_defs.h:338
fs_sel_aux_gyro_fs_sel_t
fs_sel_aux_gyro_fs_sel_t
Definition: inv_imu_defs.h:544
fsync_config0_ap_fsync_sel_t
fsync_config0_ap_fsync_sel_t
Definition: inv_imu_defs.h:398
intx_config2_intx_drive_t
intx_config2_intx_drive_t
Definition: inv_imu_defs.h:219
stc_patch_params_t
stc_patch_params_t
Definition: inv_imu_defs.h:804
fifo_config4_fifo_comp_nc_flow_cfg_t
fifo_config4_fifo_comp_nc_flow_cfg_t
Definition: inv_imu_defs.h:348
pwr_mgmt0_gyro_mode_t
pwr_mgmt0_gyro_mode_t
Definition: inv_imu_defs.h:198
selftest_gyro_threshold_t
selftest_gyro_threshold_t
Definition: inv_imu_defs.h:789
drive_config0_pads_spi_slew_t
drive_config0_pads_spi_slew_t
Definition: inv_imu_defs.h:500
fifo_config4_fifo_es0_6b_9b_t
fifo_config4_fifo_es0_6b_9b_t
Definition: inv_imu_defs.h:358
fs_sel_aux_accel_fs_sel_t
fs_sel_aux_accel_fs_sel_t
Definition: inv_imu_defs.h:559
tmst_wom_config_wom_mode_t
tmst_wom_config_wom_mode_t
Definition: inv_imu_defs.h:374
pwr_mgmt0_accel_mode_t
pwr_mgmt0_accel_mode_t
Definition: inv_imu_defs.h:206
sreg_ctrl_sreg_data_endian_sel_t
sreg_ctrl_sreg_data_endian_sel_t
Definition: inv_imu_defs.h:588
dmp_ext_sen_odr_cfg_apex_odr_t
dmp_ext_sen_odr_cfg_apex_odr_t
Definition: inv_imu_defs.h:426
ioc_pad_scenario_ovrd_pads_int2_cfg_ovrd_val_t
ioc_pad_scenario_ovrd_pads_int2_cfg_ovrd_val_t
Definition: inv_imu_defs.h:515
selftest_average_time_t
selftest_average_time_t
Definition: inv_imu_defs.h:769
selftest_accel_threshold_t
selftest_accel_threshold_t
Definition: inv_imu_defs.h:778
intf_config1_ovrd_ap_spi_34_mode_ovrd_val_t
intf_config1_ovrd_ap_spi_34_mode_ovrd_val_t
Definition: inv_imu_defs.h:478
ipreg_sys1_reg_172_gyro_ui_lpfbw_sel_t
ipreg_sys1_reg_172_gyro_ui_lpfbw_sel_t
Definition: inv_imu_defs.h:646
fifo_config0_fifo_depth_t
fifo_config0_fifo_depth_t
Definition: inv_imu_defs.h:323
accel_config0_accel_ui_fs_sel_t
accel_config0_accel_ui_fs_sel_t
Definition: inv_imu_defs.h:248
tmst_wom_config_wom_int_dur_t
tmst_wom_config_wom_int_dur_t
Definition: inv_imu_defs.h:386
tmst_wom_config_wom_int_mode_t
tmst_wom_config_wom_int_mode_t
Definition: inv_imu_defs.h:380
inv_imu_int_num_t
inv_imu_int_num_t
Interrupt number.
Definition: inv_imu_defs.h:102
ipreg_sys1_reg_166_gyro_src_ctrl_sel_t
ipreg_sys1_reg_166_gyro_src_ctrl_sel_t
Definition: inv_imu_defs.h:614
ipreg_sys2_reg_131_accel_ui_lpfbw_t
ipreg_sys2_reg_131_accel_ui_lpfbw_t
Definition: inv_imu_defs.h:697
drive_config0_pads_i2c_slew_t
drive_config0_pads_i2c_slew_t
Definition: inv_imu_defs.h:494
tmst_wom_config_tmst_resol_t
tmst_wom_config_tmst_resol_t
Definition: inv_imu_defs.h:368
gyro_config0_gyro_odr_t
gyro_config0_gyro_odr_t
Definition: inv_imu_defs.h:295
intf_config1_ovrd_ap_spi_mode_ovrd_val_t
intf_config1_ovrd_ap_spi_mode_ovrd_val_t
Definition: inv_imu_defs.h:484
intx_config2_intx_polarity_t
intx_config2_intx_polarity_t
Definition: inv_imu_defs.h:231
gyro_config0_gyro_ui_fs_sel_t
gyro_config0_gyro_ui_fs_sel_t
Definition: inv_imu_defs.h:280
ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_128
@ ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_128
Definition: inv_imu_defs.h:448
ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_4
@ ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_4
Definition: inv_imu_defs.h:443
ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_16
@ ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_16
Definition: inv_imu_defs.h:445
ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_2048
@ ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_2048
Definition: inv_imu_defs.h:452
ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_8
@ ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_8
Definition: inv_imu_defs.h:444
ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_1024
@ ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_1024
Definition: inv_imu_defs.h:451
ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_256
@ ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_256
Definition: inv_imu_defs.h:449
ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_64
@ ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_64
Definition: inv_imu_defs.h:447
ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_1
@ ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_1
Definition: inv_imu_defs.h:441
ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_2
@ ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_2
Definition: inv_imu_defs.h:442
ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_4096
@ ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_4096
Definition: inv_imu_defs.h:453
ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_512
@ ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_512
Definition: inv_imu_defs.h:450
ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_32
@ ODR_DECIMATE_CONFIG_GYRO_FIFO_ODR_DEC_32
Definition: inv_imu_defs.h:446
FIFO_CONFIG0_FIFO_MODE_BYPASS
@ FIFO_CONFIG0_FIFO_MODE_BYPASS
Definition: inv_imu_defs.h:319
FIFO_CONFIG0_FIFO_MODE_STREAM
@ FIFO_CONFIG0_FIFO_MODE_STREAM
Definition: inv_imu_defs.h:318
FIFO_CONFIG0_FIFO_MODE_SNAPSHOT
@ FIFO_CONFIG0_FIFO_MODE_SNAPSHOT
Definition: inv_imu_defs.h:317
ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_2
@ ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_2
Definition: inv_imu_defs.h:459
ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_512
@ ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_512
Definition: inv_imu_defs.h:467
ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_4
@ ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_4
Definition: inv_imu_defs.h:460
ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_32
@ ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_32
Definition: inv_imu_defs.h:463
ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_256
@ ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_256
Definition: inv_imu_defs.h:466
ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_64
@ ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_64
Definition: inv_imu_defs.h:464
ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_128
@ ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_128
Definition: inv_imu_defs.h:465
ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_16
@ ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_16
Definition: inv_imu_defs.h:462
ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_1
@ ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_1
Definition: inv_imu_defs.h:458
ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_4096
@ ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_4096
Definition: inv_imu_defs.h:470
ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_1024
@ ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_1024
Definition: inv_imu_defs.h:468
ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_8
@ ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_8
Definition: inv_imu_defs.h:461
ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_2048
@ ODR_DECIMATE_CONFIG_ACCEL_FIFO_ODR_DEC_2048
Definition: inv_imu_defs.h:469
SMC_CONTROL_0_ACCEL_LP_CLK_WUOSC
@ SMC_CONTROL_0_ACCEL_LP_CLK_WUOSC
Definition: inv_imu_defs.h:580
SMC_CONTROL_0_ACCEL_LP_CLK_RCOSC
@ SMC_CONTROL_0_ACCEL_LP_CLK_RCOSC
Definition: inv_imu_defs.h:579
IPREG_SYS2_REG_123_ACCEL_SRC_CTRL_INTERPOLATOR_ON_FIR_ON
@ IPREG_SYS2_REG_123_ACCEL_SRC_CTRL_INTERPOLATOR_ON_FIR_ON
Definition: inv_imu_defs.h:666
IPREG_SYS2_REG_123_ACCEL_SRC_CTRL_INTERPOLATOR_OFF_FIR_OFF
@ IPREG_SYS2_REG_123_ACCEL_SRC_CTRL_INTERPOLATOR_OFF_FIR_OFF
Definition: inv_imu_defs.h:668
IPREG_SYS2_REG_123_ACCEL_SRC_CTRL_INTERPOLATOR_OFF_FIR_ON
@ IPREG_SYS2_REG_123_ACCEL_SRC_CTRL_INTERPOLATOR_OFF_FIR_ON
Definition: inv_imu_defs.h:667
REG_MISC1_OSC_ID_OVRD_PLL
@ REG_MISC1_OSC_ID_OVRD_PLL
Definition: inv_imu_defs.h:535
REG_MISC1_OSC_ID_OVRD_EXT_CLK
@ REG_MISC1_OSC_ID_OVRD_EXT_CLK
Definition: inv_imu_defs.h:536
REG_MISC1_OSC_ID_OVRD_RCOSC
@ REG_MISC1_OSC_ID_OVRD_RCOSC
Definition: inv_imu_defs.h:534
REG_MISC1_OSC_ID_OVRD_OFF
@ REG_MISC1_OSC_ID_OVRD_OFF
Definition: inv_imu_defs.h:532
REG_MISC1_OSC_ID_OVRD_EDOSC
@ REG_MISC1_OSC_ID_OVRD_EDOSC
Definition: inv_imu_defs.h:533
ACCEL_CONFIG0_ACCEL_ODR_3_125_HZ
@ ACCEL_CONFIG0_ACCEL_ODR_3_125_HZ
Definition: inv_imu_defs.h:261
ACCEL_CONFIG0_ACCEL_ODR_100_HZ
@ ACCEL_CONFIG0_ACCEL_ODR_100_HZ
Definition: inv_imu_defs.h:266
ACCEL_CONFIG0_ACCEL_ODR_50_HZ
@ ACCEL_CONFIG0_ACCEL_ODR_50_HZ
Definition: inv_imu_defs.h:265
ACCEL_CONFIG0_ACCEL_ODR_1_5625_HZ
@ ACCEL_CONFIG0_ACCEL_ODR_1_5625_HZ
Definition: inv_imu_defs.h:260
ACCEL_CONFIG0_ACCEL_ODR_6_25_HZ
@ ACCEL_CONFIG0_ACCEL_ODR_6_25_HZ
Definition: inv_imu_defs.h:262
ACCEL_CONFIG0_ACCEL_ODR_6400_HZ
@ ACCEL_CONFIG0_ACCEL_ODR_6400_HZ
Definition: inv_imu_defs.h:272
ACCEL_CONFIG0_ACCEL_ODR_12_5_HZ
@ ACCEL_CONFIG0_ACCEL_ODR_12_5_HZ
Definition: inv_imu_defs.h:263
ACCEL_CONFIG0_ACCEL_ODR_1600_HZ
@ ACCEL_CONFIG0_ACCEL_ODR_1600_HZ
Definition: inv_imu_defs.h:270
ACCEL_CONFIG0_ACCEL_ODR_25_HZ
@ ACCEL_CONFIG0_ACCEL_ODR_25_HZ
Definition: inv_imu_defs.h:264
ACCEL_CONFIG0_ACCEL_ODR_3200_HZ
@ ACCEL_CONFIG0_ACCEL_ODR_3200_HZ
Definition: inv_imu_defs.h:271
ACCEL_CONFIG0_ACCEL_ODR_400_HZ
@ ACCEL_CONFIG0_ACCEL_ODR_400_HZ
Definition: inv_imu_defs.h:268
ACCEL_CONFIG0_ACCEL_ODR_200_HZ
@ ACCEL_CONFIG0_ACCEL_ODR_200_HZ
Definition: inv_imu_defs.h:267
ACCEL_CONFIG0_ACCEL_ODR_800_HZ
@ ACCEL_CONFIG0_ACCEL_ODR_800_HZ
Definition: inv_imu_defs.h:269
INTX_CONFIG2_INTX_MODE_PULSE
@ INTX_CONFIG2_INTX_MODE_PULSE
Definition: inv_imu_defs.h:226
INTX_CONFIG2_INTX_MODE_LATCH
@ INTX_CONFIG2_INTX_MODE_LATCH
Definition: inv_imu_defs.h:227
IPREG_SYS1_REG_170_GYRO_LP_AVG_18
@ IPREG_SYS1_REG_170_GYRO_LP_AVG_18
Definition: inv_imu_defs.h:629
IPREG_SYS1_REG_170_GYRO_LP_AVG_2
@ IPREG_SYS1_REG_170_GYRO_LP_AVG_2
Definition: inv_imu_defs.h:637
IPREG_SYS1_REG_170_GYRO_LP_AVG_32
@ IPREG_SYS1_REG_170_GYRO_LP_AVG_32
Definition: inv_imu_defs.h:627
IPREG_SYS1_REG_170_GYRO_LP_AVG_20
@ IPREG_SYS1_REG_170_GYRO_LP_AVG_20
Definition: inv_imu_defs.h:628
IPREG_SYS1_REG_170_GYRO_LP_AVG_1
@ IPREG_SYS1_REG_170_GYRO_LP_AVG_1
Definition: inv_imu_defs.h:638
IPREG_SYS1_REG_170_GYRO_LP_AVG_5
@ IPREG_SYS1_REG_170_GYRO_LP_AVG_5
Definition: inv_imu_defs.h:635
IPREG_SYS1_REG_170_GYRO_LP_AVG_7
@ IPREG_SYS1_REG_170_GYRO_LP_AVG_7
Definition: inv_imu_defs.h:634
IPREG_SYS1_REG_170_GYRO_LP_AVG_8
@ IPREG_SYS1_REG_170_GYRO_LP_AVG_8
Definition: inv_imu_defs.h:633
IPREG_SYS1_REG_170_GYRO_LP_AVG_4
@ IPREG_SYS1_REG_170_GYRO_LP_AVG_4
Definition: inv_imu_defs.h:636
IPREG_SYS1_REG_170_GYRO_LP_AVG_10
@ IPREG_SYS1_REG_170_GYRO_LP_AVG_10
Definition: inv_imu_defs.h:632
IPREG_SYS1_REG_170_GYRO_LP_AVG_16
@ IPREG_SYS1_REG_170_GYRO_LP_AVG_16
Definition: inv_imu_defs.h:630
IPREG_SYS1_REG_170_GYRO_LP_AVG_11
@ IPREG_SYS1_REG_170_GYRO_LP_AVG_11
Definition: inv_imu_defs.h:631
IPREG_SYS1_REG_170_GYRO_LP_AVG_64
@ IPREG_SYS1_REG_170_GYRO_LP_AVG_64
Definition: inv_imu_defs.h:626
IPREG_SYS2_REG_129_ACCEL_LP_AVG_16
@ IPREG_SYS2_REG_129_ACCEL_LP_AVG_16
Definition: inv_imu_defs.h:681
IPREG_SYS2_REG_129_ACCEL_LP_AVG_64
@ IPREG_SYS2_REG_129_ACCEL_LP_AVG_64
Definition: inv_imu_defs.h:677
IPREG_SYS2_REG_129_ACCEL_LP_AVG_11
@ IPREG_SYS2_REG_129_ACCEL_LP_AVG_11
Definition: inv_imu_defs.h:682
IPREG_SYS2_REG_129_ACCEL_LP_AVG_7
@ IPREG_SYS2_REG_129_ACCEL_LP_AVG_7
Definition: inv_imu_defs.h:685
IPREG_SYS2_REG_129_ACCEL_LP_AVG_18
@ IPREG_SYS2_REG_129_ACCEL_LP_AVG_18
Definition: inv_imu_defs.h:680
IPREG_SYS2_REG_129_ACCEL_LP_AVG_4
@ IPREG_SYS2_REG_129_ACCEL_LP_AVG_4
Definition: inv_imu_defs.h:687
IPREG_SYS2_REG_129_ACCEL_LP_AVG_2
@ IPREG_SYS2_REG_129_ACCEL_LP_AVG_2
Definition: inv_imu_defs.h:688
IPREG_SYS2_REG_129_ACCEL_LP_AVG_10
@ IPREG_SYS2_REG_129_ACCEL_LP_AVG_10
Definition: inv_imu_defs.h:683
IPREG_SYS2_REG_129_ACCEL_LP_AVG_5
@ IPREG_SYS2_REG_129_ACCEL_LP_AVG_5
Definition: inv_imu_defs.h:686
IPREG_SYS2_REG_129_ACCEL_LP_AVG_1
@ IPREG_SYS2_REG_129_ACCEL_LP_AVG_1
Definition: inv_imu_defs.h:689
IPREG_SYS2_REG_129_ACCEL_LP_AVG_32
@ IPREG_SYS2_REG_129_ACCEL_LP_AVG_32
Definition: inv_imu_defs.h:678
IPREG_SYS2_REG_129_ACCEL_LP_AVG_20
@ IPREG_SYS2_REG_129_ACCEL_LP_AVG_20
Definition: inv_imu_defs.h:679
IPREG_SYS2_REG_129_ACCEL_LP_AVG_8
@ IPREG_SYS2_REG_129_ACCEL_LP_AVG_8
Definition: inv_imu_defs.h:684
DMP_EXT_SEN_ODR_CFG_EXT_ODR_12_5_HZ
@ DMP_EXT_SEN_ODR_CFG_EXT_ODR_12_5_HZ
Definition: inv_imu_defs.h:417
DMP_EXT_SEN_ODR_CFG_EXT_ODR_400_HZ
@ DMP_EXT_SEN_ODR_CFG_EXT_ODR_400_HZ
Definition: inv_imu_defs.h:422
DMP_EXT_SEN_ODR_CFG_EXT_ODR_100_HZ
@ DMP_EXT_SEN_ODR_CFG_EXT_ODR_100_HZ
Definition: inv_imu_defs.h:420
DMP_EXT_SEN_ODR_CFG_EXT_ODR_6_25_HZ
@ DMP_EXT_SEN_ODR_CFG_EXT_ODR_6_25_HZ
Definition: inv_imu_defs.h:416
DMP_EXT_SEN_ODR_CFG_EXT_ODR_50_HZ
@ DMP_EXT_SEN_ODR_CFG_EXT_ODR_50_HZ
Definition: inv_imu_defs.h:419
DMP_EXT_SEN_ODR_CFG_EXT_ODR_25_HZ
@ DMP_EXT_SEN_ODR_CFG_EXT_ODR_25_HZ
Definition: inv_imu_defs.h:418
DMP_EXT_SEN_ODR_CFG_EXT_ODR_200_HZ
@ DMP_EXT_SEN_ODR_CFG_EXT_ODR_200_HZ
Definition: inv_imu_defs.h:421
DMP_EXT_SEN_ODR_CFG_EXT_ODR_3_25_HZ
@ DMP_EXT_SEN_ODR_CFG_EXT_ODR_3_25_HZ
Definition: inv_imu_defs.h:415
FIFO_CONFIG2_FIFO_WR_WM_EQ_OR_GT_TH
@ FIFO_CONFIG2_FIFO_WR_WM_EQ_OR_GT_TH
Definition: inv_imu_defs.h:339
FIFO_CONFIG2_FIFO_WR_WM_EQ_TH
@ FIFO_CONFIG2_FIFO_WR_WM_EQ_TH
Definition: inv_imu_defs.h:340
FS_SEL_AUX_GYRO_FS_SEL_15_625_DPS
@ FS_SEL_AUX_GYRO_FS_SEL_15_625_DPS
Definition: inv_imu_defs.h:545
FS_SEL_AUX_GYRO_FS_SEL_250_DPS
@ FS_SEL_AUX_GYRO_FS_SEL_250_DPS
Definition: inv_imu_defs.h:549
FS_SEL_AUX_GYRO_FS_SEL_125_DPS
@ FS_SEL_AUX_GYRO_FS_SEL_125_DPS
Definition: inv_imu_defs.h:548
FS_SEL_AUX_GYRO_FS_SEL_500_DPS
@ FS_SEL_AUX_GYRO_FS_SEL_500_DPS
Definition: inv_imu_defs.h:550
FS_SEL_AUX_GYRO_FS_SEL_2000_DPS
@ FS_SEL_AUX_GYRO_FS_SEL_2000_DPS
Definition: inv_imu_defs.h:552
FS_SEL_AUX_GYRO_FS_SEL_31_25_DPS
@ FS_SEL_AUX_GYRO_FS_SEL_31_25_DPS
Definition: inv_imu_defs.h:546
FS_SEL_AUX_GYRO_FS_SEL_62_5_DPS
@ FS_SEL_AUX_GYRO_FS_SEL_62_5_DPS
Definition: inv_imu_defs.h:547
FS_SEL_AUX_GYRO_FS_SEL_1000_DPS
@ FS_SEL_AUX_GYRO_FS_SEL_1000_DPS
Definition: inv_imu_defs.h:551
FSYNC_CONFIG0_AP_FSYNC_GYRO_X
@ FSYNC_CONFIG0_AP_FSYNC_GYRO_X
Definition: inv_imu_defs.h:401
FSYNC_CONFIG0_AP_FSYNC_ACCEL_X
@ FSYNC_CONFIG0_AP_FSYNC_ACCEL_X
Definition: inv_imu_defs.h:404
FSYNC_CONFIG0_AP_FSYNC_TEMP
@ FSYNC_CONFIG0_AP_FSYNC_TEMP
Definition: inv_imu_defs.h:400
FSYNC_CONFIG0_AP_FSYNC_GYRO_Z
@ FSYNC_CONFIG0_AP_FSYNC_GYRO_Z
Definition: inv_imu_defs.h:403
FSYNC_CONFIG0_AP_FSYNC_NO
@ FSYNC_CONFIG0_AP_FSYNC_NO
Definition: inv_imu_defs.h:399
FSYNC_CONFIG0_AP_FSYNC_ACCEL_Y
@ FSYNC_CONFIG0_AP_FSYNC_ACCEL_Y
Definition: inv_imu_defs.h:405
FSYNC_CONFIG0_AP_FSYNC_ACCEL_Z
@ FSYNC_CONFIG0_AP_FSYNC_ACCEL_Z
Definition: inv_imu_defs.h:406
FSYNC_CONFIG0_AP_FSYNC_GYRO_Y
@ FSYNC_CONFIG0_AP_FSYNC_GYRO_Y
Definition: inv_imu_defs.h:402
INTX_CONFIG2_INTX_DRIVE_PP
@ INTX_CONFIG2_INTX_DRIVE_PP
Definition: inv_imu_defs.h:220
INTX_CONFIG2_INTX_DRIVE_OD
@ INTX_CONFIG2_INTX_DRIVE_OD
Definition: inv_imu_defs.h:221
SELFTEST_PATCH_EN_GYRO1_PHASE2
@ SELFTEST_PATCH_EN_GYRO1_PHASE2
Definition: inv_imu_defs.h:808
SELFTEST_PATCH_EN_GYRO1_PHASE1
@ SELFTEST_PATCH_EN_GYRO1_PHASE1
Definition: inv_imu_defs.h:807
SELFTEST_PATCH_EN_ACCEL_PHASE1
@ SELFTEST_PATCH_EN_ACCEL_PHASE1
Definition: inv_imu_defs.h:805
SELFTEST_PATCH_EN_ACCEL_PHASE2
@ SELFTEST_PATCH_EN_ACCEL_PHASE2
Definition: inv_imu_defs.h:806
FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_DIS
@ FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_DIS
Definition: inv_imu_defs.h:354
FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_64_FR
@ FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_64_FR
Definition: inv_imu_defs.h:350
FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_32_FR
@ FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_32_FR
Definition: inv_imu_defs.h:351
FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_128_FR
@ FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_128_FR
Definition: inv_imu_defs.h:349
FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_8_FR
@ FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_8_FR
Definition: inv_imu_defs.h:353
FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_16_FR
@ FIFO_CONFIG4_FIFO_COMP_NC_FLOW_CFG_EVERY_16_FR
Definition: inv_imu_defs.h:352
PWR_MGMT0_GYRO_MODE_LP
@ PWR_MGMT0_GYRO_MODE_LP
Definition: inv_imu_defs.h:200
PWR_MGMT0_GYRO_MODE_STANDBY
@ PWR_MGMT0_GYRO_MODE_STANDBY
Definition: inv_imu_defs.h:201
PWR_MGMT0_GYRO_MODE_OFF
@ PWR_MGMT0_GYRO_MODE_OFF
Definition: inv_imu_defs.h:202
PWR_MGMT0_GYRO_MODE_LN
@ PWR_MGMT0_GYRO_MODE_LN
Definition: inv_imu_defs.h:199
SELFTEST_GYRO_THRESHOLD_15_PERCENT
@ SELFTEST_GYRO_THRESHOLD_15_PERCENT
Definition: inv_imu_defs.h:792
SELFTEST_GYRO_THRESHOLD_50_PERCENT
@ SELFTEST_GYRO_THRESHOLD_50_PERCENT
Definition: inv_imu_defs.h:797
SELFTEST_GYRO_THRESHOLD_25_PERCENT
@ SELFTEST_GYRO_THRESHOLD_25_PERCENT
Definition: inv_imu_defs.h:794
SELFTEST_GYRO_THRESHOLD_5_PERCENT
@ SELFTEST_GYRO_THRESHOLD_5_PERCENT
Definition: inv_imu_defs.h:790
SELFTEST_GYRO_THRESHOLD_30_PERCENT
@ SELFTEST_GYRO_THRESHOLD_30_PERCENT
Definition: inv_imu_defs.h:795
SELFTEST_GYRO_THRESHOLD_40_PERCENT
@ SELFTEST_GYRO_THRESHOLD_40_PERCENT
Definition: inv_imu_defs.h:796
SELFTEST_GYRO_THRESHOLD_20_PERCENT
@ SELFTEST_GYRO_THRESHOLD_20_PERCENT
Definition: inv_imu_defs.h:793
SELFTEST_GYRO_THRESHOLD_10_PERCENT
@ SELFTEST_GYRO_THRESHOLD_10_PERCENT
Definition: inv_imu_defs.h:791
DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_14NS
@ DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_14NS
Definition: inv_imu_defs.h:502
DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_5NS
@ DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_5NS
Definition: inv_imu_defs.h:505
DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_7NS
@ DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_7NS
Definition: inv_imu_defs.h:504
DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_10NS
@ DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_10NS
Definition: inv_imu_defs.h:503
DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_4NS
@ DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_4NS
Definition: inv_imu_defs.h:506
DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_38NS
@ DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_38NS
Definition: inv_imu_defs.h:501
DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_0_5NS
@ DRIVE_CONFIG0_PADS_SPI_SLEW_TYP_0_5NS
Definition: inv_imu_defs.h:507
FIFO_CONFIG4_FIFO_ES0_9B
@ FIFO_CONFIG4_FIFO_ES0_9B
Definition: inv_imu_defs.h:359
FIFO_CONFIG4_FIFO_ES0_6B
@ FIFO_CONFIG4_FIFO_ES0_6B
Definition: inv_imu_defs.h:360
FS_SEL_AUX_ACCEL_FS_SEL_16_G
@ FS_SEL_AUX_ACCEL_FS_SEL_16_G
Definition: inv_imu_defs.h:563
FS_SEL_AUX_ACCEL_FS_SEL_4_G
@ FS_SEL_AUX_ACCEL_FS_SEL_4_G
Definition: inv_imu_defs.h:561
FS_SEL_AUX_ACCEL_FS_SEL_2_G
@ FS_SEL_AUX_ACCEL_FS_SEL_2_G
Definition: inv_imu_defs.h:560
FS_SEL_AUX_ACCEL_FS_SEL_8_G
@ FS_SEL_AUX_ACCEL_FS_SEL_8_G
Definition: inv_imu_defs.h:562
TMST_WOM_CONFIG_WOM_MODE_CMP_INIT
@ TMST_WOM_CONFIG_WOM_MODE_CMP_INIT
Definition: inv_imu_defs.h:376
TMST_WOM_CONFIG_WOM_MODE_CMP_PREV
@ TMST_WOM_CONFIG_WOM_MODE_CMP_PREV
Definition: inv_imu_defs.h:375
PWR_MGMT0_ACCEL_MODE_OFF
@ PWR_MGMT0_ACCEL_MODE_OFF
Definition: inv_imu_defs.h:209
PWR_MGMT0_ACCEL_MODE_LP
@ PWR_MGMT0_ACCEL_MODE_LP
Definition: inv_imu_defs.h:208
PWR_MGMT0_ACCEL_MODE_LN
@ PWR_MGMT0_ACCEL_MODE_LN
Definition: inv_imu_defs.h:207
SREG_CTRL_SREG_DATA_BIG_ENDIAN
@ SREG_CTRL_SREG_DATA_BIG_ENDIAN
Definition: inv_imu_defs.h:589
SREG_CTRL_SREG_DATA_LITTLE_ENDIAN
@ SREG_CTRL_SREG_DATA_LITTLE_ENDIAN
Definition: inv_imu_defs.h:590
DMP_EXT_SEN_ODR_CFG_APEX_ODR_400_HZ
@ DMP_EXT_SEN_ODR_CFG_APEX_ODR_400_HZ
Definition: inv_imu_defs.h:431
DMP_EXT_SEN_ODR_CFG_APEX_ODR_200_HZ
@ DMP_EXT_SEN_ODR_CFG_APEX_ODR_200_HZ
Definition: inv_imu_defs.h:430
DMP_EXT_SEN_ODR_CFG_APEX_ODR_50_HZ
@ DMP_EXT_SEN_ODR_CFG_APEX_ODR_50_HZ
Definition: inv_imu_defs.h:428
DMP_EXT_SEN_ODR_CFG_APEX_ODR_800_HZ
@ DMP_EXT_SEN_ODR_CFG_APEX_ODR_800_HZ
Definition: inv_imu_defs.h:432
DMP_EXT_SEN_ODR_CFG_APEX_ODR_25_HZ
@ DMP_EXT_SEN_ODR_CFG_APEX_ODR_25_HZ
Definition: inv_imu_defs.h:427
DMP_EXT_SEN_ODR_CFG_APEX_ODR_100_HZ
@ DMP_EXT_SEN_ODR_CFG_APEX_ODR_100_HZ
Definition: inv_imu_defs.h:429
IOC_PAD_SCENARIO_OVRD_INT2_CFG_OVRD_VAL_DRDY_INTR
@ IOC_PAD_SCENARIO_OVRD_INT2_CFG_OVRD_VAL_DRDY_INTR
Definition: inv_imu_defs.h:523
IOC_PAD_SCENARIO_OVRD_INT2_CFG_OVRD_VAL_INT2
@ IOC_PAD_SCENARIO_OVRD_INT2_CFG_OVRD_VAL_INT2
Definition: inv_imu_defs.h:516
SELFTEST_AVG_TIME_80_MS
@ SELFTEST_AVG_TIME_80_MS
Definition: inv_imu_defs.h:773
SELFTEST_AVG_TIME_20_MS
@ SELFTEST_AVG_TIME_20_MS
Definition: inv_imu_defs.h:771
SELFTEST_AVG_TIME_10_MS
@ SELFTEST_AVG_TIME_10_MS
Definition: inv_imu_defs.h:770
SELFTEST_AVG_TIME_160_MS
@ SELFTEST_AVG_TIME_160_MS
Definition: inv_imu_defs.h:774
SELFTEST_AVG_TIME_40_MS
@ SELFTEST_AVG_TIME_40_MS
Definition: inv_imu_defs.h:772
SELFTEST_AVG_TIME_320_MS
@ SELFTEST_AVG_TIME_320_MS
Definition: inv_imu_defs.h:775
SELFTEST_ACCEL_THRESHOLD_20_PERCENT
@ SELFTEST_ACCEL_THRESHOLD_20_PERCENT
Definition: inv_imu_defs.h:782
SELFTEST_ACCEL_THRESHOLD_10_PERCENT
@ SELFTEST_ACCEL_THRESHOLD_10_PERCENT
Definition: inv_imu_defs.h:780
SELFTEST_ACCEL_THRESHOLD_25_PERCENT
@ SELFTEST_ACCEL_THRESHOLD_25_PERCENT
Definition: inv_imu_defs.h:783
SELFTEST_ACCEL_THRESHOLD_40_PERCENT
@ SELFTEST_ACCEL_THRESHOLD_40_PERCENT
Definition: inv_imu_defs.h:785
SELFTEST_ACCEL_THRESHOLD_50_PERCENT
@ SELFTEST_ACCEL_THRESHOLD_50_PERCENT
Definition: inv_imu_defs.h:786
SELFTEST_ACCEL_THRESHOLD_30_PERCENT
@ SELFTEST_ACCEL_THRESHOLD_30_PERCENT
Definition: inv_imu_defs.h:784
SELFTEST_ACCEL_THRESHOLD_15_PERCENT
@ SELFTEST_ACCEL_THRESHOLD_15_PERCENT
Definition: inv_imu_defs.h:781
SELFTEST_ACCEL_THRESHOLD_5_PERCENT
@ SELFTEST_ACCEL_THRESHOLD_5_PERCENT
Definition: inv_imu_defs.h:779
INTF_CONFIG1_OVRD_AP_SPI_34_MODE_OVRD_VAL_4_WIRE
@ INTF_CONFIG1_OVRD_AP_SPI_34_MODE_OVRD_VAL_4_WIRE
Definition: inv_imu_defs.h:480
INTF_CONFIG1_OVRD_AP_SPI_34_MODE_OVRD_VAL_3_WIRE
@ INTF_CONFIG1_OVRD_AP_SPI_34_MODE_OVRD_VAL_3_WIRE
Definition: inv_imu_defs.h:479
IPREG_SYS1_REG_172_GYRO_UI_LPFBW_NO_FILTER
@ IPREG_SYS1_REG_172_GYRO_UI_LPFBW_NO_FILTER
Definition: inv_imu_defs.h:653
IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_128
@ IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_128
Definition: inv_imu_defs.h:647
IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_16
@ IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_16
Definition: inv_imu_defs.h:650
IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_4
@ IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_4
Definition: inv_imu_defs.h:652
IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_32
@ IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_32
Definition: inv_imu_defs.h:649
IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_8
@ IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_8
Definition: inv_imu_defs.h:651
IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_64
@ IPREG_SYS1_REG_172_GYRO_UI_LPFBW_DIV_64
Definition: inv_imu_defs.h:648
FIFO_CONFIG0_FIFO_DEPTH_APEX
@ FIFO_CONFIG0_FIFO_DEPTH_APEX
Definition: inv_imu_defs.h:328
FIFO_CONFIG0_FIFO_DEPTH_GAF
@ FIFO_CONFIG0_FIFO_DEPTH_GAF
Definition: inv_imu_defs.h:330
FIFO_CONFIG0_FIFO_DEPTH_MAX
@ FIFO_CONFIG0_FIFO_DEPTH_MAX
Definition: inv_imu_defs.h:324
ACCEL_CONFIG0_ACCEL_UI_FS_SEL_16_G
@ ACCEL_CONFIG0_ACCEL_UI_FS_SEL_16_G
Definition: inv_imu_defs.h:252
ACCEL_CONFIG0_ACCEL_UI_FS_SEL_8_G
@ ACCEL_CONFIG0_ACCEL_UI_FS_SEL_8_G
Definition: inv_imu_defs.h:251
ACCEL_CONFIG0_ACCEL_UI_FS_SEL_2_G
@ ACCEL_CONFIG0_ACCEL_UI_FS_SEL_2_G
Definition: inv_imu_defs.h:249
ACCEL_CONFIG0_ACCEL_UI_FS_SEL_4_G
@ ACCEL_CONFIG0_ACCEL_UI_FS_SEL_4_G
Definition: inv_imu_defs.h:250
TMST_WOM_CONFIG_WOM_INT_DUR_1_SMPL
@ TMST_WOM_CONFIG_WOM_INT_DUR_1_SMPL
Definition: inv_imu_defs.h:387
TMST_WOM_CONFIG_WOM_INT_DUR_4_SMPL
@ TMST_WOM_CONFIG_WOM_INT_DUR_4_SMPL
Definition: inv_imu_defs.h:390
TMST_WOM_CONFIG_WOM_INT_DUR_2_SMPL
@ TMST_WOM_CONFIG_WOM_INT_DUR_2_SMPL
Definition: inv_imu_defs.h:388
TMST_WOM_CONFIG_WOM_INT_DUR_3_SMPL
@ TMST_WOM_CONFIG_WOM_INT_DUR_3_SMPL
Definition: inv_imu_defs.h:389
TMST_WOM_CONFIG_WOM_INT_MODE_ORED
@ TMST_WOM_CONFIG_WOM_INT_MODE_ORED
Definition: inv_imu_defs.h:382
TMST_WOM_CONFIG_WOM_INT_MODE_ANDED
@ TMST_WOM_CONFIG_WOM_INT_MODE_ANDED
Definition: inv_imu_defs.h:381
INV_IMU_INT1
@ INV_IMU_INT1
Definition: inv_imu_defs.h:103
INV_IMU_INT2
@ INV_IMU_INT2
Definition: inv_imu_defs.h:104
IPREG_SYS1_REG_166_GYRO_SRC_CTRL_INTERPOLATOR_OFF_FIR_OFF
@ IPREG_SYS1_REG_166_GYRO_SRC_CTRL_INTERPOLATOR_OFF_FIR_OFF
Definition: inv_imu_defs.h:617
IPREG_SYS1_REG_166_GYRO_SRC_CTRL_INTERPOLATOR_ON_FIR_ON
@ IPREG_SYS1_REG_166_GYRO_SRC_CTRL_INTERPOLATOR_ON_FIR_ON
Definition: inv_imu_defs.h:615
IPREG_SYS1_REG_166_GYRO_SRC_CTRL_INTERPOLATOR_OFF_FIR_ON
@ IPREG_SYS1_REG_166_GYRO_SRC_CTRL_INTERPOLATOR_OFF_FIR_ON
Definition: inv_imu_defs.h:616
IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_NO_FILTER
@ IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_NO_FILTER
Definition: inv_imu_defs.h:704
IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_4
@ IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_4
Definition: inv_imu_defs.h:703
IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_8
@ IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_8
Definition: inv_imu_defs.h:702
IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_16
@ IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_16
Definition: inv_imu_defs.h:701
IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_32
@ IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_32
Definition: inv_imu_defs.h:700
IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_128
@ IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_128
Definition: inv_imu_defs.h:698
IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_64
@ IPREG_SYS2_REG_131_ACCEL_UI_LPFBW_DIV_64
Definition: inv_imu_defs.h:699
DRIVE_CONFIG0_PADS_I2C_SLEW_TYP_20NS
@ DRIVE_CONFIG0_PADS_I2C_SLEW_TYP_20NS
Definition: inv_imu_defs.h:495
DRIVE_CONFIG0_PADS_I2C_SLEW_TYP_7NS
@ DRIVE_CONFIG0_PADS_I2C_SLEW_TYP_7NS
Definition: inv_imu_defs.h:496
TMST_WOM_CONFIG_TMST_RESOL_16_US
@ TMST_WOM_CONFIG_TMST_RESOL_16_US
Definition: inv_imu_defs.h:369
TMST_WOM_CONFIG_TMST_RESOL_1_US
@ TMST_WOM_CONFIG_TMST_RESOL_1_US
Definition: inv_imu_defs.h:370
GYRO_CONFIG0_GYRO_ODR_200_HZ
@ GYRO_CONFIG0_GYRO_ODR_200_HZ
Definition: inv_imu_defs.h:303
GYRO_CONFIG0_GYRO_ODR_3200_HZ
@ GYRO_CONFIG0_GYRO_ODR_3200_HZ
Definition: inv_imu_defs.h:307
GYRO_CONFIG0_GYRO_ODR_1600_HZ
@ GYRO_CONFIG0_GYRO_ODR_1600_HZ
Definition: inv_imu_defs.h:306
GYRO_CONFIG0_GYRO_ODR_3_125_HZ
@ GYRO_CONFIG0_GYRO_ODR_3_125_HZ
Definition: inv_imu_defs.h:297
GYRO_CONFIG0_GYRO_ODR_100_HZ
@ GYRO_CONFIG0_GYRO_ODR_100_HZ
Definition: inv_imu_defs.h:302
GYRO_CONFIG0_GYRO_ODR_800_HZ
@ GYRO_CONFIG0_GYRO_ODR_800_HZ
Definition: inv_imu_defs.h:305
GYRO_CONFIG0_GYRO_ODR_50_HZ
@ GYRO_CONFIG0_GYRO_ODR_50_HZ
Definition: inv_imu_defs.h:301
GYRO_CONFIG0_GYRO_ODR_1_5625_HZ
@ GYRO_CONFIG0_GYRO_ODR_1_5625_HZ
Definition: inv_imu_defs.h:296
GYRO_CONFIG0_GYRO_ODR_25_HZ
@ GYRO_CONFIG0_GYRO_ODR_25_HZ
Definition: inv_imu_defs.h:300
GYRO_CONFIG0_GYRO_ODR_400_HZ
@ GYRO_CONFIG0_GYRO_ODR_400_HZ
Definition: inv_imu_defs.h:304
GYRO_CONFIG0_GYRO_ODR_6_25_HZ
@ GYRO_CONFIG0_GYRO_ODR_6_25_HZ
Definition: inv_imu_defs.h:298
GYRO_CONFIG0_GYRO_ODR_12_5_HZ
@ GYRO_CONFIG0_GYRO_ODR_12_5_HZ
Definition: inv_imu_defs.h:299
GYRO_CONFIG0_GYRO_ODR_6400_HZ
@ GYRO_CONFIG0_GYRO_ODR_6400_HZ
Definition: inv_imu_defs.h:308
INTF_CONFIG1_OVRD_AP_SPI_MODE_OVRD_VAL_1_OR_2
@ INTF_CONFIG1_OVRD_AP_SPI_MODE_OVRD_VAL_1_OR_2
Definition: inv_imu_defs.h:486
INTF_CONFIG1_OVRD_AP_SPI_MODE_OVRD_VAL_0_OR_3
@ INTF_CONFIG1_OVRD_AP_SPI_MODE_OVRD_VAL_0_OR_3
Definition: inv_imu_defs.h:485
INTX_CONFIG2_INTX_POLARITY_LOW
@ INTX_CONFIG2_INTX_POLARITY_LOW
Definition: inv_imu_defs.h:232
INTX_CONFIG2_INTX_POLARITY_HIGH
@ INTX_CONFIG2_INTX_POLARITY_HIGH
Definition: inv_imu_defs.h:233
GYRO_CONFIG0_GYRO_UI_FS_SEL_62_5_DPS
@ GYRO_CONFIG0_GYRO_UI_FS_SEL_62_5_DPS
Definition: inv_imu_defs.h:283
GYRO_CONFIG0_GYRO_UI_FS_SEL_500_DPS
@ GYRO_CONFIG0_GYRO_UI_FS_SEL_500_DPS
Definition: inv_imu_defs.h:286
GYRO_CONFIG0_GYRO_UI_FS_SEL_2000_DPS
@ GYRO_CONFIG0_GYRO_UI_FS_SEL_2000_DPS
Definition: inv_imu_defs.h:288
GYRO_CONFIG0_GYRO_UI_FS_SEL_250_DPS
@ GYRO_CONFIG0_GYRO_UI_FS_SEL_250_DPS
Definition: inv_imu_defs.h:285
GYRO_CONFIG0_GYRO_UI_FS_SEL_125_DPS
@ GYRO_CONFIG0_GYRO_UI_FS_SEL_125_DPS
Definition: inv_imu_defs.h:284
GYRO_CONFIG0_GYRO_UI_FS_SEL_1000_DPS
@ GYRO_CONFIG0_GYRO_UI_FS_SEL_1000_DPS
Definition: inv_imu_defs.h:287
GYRO_CONFIG0_GYRO_UI_FS_SEL_15_625_DPS
@ GYRO_CONFIG0_GYRO_UI_FS_SEL_15_625_DPS
Definition: inv_imu_defs.h:281
GYRO_CONFIG0_GYRO_UI_FS_SEL_31_25_DPS
@ GYRO_CONFIG0_GYRO_UI_FS_SEL_31_25_DPS
Definition: inv_imu_defs.h:282
int1_config0_t
Definition: inv_imu_regmap_le.h:62
int1_config1_t
Definition: inv_imu_regmap_le.h:74
int1_status0_t
Definition: inv_imu_regmap_le.h:94
int1_status1_t
Definition: inv_imu_regmap_le.h:106
fifo_config0_t
Definition: inv_imu_regmap_le.h:131
fifo_config2_t
Definition: inv_imu_regmap_le.h:139
fifo_config3_t
Definition: inv_imu_regmap_le.h:147
fifo_config4_t
Definition: inv_imu_regmap_le.h:158
inv_imu_sensor_data_t
Sensor data from registers.
Definition: inv_imu_defs.h:95
inv_imu_sensor_data_t::temp_data
int16_t temp_data
Definition: inv_imu_defs.h:98
fifo_header_t
Describe the content of the FIFO header.
Definition: inv_imu_defs.h:108
fifo_header_t::twentybits_bit
uint8_t twentybits_bit
Definition: inv_imu_defs.h:115
fifo_header_t::accel_odr_different
uint8_t accel_odr_different
Definition: inv_imu_defs.h:112
fifo_header_t::Byte
uint8_t Byte
Definition: inv_imu_defs.h:109
fifo_header_t::accel_bit
uint8_t accel_bit
Definition: inv_imu_defs.h:117
fifo_header_t::gyro_odr_different
uint8_t gyro_odr_different
Definition: inv_imu_defs.h:111
fifo_header_t::timestamp_bit
uint8_t timestamp_bit
Definition: inv_imu_defs.h:114
fifo_header_t::ext_header
uint8_t ext_header
Definition: inv_imu_defs.h:118
fifo_header_t::gyro_bit
uint8_t gyro_bit
Definition: inv_imu_defs.h:116
fifo_header_t::fsync_bit
uint8_t fsync_bit
Definition: inv_imu_defs.h:113
fifo_comp_header_t
Describe the content of the FIFO header for compressed packets.
Definition: inv_imu_defs.h:123
fifo_comp_header_t::ext_header
uint8_t ext_header
Definition: inv_imu_defs.h:131
fifo_comp_header_t::gyro_bit
uint8_t gyro_bit
Definition: inv_imu_defs.h:129
fifo_comp_header_t::Byte
uint8_t Byte
Definition: inv_imu_defs.h:124
fifo_comp_header_t::tot_sample
uint8_t tot_sample
Definition: inv_imu_defs.h:126
fifo_comp_header_t::comp_frame
uint8_t comp_frame
Definition: inv_imu_defs.h:128
fifo_comp_header_t::accel_bit
uint8_t accel_bit
Definition: inv_imu_defs.h:130
fifo_comp_header_t::comp_ratio
uint8_t comp_ratio
Definition: inv_imu_defs.h:127
fifo_header2_t
Describe the content of the second FIFO header.
Definition: inv_imu_defs.h:136
fifo_header2_t::Byte
uint8_t Byte
Definition: inv_imu_defs.h:137
fifo_header2_t::es0_en
uint8_t es0_en
Definition: inv_imu_defs.h:139
fifo_header2_t::es1_vld
uint8_t es1_vld
Definition: inv_imu_defs.h:142
fifo_header2_t::es0_6b_9b
uint8_t es0_6b_9b
Definition: inv_imu_defs.h:143
fifo_header2_t::unused1
uint8_t unused1
Definition: inv_imu_defs.h:144
fifo_header2_t::es1_en
uint8_t es1_en
Definition: inv_imu_defs.h:140
fifo_header2_t::unused3
uint8_t unused3
Definition: inv_imu_defs.h:146
fifo_header2_t::unused2
uint8_t unused2
Definition: inv_imu_defs.h:145
fifo_header2_t::es0_vld
uint8_t es0_vld
Definition: inv_imu_defs.h:141
fifo_comp_decode_t
Describe the content of the FIFO Compression Decoding Tag.
Definition: inv_imu_defs.h:151
fifo_comp_decode_t::valid_samples_g
uint8_t valid_samples_g
Definition: inv_imu_defs.h:155
fifo_comp_decode_t::Byte
uint8_t Byte
Definition: inv_imu_defs.h:152
fifo_comp_decode_t::valid_samples_a
uint8_t valid_samples_a
Definition: inv_imu_defs.h:154
fifo_configx_t
Required registers to configure FIFO.
Definition: inv_imu_defs.h:160
fifo_configx_t::fifo_config1_0
uint8_t fifo_config1_0
Definition: inv_imu_defs.h:162
fifo_configx_t::fifo_config4
fifo_config4_t fifo_config4
Definition: inv_imu_defs.h:166
fifo_configx_t::fifo_config0
fifo_config0_t fifo_config0
Definition: inv_imu_defs.h:161
fifo_configx_t::fifo_config1_1
uint8_t fifo_config1_1
Definition: inv_imu_defs.h:163
fifo_configx_t::fifo_config3
fifo_config3_t fifo_config3
Definition: inv_imu_defs.h:165
fifo_configx_t::fifo_config2
fifo_config2_t fifo_config2
Definition: inv_imu_defs.h:164
intx_configx_t
Required registers to configure interrupts.
Definition: inv_imu_defs.h:172
intx_configx_t::int1_config1
int1_config1_t int1_config1
Definition: inv_imu_defs.h:174
intx_configx_t::int1_config0
int1_config0_t int1_config0
Definition: inv_imu_defs.h:173
intx_statusx_t
Registers to retrieve interrupts status.
Definition: inv_imu_defs.h:180
intx_statusx_t::int1_status0
int1_status0_t int1_status0
Definition: inv_imu_defs.h:181
intx_statusx_t::int1_status1
int1_status1_t int1_status1
Definition: inv_imu_defs.h:182
inv_imu_int_pin_config_t
Interrupts pin configuration.
Definition: inv_imu_defs.h:237
inv_imu_int_pin_config_t::int_drive
intx_config2_intx_drive_t int_drive
Definition: inv_imu_defs.h:240
inv_imu_int_pin_config_t::int_polarity
intx_config2_intx_polarity_t int_polarity
Definition: inv_imu_defs.h:238
inv_imu_int_pin_config_t::int_mode
intx_config2_intx_mode_t int_mode
Definition: inv_imu_defs.h:239