| eMD IIM4265x Driver API 1.0.0

Ixm42xxxTransport.c
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1 /*
2 * ________________________________________________________________________________________________________
3 * Copyright (c) 2015-2015 InvenSense Inc. All rights reserved.
4 *
5 * This software, related documentation and any modifications thereto (collectively “Software”) is subject
6 * to InvenSense and its licensors' intellectual property rights under U.S. and international copyright
7 * and other intellectual property rights laws.
8 *
9 * InvenSense and its licensors retain all intellectual property and proprietary rights in and to the Software
10 * and any use, reproduction, disclosure or distribution of the Software without an express license agreement
11 * from InvenSense is strictly prohibited.
12 *
13 * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE SOFTWARE IS
14 * PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
15 * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
16 * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL
17 * INVENSENSE BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY
18 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
19 * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THE SOFTWARE.
21 * ________________________________________________________________________________________________________
22 */
23
24 #include "Invn/Drivers/Ixm42xxx/Ixm42xxxTransport.h"
25 #include "Invn/Drivers/Ixm42xxx/Ixm42xxxDefs.h"
26
27 #include "Invn/InvError.h"
28
29
30 /* Function definition */
31 static uint8_t * get_register_cache_addr(struct inv_ixm42xxx * s, uint8_t reg);
32 static uint8_t is_aux_interface(struct inv_ixm42xxx_transport *t);
33
34
35 int inv_ixm42xxx_init_transport(struct inv_ixm42xxx * s)
36 {
37 // Registers in cache must be in bank 0
38 int status = 0;
39 struct inv_ixm42xxx_transport *t = (struct inv_ixm42xxx_transport *)s;
40
41 if(!is_aux_interface(t)){
42 status |= t->serif.read_reg(&(t->serif), MPUREG_INTF_CONFIG1, &(t->register_cache.intf_cfg_1_reg), 1);
43 status |= t->serif.read_reg(&(t->serif), MPUREG_PWR_MGMT_0, &(t->register_cache.pwr_mngt_0_reg), 1);
44 status |= t->serif.read_reg(&(t->serif), MPUREG_GYRO_CONFIG0, &(t->register_cache.gyro_cfg_0_reg), 1);
45 status |= t->serif.read_reg(&(t->serif), MPUREG_ACCEL_CONFIG0, &(t->register_cache.accel_cfg_0_reg), 1);
46 status |= t->serif.read_reg(&(t->serif), MPUREG_TMST_CONFIG, &(t->register_cache.tmst_cfg_reg), 1);
47 }
48
49 status |= t->serif.read_reg(&(t->serif), MPUREG_REG_BANK_SEL, &(t->register_cache.bank_sel_reg), 1);
50
51 return status;
52 }
53
54 int inv_ixm42xxx_read_reg(struct inv_ixm42xxx * s, uint8_t reg, uint32_t len, uint8_t * buf)
55 {
56 // First field of struct inv_ixm42xxx is assumed to be a struct inv_ixm42xxx_transport object.
57 // So let's cast s to struct inv_ixm42xxx_transport and ignore the rest of struct inv_ixm42xxx.
58 struct inv_ixm42xxx_transport *t = (struct inv_ixm42xxx_transport *)s;
59 uint32_t i=0;
60
61 // Registers in cache are only in bank 0
62 // Check if bank0 is used because of duplicate register addresses between banks
63 // For AUX interface, register cache must not be used
64 if((t->register_cache.bank_sel_reg == 0) && (is_aux_interface(t) == 0)) {
65 for(i=0; i<len ; i++) {
66 uint8_t * cache_addr = get_register_cache_addr(s, reg+i);
67 if(cache_addr)
68 buf[i] = *cache_addr;
69 else
70 break; // If one register isn't in cache, exit the loop and proceed a physical access
71 }
72
73 if(i==len) // If the end of loop is reached, then all registers have been read in cache so return
74 return 0;
75 }
76
77 // Physical access to read registers
78 if((len-i) > t->serif.max_read)
79 return INV_ERROR_SIZE;
80 if(t->serif.read_reg(&(t->serif), reg+i, &buf[i], len-i) != 0)
81 return INV_ERROR_TRANSPORT;
82
83 return 0;
84 }
85
86 int inv_ixm42xxx_write_reg(struct inv_ixm42xxx * s, uint8_t reg, uint32_t len, const uint8_t * buf)
87 {
88 // First field of struct inv_ixm42xxx is assumed to be a struct inv_ixm42xxx_transport object.
89 // So let's cast s to struct inv_ixm42xxx_transport and ignore the rest of struct inv_ixm42xxx.
90 struct inv_ixm42xxx_transport *t = (struct inv_ixm42xxx_transport *)s;
91 uint32_t i;
92
93 if(len > t->serif.max_write)
94 return INV_ERROR_SIZE;
95
96
97 for(i=0; i<len; i++) {
98 // Update bank_sel_reg in the cache
99 if((reg+i) == MPUREG_REG_BANK_SEL){
100 t->register_cache.bank_sel_reg = buf[i];
101 }
102 else {
103 uint8_t * cache_addr = get_register_cache_addr(s, reg+i);
104 if(cache_addr){
105 if (t->register_cache.bank_sel_reg == 0){
106 if(is_aux_interface(t) == 1)
107 return INV_ERROR_BAD_ARG; // Cached registers must not be written from AUX interface
108 else
109 *cache_addr = buf[i]; // Update register cache if the current bank is 0
110 }
111 }
112 }
113 }
114
115 // Physical access to write registers
116 if(t->serif.write_reg(&(t->serif), reg, buf, len) != 0)
117 return INV_ERROR_TRANSPORT;
118
119 return 0;
120 }
121
122 /* Static function */
123
124 /* MPUREG_REG_BANK_SEL shall never be added to the function get_register_cache_addr() */
125 static uint8_t * get_register_cache_addr(struct inv_ixm42xxx * s, uint8_t reg)
126 {
127 struct inv_ixm42xxx_transport *t = (struct inv_ixm42xxx_transport *)s;
128
129 switch(reg) {
130 case MPUREG_INTF_CONFIG1: return &(t->register_cache.intf_cfg_1_reg);
131 case MPUREG_PWR_MGMT_0: return &(t->register_cache.pwr_mngt_0_reg);
132 case MPUREG_GYRO_CONFIG0: return &(t->register_cache.gyro_cfg_0_reg);
133 case MPUREG_ACCEL_CONFIG0: return &(t->register_cache.accel_cfg_0_reg);
134 case MPUREG_TMST_CONFIG: return &(t->register_cache.tmst_cfg_reg);
135 default: return (uint8_t *)0; // Not found
136 }
137 }
138
139 static uint8_t is_aux_interface(struct inv_ixm42xxx_transport *t)
140 {
141 if ((t->serif.serif_type == IXM42XXX_AUX1_SPI3) || (t->serif.serif_type == IXM42XXX_AUX2_SPI3))
142 return 1;
143 else
144 return 0;
145 }
Ixm42xxxDefs.h
inv_ixm42xxx
Ixm42xxx driver states definition.
Definition: Ixm42xxxDriver_HL.h:164
inv_ixm42xxx_init_transport
int inv_ixm42xxx_init_transport(struct inv_ixm42xxx *s)
Init cache variable.
Definition: Ixm42xxxTransport.c:35
MPUREG_TMST_CONFIG
#define MPUREG_TMST_CONFIG
Definition: Ixm42xxxDefs.h:118
inv_ixm42xxx_transport::register_cache::tmst_cfg_reg
uint8_t tmst_cfg_reg
Definition: Ixm42xxxTransport.h:82
inv_ixm42xxx_serif::read_reg
int(* read_reg)(struct inv_ixm42xxx_serif *serif, uint8_t reg, uint8_t *buf, uint32_t len)
Definition: Ixm42xxxTransport.h:63
MPUREG_REG_BANK_SEL
#define MPUREG_REG_BANK_SEL
Definition: Ixm42xxxDefs.h:135
MPUREG_ACCEL_CONFIG0
#define MPUREG_ACCEL_CONFIG0
Definition: Ixm42xxxDefs.h:114
inv_ixm42xxx_serif::max_write
uint32_t max_write
Definition: Ixm42xxxTransport.h:67
Ixm42xxxTransport.h
inv_ixm42xxx_transport
transport interface
Definition: Ixm42xxxTransport.h:73
inv_ixm42xxx_transport::register_cache
struct inv_ixm42xxx_transport::register_cache register_cache
inv_ixm42xxx_transport::register_cache::pwr_mngt_0_reg
uint8_t pwr_mngt_0_reg
Definition: Ixm42xxxTransport.h:79
inv_ixm42xxx_transport::register_cache::accel_cfg_0_reg
uint8_t accel_cfg_0_reg
Definition: Ixm42xxxTransport.h:81
IXM42XXX_AUX1_SPI3
@ IXM42XXX_AUX1_SPI3
Definition: Ixm42xxxTransport.h:54
inv_ixm42xxx_serif::max_read
uint32_t max_read
Definition: Ixm42xxxTransport.h:66
inv_ixm42xxx_transport::register_cache::intf_cfg_1_reg
uint8_t intf_cfg_1_reg
Definition: Ixm42xxxTransport.h:78
MPUREG_PWR_MGMT_0
#define MPUREG_PWR_MGMT_0
Definition: Ixm42xxxDefs.h:112
inv_ixm42xxx_transport::serif
struct inv_ixm42xxx_serif serif
Definition: Ixm42xxxTransport.h:74
inv_ixm42xxx_transport::register_cache::gyro_cfg_0_reg
uint8_t gyro_cfg_0_reg
Definition: Ixm42xxxTransport.h:80
inv_ixm42xxx_serif::write_reg
int(* write_reg)(struct inv_ixm42xxx_serif *serif, uint8_t reg, const uint8_t *buf, uint32_t len)
Definition: Ixm42xxxTransport.h:64
MPUREG_INTF_CONFIG1
#define MPUREG_INTF_CONFIG1
Definition: Ixm42xxxDefs.h:111
inv_ixm42xxx_write_reg
int inv_ixm42xxx_write_reg(struct inv_ixm42xxx *s, uint8_t reg, uint32_t len, const uint8_t *buf)
Writes data to a register on Ixm42xxx.
Definition: Ixm42xxxTransport.c:86
MPUREG_GYRO_CONFIG0
#define MPUREG_GYRO_CONFIG0
Definition: Ixm42xxxDefs.h:113
IXM42XXX_AUX2_SPI3
@ IXM42XXX_AUX2_SPI3
Definition: Ixm42xxxTransport.h:55
inv_ixm42xxx_read_reg
int inv_ixm42xxx_read_reg(struct inv_ixm42xxx *s, uint8_t reg, uint32_t len, uint8_t *buf)
Reads data from a register on Ixm42xxx.
Definition: Ixm42xxxTransport.c:54
inv_ixm42xxx_serif::serif_type
IXM42XXX_SERIAL_IF_TYPE_t serif_type
Definition: Ixm42xxxTransport.h:68
inv_ixm42xxx_transport::register_cache::bank_sel_reg
uint8_t bank_sel_reg
Definition: Ixm42xxxTransport.h:83