| eMD IIM4265x Driver API 1.0.0

Ixm42xxxDriver_HL_apex.c
Go to the documentation of this file.
1 /*
2 * ________________________________________________________________________________________________________
3 * Copyright (c) 2017 InvenSense Inc. All rights reserved.
4 *
5 * This software, related documentation and any modifications thereto (collectively “Software”) is subject
6 * to InvenSense and its licensors' intellectual property rights under U.S. and international copyright
7 * and other intellectual property rights laws.
8 *
9 * InvenSense and its licensors retain all intellectual property and proprietary rights in and to the Software
10 * and any use, reproduction, disclosure or distribution of the Software without an express license agreement
11 * from InvenSense is strictly prohibited.
12 *
13 * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE SOFTWARE IS
14 * PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
15 * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
16 * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL
17 * INVENSENSE BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY
18 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
19 * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THE SOFTWARE.
21 * ________________________________________________________________________________________________________
22 */
23
24 #include "Invn/Drivers/Ixm42xxx/Ixm42xxxDefs.h"
25 #include "Invn/Drivers/Ixm42xxx/Ixm42xxxExtFunc.h"
26 #include "Invn/Drivers/Ixm42xxx/Ixm42xxxDriver_HL.h"
27 #include "Invn/Drivers/Ixm42xxx/Ixm42xxxDriver_HL_apex.h"
28
29 static int inv_ixm42xxx_resume_dmp(struct inv_ixm42xxx * s);
30 static int inv_ixm42xxx_reset_dmp(struct inv_ixm42xxx * s);
31
32 int inv_ixm42xxx_configure_smd_wom(struct inv_ixm42xxx * s, const uint8_t x_th, const uint8_t y_th, const uint8_t z_th, IXM42XXX_SMD_CONFIG_WOM_INT_MODE_t wom_int, IXM42XXX_SMD_CONFIG_WOM_MODE_t wom_mode)
33 {
34 int status = 0;
35 uint8_t data[3];
36
37 /* Set memory bank 4 */
38 status |= inv_ixm42xxx_set_reg_bank(s, 4);
39
40 data[0] = x_th; /* Set X threshold */
41 data[1] = y_th; /* Set Y threshold */
42 data[2] = z_th; /* Set Z threshold */
43 status |= inv_ixm42xxx_write_reg(s, MPUREG_ACCEL_WOM_X_THR_B4, sizeof(data), &data[0]);
44
45 /* Set memory bank 0 */
46 status |= inv_ixm42xxx_set_reg_bank(s, 0);
47
48 data[0] = ((uint8_t)wom_int) | ((uint8_t)wom_mode);
49 status |= inv_ixm42xxx_write_reg(s, MPUREG_SMD_CONFIG, 1, &data[0]);
50
51 return status;
52 }
53
54 int inv_ixm42xxx_enable_wom(struct inv_ixm42xxx * s)
55 {
56 uint8_t data;
57 int status = 0;
58 inv_ixm42xxx_interrupt_parameter_t config_int = {(inv_ixm42xxx_interrupt_value)0};
59
60 /* Enable WOM only if SMD is not enabled
61 * If SMD is enabled, WOM event will be generated
62 */
63 if (s->wom_smd_mask == IXM42XXX_SMD_CONFIG_SMD_MODE_DISABLED) {
64 /* Set SMD mode to WOM */
65 status |= inv_ixm42xxx_read_reg(s, MPUREG_SMD_CONFIG, 1, &data);
66 data &= (uint8_t)~BIT_SMD_CONFIG_SMD_MODE_MASK;
67 data |= (uint8_t)IXM42XXX_SMD_CONFIG_SMD_MODE_WOM;
68 status |= inv_ixm42xxx_write_reg(s, MPUREG_SMD_CONFIG, 1, &data);
69 /* Update mask to inform wom is enabled */
70 s->wom_smd_mask = IXM42XXX_SMD_CONFIG_SMD_MODE_WOM;
71 }
72
73 /* Disable fifo threshold int1 */
74 status |= inv_ixm42xxx_get_config_int1(s, &config_int);
75 config_int.INV_IXM42XXX_FIFO_THS = INV_IXM42XXX_DISABLE;
76 status |= inv_ixm42xxx_set_config_int1(s, &config_int);
77
78 /* Disable data ready ibi (used instead of FIFO THS for I3C) */
79 status |= inv_ixm42xxx_get_config_ibi(s, &config_int);
80 config_int.INV_IXM42XXX_UI_DRDY = INV_IXM42XXX_DISABLE;
81 status |= inv_ixm42xxx_set_config_ibi(s, &config_int);
82
83 s->wom_enable = 1;
84
85 return status;
86 }
87
88 int inv_ixm42xxx_disable_wom(struct inv_ixm42xxx * s)
89 {
90 uint8_t data;
91 int status = 0;
92 inv_ixm42xxx_interrupt_parameter_t config_int = {(inv_ixm42xxx_interrupt_value)0};
93
94 /* Enable fifo threshold int1 */
95 status |= inv_ixm42xxx_get_config_int1(s, &config_int);
96 config_int.INV_IXM42XXX_FIFO_THS = INV_IXM42XXX_ENABLE;
97 status |= inv_ixm42xxx_set_config_int1(s, &config_int);
98
99 /* Enable data ready ibi (used instead of FIFO THS for I3C) */
100 status |= inv_ixm42xxx_get_config_ibi(s, &config_int);
101 config_int.INV_IXM42XXX_UI_DRDY = INV_IXM42XXX_ENABLE;
102 status |= inv_ixm42xxx_set_config_ibi(s, &config_int);
103
104 if(s->wom_smd_mask == IXM42XXX_SMD_CONFIG_SMD_MODE_WOM) {
105 /* Set SMD mode to disabled */
106 status |= inv_ixm42xxx_read_reg(s, MPUREG_SMD_CONFIG, 1, &data);
107 data &= (uint8_t)~BIT_SMD_CONFIG_SMD_MODE_MASK; /* == IXM42XXX_SMD_CONFIG_SMD_MODE_DISABLED */
108 status |= inv_ixm42xxx_write_reg(s, MPUREG_SMD_CONFIG, 1, &data);
109 /* Update mask to inform wom is disabled */
110 s->wom_smd_mask = IXM42XXX_SMD_CONFIG_SMD_MODE_DISABLED;
111 }
112 s->wom_enable = 0;
113
114 return status;
115 }
116
117 int inv_ixm42xxx_enable_smd(struct inv_ixm42xxx * s)
118 {
119 uint8_t data;
120 int status = 0;
121
122 /*
123 * SMD engine is based on two occurences of WoM events within a defined timeframe.
124 * POR value for WoM mode is to compare current sample against first sample,
125 * which may happen during accel engine stabilisation and therefore could
126 * be significantly different compared to the normalised value. Comparing
127 * the two has a higher chance of leading to wrong SMD events signalling,
128 * therefore it is required to configure WoM to compare the current sample
129 * against the previous sample instead.
130 */
131
132 /* Set SMD mode to SMD */
133 status |= inv_ixm42xxx_read_reg(s, MPUREG_SMD_CONFIG, 1, &data);
134 data &= (uint8_t)~BIT_SMD_CONFIG_SMD_MODE_MASK;
135 data |= (uint8_t)IXM42XXX_SMD_CONFIG_SMD_MODE_LONG;
136 status |= inv_ixm42xxx_write_reg(s, MPUREG_SMD_CONFIG, 1, &data);
137 /* Update mask to inform smd is enabled */
138 s->wom_smd_mask = IXM42XXX_SMD_CONFIG_SMD_MODE_LONG;
139
140 return status;
141 }
142
143 int inv_ixm42xxx_disable_smd(struct inv_ixm42xxx * s)
144 {
145 uint8_t data;
146 int status = 0;
147
148 status |= inv_ixm42xxx_read_reg(s, MPUREG_SMD_CONFIG, 1, &data);
149 data &= (uint8_t)~BIT_SMD_CONFIG_SMD_MODE_MASK;
150
151 if (s->wom_smd_mask == IXM42XXX_SMD_CONFIG_SMD_MODE_SHORT ||
152 s->wom_smd_mask == IXM42XXX_SMD_CONFIG_SMD_MODE_LONG) {
153 if (s->wom_enable == 1) {
154 data |= (uint8_t)IXM42XXX_SMD_CONFIG_SMD_MODE_WOM;
155 s->wom_smd_mask = IXM42XXX_SMD_CONFIG_SMD_MODE_WOM;
156 } else {
157 s->wom_smd_mask = IXM42XXX_SMD_CONFIG_SMD_MODE_DISABLED;
158 }
159 }
160
161 status |= inv_ixm42xxx_write_reg(s, MPUREG_SMD_CONFIG, 1, &data);
162
163 return status;
164 }
165
166 int inv_ixm42xxx_init_tap_parameters_struct(struct inv_ixm42xxx *s, inv_ixm42xxx_tap_parameters_t *tap_inputs)
167 {
168 /* Default parameters at POR */
169 tap_inputs->min_jerk_thr = IXM42XXX_APEX_CONFIG7_TAP_MIN_JERK_THR_281MG_DEFAULT;
170 tap_inputs->max_peak_tol = IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_25;
171 tap_inputs->tmax = IXM42XXX_APEX_CONFIG8_TAP_TMAX_500MS;
172 tap_inputs->tmin = IXM42XXX_APEX_CONFIG8_TAP_TMIN_171MS;
173 tap_inputs->tavg = IXM42XXX_APEX_CONFIG8_TAP_TAVG_8SAMPLE;
174
175 return 0;
176 }
177
178 int inv_ixm42xxx_configure_tap_parameters(struct inv_ixm42xxx * s, const inv_ixm42xxx_tap_parameters_t *tap_inputs)
179 {
180 int status = 0;
181 uint8_t data[2];
182
183 data[0] = ((tap_inputs->min_jerk_thr << 2) | tap_inputs->max_peak_tol);
184 data[1] = ((uint8_t)tap_inputs->tmax | (uint8_t)tap_inputs->tmin | (uint8_t)tap_inputs->tavg);
185
186 /* Set memory bank 4 */
187 status |= inv_ixm42xxx_set_reg_bank(s, 4);
188
189 status |= inv_ixm42xxx_write_reg(s, MPUREG_APEX_CONFIG7_B4, sizeof(data), &data[0]);
190
191 /* Set memory bank 0 */
192 status |= inv_ixm42xxx_set_reg_bank(s, 0);
193
194 return status;
195 }
196
197 int inv_ixm42xxx_get_tap_parameters(struct inv_ixm42xxx *s, inv_ixm42xxx_tap_parameters_t *tap_params)
198 {
199 int status = 0;
200 uint8_t data[2];
201
202 /* Set memory bank 4 */
203 status |= inv_ixm42xxx_set_reg_bank(s, 4);
204
205 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_CONFIG7_B4, sizeof(data), &data[0]);
206
207 /* Set memory bank 0 */
208 status |= inv_ixm42xxx_set_reg_bank(s, 0);
209
210 tap_params->min_jerk_thr = (data[0] & BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_MASK) >> BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS;
211 tap_params->max_peak_tol = (IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t)(data[0] & BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_MASK);
212 tap_params->tmax = (IXM42XXX_APEX_CONFIG8_TAP_TMAX_t)(data[1] & BIT_APEX_CONFIG8_TAP_TMAX_MASK);
213 tap_params->tmin = (IXM42XXX_APEX_CONFIG8_TAP_TMIN_t)(data[1] & BIT_APEX_CONFIG8_TAP_TMIN_MASK);
214 tap_params->tavg = (IXM42XXX_APEX_CONFIG8_TAP_TAVG_t)(data[1] & BIT_APEX_CONFIG8_TAP_TAVG_MASK);
215
216 return status;
217 }
218
219 int inv_ixm42xxx_enable_tap(struct inv_ixm42xxx * s)
220 {
221 uint8_t data;
222 int status = 0;
223
224 /* Enable TAP */
225 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
226 data |= (uint8_t)IXM42XXX_APEX_CONFIG0_TAP_ENABLE_EN;
227 status |= inv_ixm42xxx_write_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
228
229 return status;
230 }
231
232 int inv_ixm42xxx_disable_tap(struct inv_ixm42xxx * s)
233 {
234 uint8_t data;
235 int status = 0;
236
237 /* Disable TAP */
238 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
239 data &= (uint8_t)~BIT_APEX_CONFIG0_TAP_ENABLE_MASK; /* == IXM42XXX_APEX_CONFIG0_TAP_ENABLE_DIS */
240 status |= inv_ixm42xxx_write_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
241
242 return status;
243 }
244
245 int inv_ixm42xxx_init_apex_parameters_struct(struct inv_ixm42xxx *s, inv_ixm42xxx_apex_parameters_t *apex_inputs)
246 {
247 int status = 0;
248
249 /* Default parameters at POR */
250 apex_inputs->pedo_amp_th = IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2080374_MG;
251 apex_inputs->pedo_step_cnt_th = 0x5;
252 apex_inputs->pedo_step_det_th = 0x2;
253 apex_inputs->pedo_sb_timer_th = IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_150_SAMPLES;
254 apex_inputs->pedo_hi_enrgy_th = IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_107;
255 apex_inputs->tilt_wait_time = IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_4S;
256 apex_inputs->r2w_sleep_time_out = IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_6_4S;
257 apex_inputs->r2w_mounting_matrix = IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_0;
258 apex_inputs->r2w_gest_delay = IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_96S;
259 apex_inputs->power_save_time = IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_8S;
260 apex_inputs->power_save = IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_EN;
261 apex_inputs->sensitivity_mode = IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_NORMAL;
262 apex_inputs->low_energy_amp_th = IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2684354MG;
263
264 return status;
265 }
266
267 int inv_ixm42xxx_configure_apex_parameters(struct inv_ixm42xxx *s, const inv_ixm42xxx_apex_parameters_t *apex_inputs)
268 {
269 int status = 0;
270 uint8_t data, data2[7];
271
272 /* DMP cannot be configured if it is running, hence make sure all APEX algorithms are off */
273 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
274
275 if(data & BIT_APEX_CONFIG0_PEDO_EN_MASK)
276 return INV_ERROR;
277 if(data & BIT_APEX_CONFIG0_TILT_EN_MASK)
278 return INV_ERROR;
279 if(data & BIT_APEX_CONFIG0_R2W_EN_MASK)
280 return INV_ERROR;
281
282 /* Pedometer parameters (APEX_CONFIG2, APEX_CONFIG3) */
283 data2[1] = (apex_inputs->pedo_amp_th | apex_inputs->pedo_step_cnt_th);
284 data2[2] = (apex_inputs->pedo_step_det_th | apex_inputs->pedo_sb_timer_th | apex_inputs->pedo_hi_enrgy_th);
285
286 /* Tilt parameter (APEX_CONFIG4) */
287 data2[3] = apex_inputs->tilt_wait_time;
288
289 /* Raise to wake parameter (APEX_CONFIG4, APEX_CONFIG5, APEX_CONFIG6) */
290 data2[3] |= apex_inputs->r2w_sleep_time_out;
291 data2[4] = apex_inputs->r2w_mounting_matrix;
292 data2[5] = apex_inputs->r2w_gest_delay;
293
294 /* Power Save mode parameters (APEX_CONFIG0, APEX_CONFIG1) */
295 data &= (uint8_t)~BIT_APEX_CONFIG0_DMP_POWER_SAVE_MASK;
296 data |= (uint8_t)apex_inputs->power_save;
297 data2[0] = apex_inputs->power_save_time;
298
299 /* Additionnal parameters for Pedometer in Slow Walk mode (APEX_CONFIG1, APEX_CONFIG9) */
300 data2[0] |= (uint8_t)apex_inputs->low_energy_amp_th;
301 data2[6] = apex_inputs->sensitivity_mode;
302
303 status |= inv_ixm42xxx_write_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
304
305 /* Set memory bank 4 */
306 status |= inv_ixm42xxx_set_reg_bank(s, 4);
307
308 /* Access continuous config registers (CONFIG1-CONFIG6) */
309 status |= inv_ixm42xxx_write_reg(s, MPUREG_APEX_CONFIG1_B4, 6, &data2[0]);
310 /* Spare bank sel transaction since CONFIG9 is also in bank 4 (but not contiguous) */
311 status |= inv_ixm42xxx_write_reg(s, MPUREG_APEX_CONFIG9_B4, 1, &data2[6]);
312
313 /* Set memory bank 0 */
314 status |= inv_ixm42xxx_set_reg_bank(s, 0);
315
316 return status;
317 }
318
319 int inv_ixm42xxx_get_apex_parameters(struct inv_ixm42xxx *s, inv_ixm42xxx_apex_parameters_t *apex_params)
320 {
321 int status = 0;
322 uint8_t data[6] /*in B4*/, data2 /*also in B4*/;
323
324 /* Set memory bank 4 */
325 status |= inv_ixm42xxx_set_reg_bank(s, 4);
326
327 /* Access continuous config registers (CONFIG1-CONFIG6) */
328 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_CONFIG1_B4, sizeof(data), &data[0]);
329 /* Spare bank sel transaction since CONFIG9 is also in bank 4 (but not contiguous) */
330 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_CONFIG9_B4, sizeof(data2), &data2);
331
332 /* Set memory bank 0 */
333 status |= inv_ixm42xxx_set_reg_bank(s, 0);
334
335 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_CONFIG0, 1, (uint8_t *)&apex_params->power_save);
336 apex_params->power_save &= BIT_APEX_CONFIG0_DMP_POWER_SAVE_MASK;
337
338 apex_params->pedo_amp_th = (IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_t)
339 (data[1] & BIT_APEX_CONFIG2_PEDO_AMP_TH_MASK);
340 apex_params->pedo_step_cnt_th =
341 (data[1] & BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_MASK) >> BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_POS;
342 apex_params->pedo_step_det_th =
343 (data[2] & BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_MASK) >> BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS;
344 apex_params->pedo_sb_timer_th = (IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t)
345 (data[2] & BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_MASK);
346 apex_params->pedo_hi_enrgy_th = (IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t)
347 (data[2] & BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_MASK);
348 apex_params->tilt_wait_time = (IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_t)
349 (data[3] & BIT_APEX_CONFIG4_TILT_WAIT_TIME_MASK);
350 apex_params->power_save_time = (IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t)
351 (data[0] & BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_MASK);
352 apex_params->sensitivity_mode = (IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_t)
353 (data2 & BIT_APEX_CONFIG9_SENSITIVITY_MODE_MASK);
354 apex_params->low_energy_amp_th = (IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t)
355 (data[0] & BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_MASK);
356 apex_params->r2w_sleep_time_out = (IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t)
357 (data[3] & BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_MASK);
358 apex_params->r2w_mounting_matrix = (IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t)
359 (data[4] & BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_MASK);
360 apex_params->r2w_gest_delay = (IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t)
361 (data[5] & BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_MASK);
362
363 return status;
364 }
365
366 int inv_ixm42xxx_set_apex_frequency(struct inv_ixm42xxx * s, const IXM42XXX_APEX_CONFIG0_DMP_ODR_t frequency)
367 {
368 uint8_t data;
369 int status = 0;
370 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
371 data &= (uint8_t)~BIT_APEX_CONFIG0_DMP_ODR_MASK;
372 data |= (uint8_t)frequency;
373 status |= inv_ixm42xxx_write_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
374 return status;
375 }
376
377 int inv_ixm42xxx_start_dmp(struct inv_ixm42xxx * s)
378 {
379 int status = 0;
380
381 /* On first enabling of DMP, reset internal state */
382 if(!s->dmp_is_on) {
383 /* Reset SRAM to 0's */
384 status |= inv_ixm42xxx_reset_dmp(s);
385 s->dmp_is_on = 1;
386 }
387
388 /* Initialize DMP */
389 status |= inv_ixm42xxx_resume_dmp(s);
390
391 return status;
392 }
393
394
395 int inv_ixm42xxx_enable_apex_pedometer(struct inv_ixm42xxx * s)
396 {
397 uint8_t data;
398 int status = 0;
399
400 status |= inv_ixm42xxx_start_dmp(s);
401
402 /* Enable Pedometer */
403 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
404 data |= (uint8_t)IXM42XXX_APEX_CONFIG0_PEDO_EN_EN;
405 status |= inv_ixm42xxx_write_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
406
407 return status;
408 }
409
410 int inv_ixm42xxx_disable_apex_pedometer(struct inv_ixm42xxx * s)
411 {
412 uint8_t data;
413 int status = 0;
414
415 /* Disable Pedometer */
416 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
417 data &= (uint8_t)~BIT_APEX_CONFIG0_PEDO_EN_MASK; /* == IXM42XXX_APEX_CONFIG0_PEDO_EN_DIS */
418 status |= inv_ixm42xxx_write_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
419
420 return status;
421 }
422
423 int inv_ixm42xxx_enable_apex_r2w(struct inv_ixm42xxx * s)
424 {
425 uint8_t data;
426 int status = 0;
427
428 status |= inv_ixm42xxx_start_dmp(s);
429
430 /* Enable r2w */
431 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
432 data |= (uint8_t)IXM42XXX_APEX_CONFIG0_R2W_EN_EN;
433 status |= inv_ixm42xxx_write_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
434
435 return status;
436 }
437
438 int inv_ixm42xxx_disable_apex_r2w(struct inv_ixm42xxx * s)
439 {
440 uint8_t data;
441 int status = 0;
442
443 /* Disable r2w */
444 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
445 data &= (uint8_t)~BIT_APEX_CONFIG0_R2W_EN_MASK; /* == IXM42XXX_APEX_CONFIG0_R2W_EN_DIS */
446 status |= inv_ixm42xxx_write_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
447
448 return status;
449 }
450
451
452 int inv_ixm42xxx_enable_apex_tilt(struct inv_ixm42xxx * s)
453 {
454 uint8_t data;
455 int status = 0;
456
457 status |= inv_ixm42xxx_start_dmp(s);
458
459 /* Enable Tilt */
460 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
461 data |= (uint8_t)IXM42XXX_APEX_CONFIG0_TILT_EN_EN;
462 status |= inv_ixm42xxx_write_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
463
464 return status;
465 }
466
467 int inv_ixm42xxx_disable_apex_tilt(struct inv_ixm42xxx * s)
468 {
469 uint8_t data;
470 int status = 0;
471
472 /* Disable Tilt */
473 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
474 data &= (uint8_t)~BIT_APEX_CONFIG0_TILT_EN_MASK; /* == IXM42XXX_APEX_CONFIG0_TILT_EN_DIS */
475 status |= inv_ixm42xxx_write_reg(s, MPUREG_APEX_CONFIG0, 1, &data);
476
477 return status;
478 }
479
480 int inv_ixm42xxx_get_apex_data_activity(struct inv_ixm42xxx * s, inv_ixm42xxx_apex_step_activity_t * apex_activity)
481 {
482 uint8_t data[4];
483 int status = inv_ixm42xxx_read_reg(s, MPUREG_APEX_DATA0, 4, data);
484
485 apex_activity->step_cnt = (((uint16_t)data[1]) << 8) | data[0];
486 apex_activity->step_cadence = data[2];
487 apex_activity->activity_class = data[3] & BIT_APEX_DATA3_ACTIVITY_CLASS_MASK;
488
489 return status;
490 }
491
492
493 int inv_ixm42xxx_get_tap_data(struct inv_ixm42xxx * s, inv_ixm42xxx_tap_data_t * tap_data)
494 {
495 uint8_t data[2];
496 int status = inv_ixm42xxx_read_reg(s, MPUREG_APEX_DATA4, 2, data);
497
498 tap_data->tap_num = (IXM42XXX_APEX_DATA4_TAP_NUM_t) (data[0] & BIT_APEX_DATA4_TAP_NUM_MASK);
499 tap_data->tap_axis = (IXM42XXX_APEX_DATA4_TAP_AXIS_t)(data[0] & BIT_APEX_DATA4_TAP_AXIS_MASK);
500 tap_data->tap_dir = (IXM42XXX_APEX_DATA4_TAP_DIR_t) (data[0] & BIT_APEX_DATA4_TAP_DIR_MASK);
501 tap_data->double_tap_timing = (data[1] & BIT_APEX_DATA5_DOUBLE_TAP_TIMING_MASK);
502
503 return status;
504 }
505
506
507 /*
508 * Static functions definition
509 */
510
511 static int inv_ixm42xxx_resume_dmp(struct inv_ixm42xxx * s)
512 {
513 int status = 0;
514 uint8_t data;
515 const int ref_timeout = 5000; /*50 ms*/
516 int timeout = ref_timeout;
517
518 data = IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_EN;
519 status |= inv_ixm42xxx_write_reg(s, MPUREG_SIGNAL_PATH_RESET, 1, &data);
520
521 /* Max accelero ODR is 100Hz, and DMP INIT is updated every accel ODR */
522 inv_ixm42xxx_sleep_us(10000U);
523
524 /* Wait for DMP idle */
525 do {
526 status |= inv_ixm42xxx_read_reg(s, MPUREG_APEX_DATA3, 1, &data);
527 inv_ixm42xxx_sleep_us(10U);
528 } while ((0 == (data & BIT_APEX_DATA3_DMP_IDLE_MASK)) && timeout--);
529
530 if (timeout <= 0)
531 return INV_ERROR_TIMEOUT;
532
533 return status;
534 }
535
536 static int inv_ixm42xxx_reset_dmp(struct inv_ixm42xxx * s)
537 {
538 int status = 0;
539 const int ref_timeout = 5000; /*50 ms*/
540 int timeout = ref_timeout;
541 uint8_t data;
542
543 /* Reset DMP internal memories */
544 data = IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN;
545 status |= inv_ixm42xxx_write_reg(s, MPUREG_SIGNAL_PATH_RESET, 1, &data);
546 inv_ixm42xxx_sleep_us(1000U);
547
548 /* Make sure reset procedure has finished by reading back mem_reset_en bit */
549 do {
550 status |= inv_ixm42xxx_read_reg(s, MPUREG_SIGNAL_PATH_RESET, 1, &data);
551 inv_ixm42xxx_sleep_us(10U);
552 } while ((data & BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_MASK) && timeout--);
553
554 if (timeout <= 0)
555 return INV_ERROR_TIMEOUT;
556
557 return status;
558 }
inv_ixm42xxx_tap_data::tap_dir
IXM42XXX_APEX_DATA4_TAP_DIR_t tap_dir
Definition: Ixm42xxxDriver_HL_apex.h:105
inv_ixm42xxx_enable_apex_tilt
int inv_ixm42xxx_enable_apex_tilt(struct inv_ixm42xxx *s)
Enable APEX algorithm Tilt. note : Tilt request to have the accelerometer enabled to works with accel...
Definition: Ixm42xxxDriver_HL_apex.c:452
BIT_APEX_DATA4_TAP_DIR_MASK
#define BIT_APEX_DATA4_TAP_DIR_MASK
Definition: Ixm42xxxDefs.h:464
inv_ixm42xxx_disable_apex_r2w
int inv_ixm42xxx_disable_apex_r2w(struct inv_ixm42xxx *s)
Disable APEX algorithm Raise to wake.
Definition: Ixm42xxxDriver_HL_apex.c:438
MPUREG_APEX_CONFIG9_B4
#define MPUREG_APEX_CONFIG9_B4
Definition: Ixm42xxxDefs.h:185
inv_ixm42xxx_get_apex_data_activity
int inv_ixm42xxx_get_apex_data_activity(struct inv_ixm42xxx *s, inv_ixm42xxx_apex_step_activity_t *apex_activity)
Retrieve APEX pedometer outputs and format them.
Definition: Ixm42xxxDriver_HL_apex.c:480
inv_ixm42xxx_interrupt_parameter_t
Ixm42xxx set of interrupt enable flag.
Definition: Ixm42xxxDriver_HL.h:230
MPUREG_ACCEL_WOM_X_THR_B4
#define MPUREG_ACCEL_WOM_X_THR_B4
Definition: Ixm42xxxDefs.h:186
IXM42XXX_APEX_CONFIG8_TAP_TMIN_t
IXM42XXX_APEX_CONFIG8_TAP_TMIN_t
Definition: Ixm42xxxDefs.h:1862
BIT_APEX_CONFIG8_TAP_TAVG_MASK
#define BIT_APEX_CONFIG8_TAP_TAVG_MASK
Definition: Ixm42xxxDefs.h:1847
BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_MASK
#define BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_MASK
Definition: Ixm42xxxDefs.h:1629
BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_MASK
#define BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_MASK
Definition: Ixm42xxxDefs.h:1812
inv_ixm42xxx_tap_parameters_t
Ixm42xxx TAP inputs parameters definition.
Definition: Ixm42xxxDriver_HL_apex.h:53
BIT_APEX_CONFIG9_SENSITIVITY_MODE_MASK
#define BIT_APEX_CONFIG9_SENSITIVITY_MODE_MASK
Definition: Ixm42xxxDefs.h:1878
BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_MASK
#define BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_MASK
Definition: Ixm42xxxDefs.h:1699
inv_ixm42xxx_tap_data::tap_axis
IXM42XXX_APEX_DATA4_TAP_AXIS_t tap_axis
Definition: Ixm42xxxDriver_HL_apex.h:104
BIT_APEX_CONFIG2_PEDO_AMP_TH_MASK
#define BIT_APEX_CONFIG2_PEDO_AMP_TH_MASK
Definition: Ixm42xxxDefs.h:1659
IXM42XXX_APEX_CONFIG8_TAP_TMAX_500MS
@ IXM42XXX_APEX_CONFIG8_TAP_TMAX_500MS
Definition: Ixm42xxxDefs.h:1841
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_0
@ IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_0
Definition: Ixm42xxxDefs.h:1773
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_96S
@ IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_96S
Definition: Ixm42xxxDefs.h:1797
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t
Definition: Ixm42xxxDefs.h:1794
INV_IXM42XXX_ENABLE
@ INV_IXM42XXX_ENABLE
Definition: Ixm42xxxDriver_HL.h:225
BIT_APEX_CONFIG0_R2W_EN_MASK
#define BIT_APEX_CONFIG0_R2W_EN_MASK
Definition: Ixm42xxxDefs.h:961
Ixm42xxxDriver_HL_apex.h
Ixm42xxxDefs.h
inv_ixm42xxx_disable_apex_pedometer
int inv_ixm42xxx_disable_apex_pedometer(struct inv_ixm42xxx *s)
Disable APEX algorithm Pedometer.
Definition: Ixm42xxxDriver_HL_apex.c:410
BIT_APEX_DATA3_ACTIVITY_CLASS_MASK
#define BIT_APEX_DATA3_ACTIVITY_CLASS_MASK
Definition: Ixm42xxxDefs.h:413
inv_ixm42xxx
Ixm42xxx driver states definition.
Definition: Ixm42xxxDriver_HL.h:164
MPUREG_APEX_DATA0
#define MPUREG_APEX_DATA0
Definition: Ixm42xxxDefs.h:101
inv_ixm42xxx_sleep_us
void inv_ixm42xxx_sleep_us(uint32_t us)
Hook for low-level high res system sleep() function to be implemented by upper layer ~100us resolutio...
inv_ixm42xxx_disable_apex_tilt
int inv_ixm42xxx_disable_apex_tilt(struct inv_ixm42xxx *s)
Disable APEX algorithm Tilt.
Definition: Ixm42xxxDriver_HL_apex.c:467
inv_ixm42xxx_get_tap_parameters
int inv_ixm42xxx_get_tap_parameters(struct inv_ixm42xxx *s, inv_ixm42xxx_tap_parameters_t *tap_params)
Returns current TAP parameters.
Definition: Ixm42xxxDriver_HL_apex.c:197
inv_ixm42xxx_disable_wom
int inv_ixm42xxx_disable_wom(struct inv_ixm42xxx *s)
Disable Wake On Motion. Disables WoM event generation and reconfigures interrupt to fire on Fifo wate...
Definition: Ixm42xxxDriver_HL_apex.c:88
inv_ixm42xxx_interrupt_parameter_t::INV_IXM42XXX_FIFO_THS
inv_ixm42xxx_interrupt_value INV_IXM42XXX_FIFO_THS
Definition: Ixm42xxxDriver_HL.h:233
BIT_APEX_CONFIG0_PEDO_EN_MASK
#define BIT_APEX_CONFIG0_PEDO_EN_MASK
Definition: Ixm42xxxDefs.h:951
inv_ixm42xxx_apex_parameters::pedo_step_det_th
uint8_t pedo_step_det_th
Definition: Ixm42xxxDriver_HL_apex.h:67
inv_ixm42xxx_enable_smd
int inv_ixm42xxx_enable_smd(struct inv_ixm42xxx *s)
Enable Significant Motion Detection. note : SMD requests to have the accelerometer enabled to work....
Definition: Ixm42xxxDriver_HL_apex.c:117
BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_MASK
#define BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_MASK
Definition: Ixm42xxxDefs.h:1791
IXM42XXX_SMD_CONFIG_WOM_INT_MODE_t
IXM42XXX_SMD_CONFIG_WOM_INT_MODE_t
Definition: Ixm42xxxDefs.h:1002
inv_ixm42xxx_configure_apex_parameters
int inv_ixm42xxx_configure_apex_parameters(struct inv_ixm42xxx *s, const inv_ixm42xxx_apex_parameters_t *apex_inputs)
Configures DMP parameters for APEX algorithms (pedometer, tilt). This programmable parameters will be...
Definition: Ixm42xxxDriver_HL_apex.c:267
IXM42XXX_APEX_CONFIG0_TAP_ENABLE_EN
@ IXM42XXX_APEX_CONFIG0_TAP_ENABLE_EN
Definition: Ixm42xxxDefs.h:945
inv_ixm42xxx_interrupt_value
inv_ixm42xxx_interrupt_value
Definition: Ixm42xxxDriver_HL.h:223
IXM42XXX_SMD_CONFIG_SMD_MODE_WOM
@ IXM42XXX_SMD_CONFIG_SMD_MODE_WOM
Definition: Ixm42xxxDefs.h:1025
inv_ixm42xxx_apex_parameters::power_save_time
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t power_save_time
Definition: Ixm42xxxDriver_HL_apex.h:76
inv_ixm42xxx_apex_parameters::pedo_sb_timer_th
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t pedo_sb_timer_th
Definition: Ixm42xxxDriver_HL_apex.h:69
inv_ixm42xxx_apex_parameters
Ixm42xxx APEX inputs parameters definition.
Definition: Ixm42xxxDriver_HL_apex.h:63
inv_ixm42xxx_apex_parameters::pedo_amp_th
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_t pedo_amp_th
Definition: Ixm42xxxDriver_HL_apex.h:64
inv_ixm42xxx_get_tap_data
int inv_ixm42xxx_get_tap_data(struct inv_ixm42xxx *s, inv_ixm42xxx_tap_data_t *tap_data)
Retrieve tap outputs.
Definition: Ixm42xxxDriver_HL_apex.c:493
IXM42XXX_APEX_CONFIG8_TAP_TAVG_8SAMPLE
@ IXM42XXX_APEX_CONFIG8_TAP_TAVG_8SAMPLE
Definition: Ixm42xxxDefs.h:1854
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t
Definition: Ixm42xxxDefs.h:1632
inv_ixm42xxx::wom_smd_mask
uint8_t wom_smd_mask
Definition: Ixm42xxxDriver_HL.h:207
inv_ixm42xxx_init_tap_parameters_struct
int inv_ixm42xxx_init_tap_parameters_struct(struct inv_ixm42xxx *s, inv_ixm42xxx_tap_parameters_t *tap_inputs)
Fill the TAP parameters structure with all the default parameters for TAP algorithm.
Definition: Ixm42xxxDriver_HL_apex.c:166
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_t
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_t
Definition: Ixm42xxxDefs.h:1662
inv_ixm42xxx_configure_tap_parameters
int inv_ixm42xxx_configure_tap_parameters(struct inv_ixm42xxx *s, const inv_ixm42xxx_tap_parameters_t *tap_inputs)
Configure TAP.
Definition: Ixm42xxxDriver_HL_apex.c:178
inv_ixm42xxx_apex_parameters::pedo_step_cnt_th
uint8_t pedo_step_cnt_th
Definition: Ixm42xxxDriver_HL_apex.h:65
MPUREG_APEX_CONFIG7_B4
#define MPUREG_APEX_CONFIG7_B4
Definition: Ixm42xxxDefs.h:183
IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_t
IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_t
Definition: Ixm42xxxDefs.h:1880
IXM42XXX_SMD_CONFIG_SMD_MODE_LONG
@ IXM42XXX_SMD_CONFIG_SMD_MODE_LONG
Definition: Ixm42xxxDefs.h:1023
Ixm42xxxExtFunc.h
BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_MASK
#define BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_MASK
Definition: Ixm42xxxDefs.h:1716
inv_ixm42xxx_tap_data::double_tap_timing
uint8_t double_tap_timing
Definition: Ixm42xxxDriver_HL_apex.h:106
BIT_APEX_CONFIG4_TILT_WAIT_TIME_MASK
#define BIT_APEX_CONFIG4_TILT_WAIT_TIME_MASK
Definition: Ixm42xxxDefs.h:1734
BIT_APEX_CONFIG0_DMP_POWER_SAVE_MASK
#define BIT_APEX_CONFIG0_DMP_POWER_SAVE_MASK
Definition: Ixm42xxxDefs.h:931
BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS
#define BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS
Definition: Ixm42xxxDefs.h:1811
BIT_APEX_CONFIG8_TAP_TMAX_MASK
#define BIT_APEX_CONFIG8_TAP_TMAX_MASK
Definition: Ixm42xxxDefs.h:1835
BIT_APEX_DATA5_DOUBLE_TAP_TIMING_MASK
#define BIT_APEX_DATA5_DOUBLE_TAP_TIMING_MASK
Definition: Ixm42xxxDefs.h:478
BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_MASK
#define BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_MASK
Definition: Ixm42xxxDefs.h:1747
inv_ixm42xxx_get_config_int1
int inv_ixm42xxx_get_config_int1(struct inv_ixm42xxx *s, inv_ixm42xxx_interrupt_parameter_t *interrupt_to_configure)
Retrieve interrupts configuration.
Definition: Ixm42xxxDriver_HL.c:620
inv_ixm42xxx_apex_parameters::low_energy_amp_th
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t low_energy_amp_th
Definition: Ixm42xxxDriver_HL_apex.h:88
inv_ixm42xxx_apex_parameters::tilt_wait_time
IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_t tilt_wait_time
Definition: Ixm42xxxDriver_HL_apex.h:74
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_6_4S
@ IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_6_4S
Definition: Ixm42xxxDefs.h:1755
IXM42XXX_APEX_CONFIG8_TAP_TAVG_t
IXM42XXX_APEX_CONFIG8_TAP_TAVG_t
Definition: Ixm42xxxDefs.h:1850
IXM42XXX_APEX_CONFIG0_PEDO_EN_EN
@ IXM42XXX_APEX_CONFIG0_PEDO_EN_EN
Definition: Ixm42xxxDefs.h:955
inv_ixm42xxx_interrupt_parameter_t::INV_IXM42XXX_UI_DRDY
inv_ixm42xxx_interrupt_value INV_IXM42XXX_UI_DRDY
Definition: Ixm42xxxDriver_HL.h:232
inv_ixm42xxx_start_dmp
int inv_ixm42xxx_start_dmp(struct inv_ixm42xxx *s)
Start DMP for APEX algorithms.
Definition: Ixm42xxxDriver_HL_apex.c:377
inv_ixm42xxx::dmp_is_on
uint8_t dmp_is_on
Definition: Ixm42xxxDriver_HL.h:181
IXM42XXX_APEX_CONFIG0_DMP_ODR_t
IXM42XXX_APEX_CONFIG0_DMP_ODR_t
DMP ODR selection.
Definition: Ixm42xxxDefs.h:986
inv_ixm42xxx_disable_tap
int inv_ixm42xxx_disable_tap(struct inv_ixm42xxx *s)
Disable TAP.
Definition: Ixm42xxxDriver_HL_apex.c:232
IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t
IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t
Definition: Ixm42xxxDefs.h:1821
inv_ixm42xxx_apex_parameters::pedo_hi_enrgy_th
IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t pedo_hi_enrgy_th
Definition: Ixm42xxxDriver_HL_apex.h:72
IXM42XXX_APEX_DATA4_TAP_AXIS_t
IXM42XXX_APEX_DATA4_TAP_AXIS_t
Definition: Ixm42xxxDefs.h:456
inv_ixm42xxx_apex_step_activity::step_cadence
uint8_t step_cadence
Definition: Ixm42xxxDriver_HL_apex.h:95
BIT_APEX_CONFIG0_TAP_ENABLE_MASK
#define BIT_APEX_CONFIG0_TAP_ENABLE_MASK
Definition: Ixm42xxxDefs.h:941
MPUREG_APEX_DATA3
#define MPUREG_APEX_DATA3
Definition: Ixm42xxxDefs.h:104
inv_ixm42xxx_apex_parameters::r2w_mounting_matrix
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t r2w_mounting_matrix
Definition: Ixm42xxxDriver_HL_apex.h:85
Ixm42xxxDriver_HL.h
inv_ixm42xxx_disable_smd
int inv_ixm42xxx_disable_smd(struct inv_ixm42xxx *s)
Disable Significant Motion Detection. Disables SMD event generation and disables SMD interrupt.
Definition: Ixm42xxxDriver_HL_apex.c:143
IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_25
@ IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_25
Definition: Ixm42xxxDefs.h:1823
BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_MASK
#define BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_MASK
Definition: Ixm42xxxDefs.h:517
MPUREG_APEX_DATA4
#define MPUREG_APEX_DATA4
Definition: Ixm42xxxDefs.h:105
INV_IXM42XXX_DISABLE
@ INV_IXM42XXX_DISABLE
Definition: Ixm42xxxDriver_HL.h:224
IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_4S
@ IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_4S
Definition: Ixm42xxxDefs.h:1740
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t
Definition: Ixm42xxxDefs.h:1702
IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_107
@ IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_107
Definition: Ixm42xxxDefs.h:1721
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2080374_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2080374_MG
Definition: Ixm42xxxDefs.h:1671
inv_ixm42xxx_tap_parameters_t::tmin
IXM42XXX_APEX_CONFIG8_TAP_TMIN_t tmin
Definition: Ixm42xxxDriver_HL_apex.h:58
inv_ixm42xxx::wom_enable
uint8_t wom_enable
Definition: Ixm42xxxDriver_HL.h:209
MPUREG_SMD_CONFIG
#define MPUREG_SMD_CONFIG
Definition: Ixm42xxxDefs.h:120
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t
Definition: Ixm42xxxDefs.h:1750
IXM42XXX_APEX_CONFIG7_TAP_MIN_JERK_THR_281MG_DEFAULT
#define IXM42XXX_APEX_CONFIG7_TAP_MIN_JERK_THR_281MG_DEFAULT
Definition: Ixm42xxxDefs.h:1814
inv_ixm42xxx_apex_parameters::sensitivity_mode
IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_t sensitivity_mode
Definition: Ixm42xxxDriver_HL_apex.h:80
IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_NORMAL
@ IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_NORMAL
Definition: Ixm42xxxDefs.h:1881
inv_ixm42xxx_tap_parameters_t::max_peak_tol
IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t max_peak_tol
Definition: Ixm42xxxDriver_HL_apex.h:55
inv_ixm42xxx_apex_parameters::r2w_gest_delay
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t r2w_gest_delay
Definition: Ixm42xxxDriver_HL_apex.h:86
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t
Definition: Ixm42xxxDefs.h:1607
BIT_SMD_CONFIG_SMD_MODE_MASK
#define BIT_SMD_CONFIG_SMD_MODE_MASK
Definition: Ixm42xxxDefs.h:1019
inv_ixm42xxx_tap_parameters_t::tmax
IXM42XXX_APEX_CONFIG8_TAP_TMAX_t tmax
Definition: Ixm42xxxDriver_HL_apex.h:56
MPUREG_APEX_CONFIG0
#define MPUREG_APEX_CONFIG0
Definition: Ixm42xxxDefs.h:119
BIT_APEX_DATA4_TAP_AXIS_MASK
#define BIT_APEX_DATA4_TAP_AXIS_MASK
Definition: Ixm42xxxDefs.h:454
inv_ixm42xxx_apex_parameters::power_save
IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_t power_save
Definition: Ixm42xxxDriver_HL_apex.h:77
BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_MASK
#define BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_MASK
Definition: Ixm42xxxDefs.h:1818
IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_EN
@ IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_EN
Definition: Ixm42xxxDefs.h:935
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t
Definition: Ixm42xxxDefs.h:1772
BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_MASK
#define BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_MASK
Definition: Ixm42xxxDefs.h:1684
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2684354MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2684354MG
Definition: Ixm42xxxDefs.h:1643
IXM42XXX_APEX_CONFIG0_TILT_EN_EN
@ IXM42XXX_APEX_CONFIG0_TILT_EN_EN
Definition: Ixm42xxxDefs.h:975
IXM42XXX_APEX_CONFIG8_TAP_TMAX_t
IXM42XXX_APEX_CONFIG8_TAP_TMAX_t
Definition: Ixm42xxxDefs.h:1838
inv_ixm42xxx_get_config_ibi
int inv_ixm42xxx_get_config_ibi(struct inv_ixm42xxx *s, inv_ixm42xxx_interrupt_parameter_t *interrupt_to_configure)
Retrieve interrupts configuration.
Definition: Ixm42xxxDriver_HL.c:590
inv_ixm42xxx_apex_parameters::r2w_sleep_time_out
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t r2w_sleep_time_out
Definition: Ixm42xxxDriver_HL_apex.h:84
inv_ixm42xxx_enable_apex_pedometer
int inv_ixm42xxx_enable_apex_pedometer(struct inv_ixm42xxx *s)
Enable APEX algorithm Pedometer. note : Pedometer request to have the accelerometer enabled to works ...
Definition: Ixm42xxxDriver_HL_apex.c:395
inv_ixm42xxx_apex_step_activity::step_cnt
uint16_t step_cnt
Definition: Ixm42xxxDriver_HL_apex.h:94
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_150_SAMPLES
@ IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_150_SAMPLES
Definition: Ixm42xxxDefs.h:1707
inv_ixm42xxx_init_apex_parameters_struct
int inv_ixm42xxx_init_apex_parameters_struct(struct inv_ixm42xxx *s, inv_ixm42xxx_apex_parameters_t *apex_inputs)
Fill the APEX parameters structure with all the default parameters for APEX algorithms (pedometer,...
Definition: Ixm42xxxDriver_HL_apex.c:245
IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_EN
@ IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_EN
Definition: Ixm42xxxDefs.h:511
inv_ixm42xxx_write_reg
int inv_ixm42xxx_write_reg(struct inv_ixm42xxx *s, uint8_t reg, uint32_t len, const uint8_t *buf)
Writes data to a register on Ixm42xxx.
Definition: Ixm42xxxTransport.c:86
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_8S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_8S
Definition: Ixm42xxxDefs.h:1610
inv_ixm42xxx_enable_tap
int inv_ixm42xxx_enable_tap(struct inv_ixm42xxx *s)
Enable TAP. note : TAP requests to have the accelerometer enabled to work. To have good performance,...
Definition: Ixm42xxxDriver_HL_apex.c:219
BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_MASK
#define BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_MASK
Definition: Ixm42xxxDefs.h:1604
MPUREG_SIGNAL_PATH_RESET
#define MPUREG_SIGNAL_PATH_RESET
Definition: Ixm42xxxDefs.h:109
BIT_APEX_CONFIG0_DMP_ODR_MASK
#define BIT_APEX_CONFIG0_DMP_ODR_MASK
Definition: Ixm42xxxDefs.h:981
IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_t
IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_t
Definition: Ixm42xxxDefs.h:1737
inv_ixm42xxx_tap_parameters_t::min_jerk_thr
uint8_t min_jerk_thr
Definition: Ixm42xxxDriver_HL_apex.h:54
BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_MASK
#define BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_MASK
Definition: Ixm42xxxDefs.h:1769
BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS
#define BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS
Definition: Ixm42xxxDefs.h:1693
inv_ixm42xxx_tap_parameters_t::tavg
IXM42XXX_APEX_CONFIG8_TAP_TAVG_t tavg
Definition: Ixm42xxxDriver_HL_apex.h:57
IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t
IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t
Definition: Ixm42xxxDefs.h:1719
inv_ixm42xxx_set_reg_bank
int inv_ixm42xxx_set_reg_bank(struct inv_ixm42xxx *s, uint8_t bank)
Set register bank index.
Definition: Ixm42xxxDriver_HL.c:35
inv_ixm42xxx_tap_data
TAP outputs.
Definition: Ixm42xxxDriver_HL_apex.h:102
IXM42XXX_SMD_CONFIG_SMD_MODE_SHORT
@ IXM42XXX_SMD_CONFIG_SMD_MODE_SHORT
Definition: Ixm42xxxDefs.h:1024
BIT_APEX_CONFIG8_TAP_TMIN_MASK
#define BIT_APEX_CONFIG8_TAP_TMIN_MASK
Definition: Ixm42xxxDefs.h:1859
IXM42XXX_SMD_CONFIG_WOM_MODE_t
IXM42XXX_SMD_CONFIG_WOM_MODE_t
Definition: Ixm42xxxDefs.h:1012
inv_ixm42xxx_read_reg
int inv_ixm42xxx_read_reg(struct inv_ixm42xxx *s, uint8_t reg, uint32_t len, uint8_t *buf)
Reads data from a register on Ixm42xxx.
Definition: Ixm42xxxTransport.c:54
IXM42XXX_APEX_CONFIG8_TAP_TMIN_171MS
@ IXM42XXX_APEX_CONFIG8_TAP_TMIN_171MS
Definition: Ixm42xxxDefs.h:1866
IXM42XXX_APEX_DATA4_TAP_DIR_t
IXM42XXX_APEX_DATA4_TAP_DIR_t
Definition: Ixm42xxxDefs.h:466
BIT_APEX_DATA3_DMP_IDLE_MASK
#define BIT_APEX_DATA3_DMP_IDLE_MASK
Definition: Ixm42xxxDefs.h:424
IXM42XXX_APEX_DATA4_TAP_NUM_t
IXM42XXX_APEX_DATA4_TAP_NUM_t
Definition: Ixm42xxxDefs.h:447
BIT_APEX_CONFIG0_TILT_EN_MASK
#define BIT_APEX_CONFIG0_TILT_EN_MASK
Definition: Ixm42xxxDefs.h:971
BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_MASK
#define BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_MASK
Definition: Ixm42xxxDefs.h:1694
IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN
@ IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN
Definition: Ixm42xxxDefs.h:521
inv_ixm42xxx_tap_data::tap_num
IXM42XXX_APEX_DATA4_TAP_NUM_t tap_num
Definition: Ixm42xxxDriver_HL_apex.h:103
inv_ixm42xxx_apex_step_activity::activity_class
uint8_t activity_class
Definition: Ixm42xxxDriver_HL_apex.h:97
MPUREG_APEX_CONFIG1_B4
#define MPUREG_APEX_CONFIG1_B4
Definition: Ixm42xxxDefs.h:177
IXM42XXX_APEX_CONFIG0_R2W_EN_EN
@ IXM42XXX_APEX_CONFIG0_R2W_EN_EN
Definition: Ixm42xxxDefs.h:965
inv_ixm42xxx_configure_smd_wom
int inv_ixm42xxx_configure_smd_wom(struct inv_ixm42xxx *s, const uint8_t x_th, const uint8_t y_th, const uint8_t z_th, IXM42XXX_SMD_CONFIG_WOM_INT_MODE_t wom_int, IXM42XXX_SMD_CONFIG_WOM_MODE_t wom_mode)
Configure Wake On Motion and SMD thresholds.
Definition: Ixm42xxxDriver_HL_apex.c:32
BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_POS
#define BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_POS
Definition: Ixm42xxxDefs.h:1683
IXM42XXX_SMD_CONFIG_SMD_MODE_DISABLED
@ IXM42XXX_SMD_CONFIG_SMD_MODE_DISABLED
Definition: Ixm42xxxDefs.h:1026
inv_ixm42xxx_set_config_int1
int inv_ixm42xxx_set_config_int1(struct inv_ixm42xxx *s, inv_ixm42xxx_interrupt_parameter_t *interrupt_to_configure)
Configure which interrupt source can trigger INT1.
Definition: Ixm42xxxDriver_HL.c:730
BIT_APEX_DATA4_TAP_NUM_MASK
#define BIT_APEX_DATA4_TAP_NUM_MASK
Definition: Ixm42xxxDefs.h:445
inv_ixm42xxx_set_apex_frequency
int inv_ixm42xxx_set_apex_frequency(struct inv_ixm42xxx *s, const IXM42XXX_APEX_CONFIG0_DMP_ODR_t frequency)
Configure DMP Output Data Rate for APEX algorithms (pedometer, tilt)
Definition: Ixm42xxxDriver_HL_apex.c:366
inv_ixm42xxx_enable_apex_r2w
int inv_ixm42xxx_enable_apex_r2w(struct inv_ixm42xxx *s)
Enable APEX algorithm Raise to wake. note : Raise to wake request to have the accelerometer enabled t...
Definition: Ixm42xxxDriver_HL_apex.c:423
inv_ixm42xxx_enable_wom
int inv_ixm42xxx_enable_wom(struct inv_ixm42xxx *s)
Enable Wake On Motion. note : WoM requests to have the accelerometer enabled to work....
Definition: Ixm42xxxDriver_HL_apex.c:54
inv_ixm42xxx_get_apex_parameters
int inv_ixm42xxx_get_apex_parameters(struct inv_ixm42xxx *s, inv_ixm42xxx_apex_parameters_t *apex_params)
Returns current DMP parameters for APEX algorithms (pedometer, tilt).
Definition: Ixm42xxxDriver_HL_apex.c:319
inv_ixm42xxx_set_config_ibi
int inv_ixm42xxx_set_config_ibi(struct inv_ixm42xxx *s, inv_ixm42xxx_interrupt_parameter_t *interrupt_to_configure)
Configure which interrupt source can trigger ibi interruptions.
Definition: Ixm42xxxDriver_HL.c:686
inv_ixm42xxx_apex_step_activity
APEX pedometer outputs.
Definition: Ixm42xxxDriver_HL_apex.h:93