| eMD IIM4265x Driver API 1.0.0

Data Structures | Macros | Enumerations
Ixm42xxxDefs.h File Reference
`#include <stdint.h>`
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## Data Structures
union | fifo_header_t

## Macros
#define | ICM40608_WHOAMI 0x39
#define | ICM42600_WHOAMI 0x40
#define | ICM42602_WHOAMI 0x41
#define | ICM42605_WHOAMI 0x42
#define | ICM42622_WHOAMI 0x46
#define | ICM42686_WHOAMI 0x44
#define | ICM42688_WHOAMI 0x47
#define | ICM42608_WHOAMI 0x48
#define | IIM42652_WHOAMI 0x6F
#define | MPUREG_DEVICE_CONFIG 0x11
#define | MPUREG_CHIP_CONFIG MPUREG_DEVICE_CONFIG
#define | MPUREG_DRIVE_CONFIG 0x13
#define | MPUREG_INT_CONFIG 0x14
#define | MPUREG_FIFO_CONFIG 0x16
#define | MPUREG_TEMP_DATA0_UI 0x1D
#define | MPUREG_ACCEL_DATA_X0_UI 0x1F
#define | MPUREG_GYRO_DATA_X0_UI 0x25
#define | MPUREG_TMST_FSYNCH 0x2B
#define | MPUREG_TMST_FSYNC1 MPUREG_TMST_FSYNCH
#define | MPUREG_INT_STATUS 0x2D
#define | MPUREG_FIFO_COUNTH 0x2E
#define | MPUREG_FIFO_BYTE_COUNT1 MPUREG_FIFO_COUNTH
#define | MPUREG_FIFO_COUNTL 0x2F
#define | MPUREG_FIFO_BYTE_COUNT2 MPUREG_FIFO_COUNTL
#define | MPUREG_FIFO_DATA 0x30
#define | MPUREG_APEX_DATA0 0x31
#define | MPUREG_APEX_DATA1 0x32
#define | MPUREG_APEX_DATA2 0x33
#define | MPUREG_APEX_DATA3 0x34
#define | MPUREG_APEX_DATA4 0x35
#define | MPUREG_APEX_DATA5 0x36
#define | MPUREG_INT_STATUS2 0x37
#define | MPUREG_INT_STATUS3 0x38
#define | MPUREG_SIGNAL_PATH_RESET 0x4B
#define | MPUREG_INTF_CONFIG0 0x4C
#define | MPUREG_INTF_CONFIG1 0x4D
#define | MPUREG_PWR_MGMT_0 0x4E
#define | MPUREG_GYRO_CONFIG0 0x4F
#define | MPUREG_ACCEL_CONFIG0 0x50
#define | MPUREG_GYRO_CONFIG1 0x51
#define | MPUREG_ACCEL_GYRO_CONFIG0 0x52
#define | MPUREG_ACCEL_CONFIG1 0x53
#define | MPUREG_TMST_CONFIG 0x54
#define | MPUREG_APEX_CONFIG0 0x56
#define | MPUREG_SMD_CONFIG 0x57
#define | MPUREG_FIFO_CONFIG1 0x5F
#define | MPUREG_FIFO_CONFIG2 0x60
#define | MPUREG_FSYNC_CONFIG 0x62
#define | MPUREG_INT_CONFIG0 0x63
#define | MPUREG_INT_CONFIG1 0x64
#define | MPUREG_INT_SOURCE0 0x65
#define | MPUREG_INT_SOURCE1 0x66
#define | MPUREG_INT_SOURCE2 0x67
#define | MPUREG_INT_SOURCE3 0x68
#define | MPUREG_INT_SOURCE4 0x69
#define | MPUREG_INT_SOURCE5 0x6A
#define | MPUREG_FIFO_LOST_PKT0 0x6C
#define | MPUREG_SELF_TEST_CONFIG 0x70
#define | MPUREG_WHO_AM_I 0x75
#define | MPUREG_REG_BANK_SEL 0x76
#define | MPUREG_GYRO_CONFIG_STATIC2_B1 0x0B
#define | MPUREG_GYRO_CONFIG_STATIC3_B1 0x0C
#define | MPUREG_GYRO_CONFIG_STATIC4_B1 0x0D
#define | MPUREG_GYRO_CONFIG_STATIC5_B1 0x0E
#define | MPUREG_XG_ST_DATA_B1 0x5F
#define | MPUREG_YG_ST_DATA_B1 0x60
#define | MPUREG_ZG_ST_DATA_B1 0x61
#define | MPUREG_TMST_VAL0_B1 0x62
#define | MPUREG_INTF_CONFIG4_B1 0x7A
#define | MPUREG_INTF_CONFIG5_B1 0x7B
#define | MPUREG_INTF_CONFIG6_B1 0x7C
#define | MPUREG_ACCEL_CONFIG_STATIC2_B2 0x03
#define | MPUREG_ACCEL_CONFIG_STATIC3_B2 0x04
#define | MPUREG_ACCEL_CONFIG_STATIC4_B2 0x05
#define | MPUREG_ACCEL_CONFIG_STATIC0_B2 0x39
#define | MPUREG_XA_ST_DATA_B2 0x3B
#define | MPUREG_YA_ST_DATA_B2 0x3C
#define | MPUREG_ZA_ST_DATA_B2 0x3D
#define | MPUREG_OIS1_CONFIG1_B2 0x44
#define | MPUREG_OIS1_CONFIG2_B2 0x45
#define | MPUREG_OIS1_CONFIG3_B2 0x46
#define | MPUREG_ACCEL_DATA_X0_OIS1_B2 0x49
#define | MPUREG_GYRO_DATA_X0_OIS1_B2 0x4F
#define | MPUREG_INT_STATUS_OIS1_B2 0x57
#define | MPUREG_OIS2_CONFIG1_B2 0x59
#define | MPUREG_OIS2_CONFIG2_B2 0x5A
#define | MPUREG_OIS2_CONFIG3_B2 0x5B
#define | MPUREG_ACCEL_DATA_X0_OIS2_B2 0x5E
#define | MPUREG_GYRO_DATA_X0_OIS2_B2 0x64
#define | MPUREG_INT_STATUS_OIS2_B2 0x6C
#define | MPUREG_APEX_CONFIG1_B4 0x40
#define | MPUREG_APEX_CONFIG2_B4 0x41
#define | MPUREG_APEX_CONFIG3_B4 0x42
#define | MPUREG_APEX_CONFIG4_B4 0x43
#define | MPUREG_APEX_CONFIG5_B4 0x44
#define | MPUREG_APEX_CONFIG6_B4 0x45
#define | MPUREG_APEX_CONFIG7_B4 0x46
#define | MPUREG_APEX_CONFIG8_B4 0x47
#define | MPUREG_APEX_CONFIG9_B4 0x48
#define | MPUREG_ACCEL_WOM_X_THR_B4 0x4A
#define | MPUREG_ACCEL_WOM_Y_THR_B4 0x4B
#define | MPUREG_ACCEL_WOM_Z_THR_B4 0x4C
#define | MPUREG_INT_SOURCE6_B4 0x4D
#define | MPUREG_INT_SOURCE7_B4 0x4E
#define | MPUREG_INT_SOURCE8_B4 0x4F
#define | MPUREG_INT_SOURCE9_B4 0x50
#define | MPUREG_INT_SOURCE10_B4 0x51
#define | MPUREG_OFFSET_USER_0_B4 0x77
#define | MPUREG_OFFSET_USER_1_B4 0x78
#define | MPUREG_OFFSET_USER_2_B4 0x79
#define | MPUREG_OFFSET_USER_3_B4 0x7A
#define | MPUREG_OFFSET_USER_4_B4 0x7B
#define | MPUREG_OFFSET_USER_5_B4 0x7C
#define | MPUREG_OFFSET_USER_6_B4 0x7D
#define | MPUREG_OFFSET_USER_7_B4 0x7E
#define | MPUREG_OFFSET_USER_8_B4 0x7F
#define | ACCEL_DATA_SIZE 6
#define | GYRO_DATA_SIZE 6
#define | TEMP_DATA_SIZE 2
#define | FIFO_HEADER_SIZE 1
#define | FIFO_ACCEL_DATA_SIZE ACCEL_DATA_SIZE
#define | FIFO_GYRO_DATA_SIZE GYRO_DATA_SIZE
#define | FIFO_TEMP_DATA_SIZE 1
#define | FIFO_TS_FSYNC_SIZE 2
#define | FIFO_TEMP_HIGH_RES_SIZE 1
#define | FIFO_ACCEL_GYRO_HIGH_RES_SIZE 3
#define | FIFO_16BYTES_PACKET_SIZE (FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + FIFO_TS_FSYNC_SIZE)
#define | FIFO_20BYTES_PACKET_SIZE
#define | FIFO_HEADER_ODR_ACCEL 0x01
#define | FIFO_HEADER_ODR_GYRO 0x02
#define | FIFO_HEADER_FSYNC 0x04
#define | FIFO_HEADER_TMST 0x08
#define | FIFO_HEADER_HEADER_20 0x10
#define | FIFO_HEADER_GYRO 0x20
#define | FIFO_HEADER_ACC 0x40
#define | FIFO_HEADER_MSG 0x80
#define | INVALID_VALUE_FIFO ((int16_t)0x8000)
#define | INVALID_VALUE_FIFO_1B ((int8_t)0x80)
#define | I3C_IBI_PAYLOAD_ALL 0xFF
#define | I3C_IBI_PAYLOAD_TIMEC 0x80
#define | I3C_IBI_PAYLOAD_CAT_MISC 0x40
#define | I3C_IBI_PAYLOAD_CAT_ERROR 0x20
#define | I3C_IBI_PAYLOAD_CAT_APEX2 0x10
#define | I3C_IBI_PAYLOAD_CAT_APEX1 0x08
#define | I3C_IBI_PAYLOAD_CAT_OIS1_DRDY 0x04
#define | I3C_IBI_PAYLOAD_CAT_FIFO 0x02
#define | I3C_IBI_PAYLOAD_CAT_UI_DRDY 0x01
#define | BIT_DEVICE_CONFIG_SPI_MODE_POS 4
#define | BIT_DEVICE_CONFIG_SPI_MODE_MASK (0x1 << BIT_DEVICE_CONFIG_SPI_MODE_POS)
#define | BIT_CHIP_CONFIG_SPI_MODE_MASK BIT_DEVICE_CONFIG_SPI_MODE_MASK
#define | BIT_CHIP_CONFIG_SPI_MODE_POS BIT_DEVICE_CONFIG_SPI_MODE_POS
#define | BIT_DEVICE_CONFIG_RESET_POS 0
#define | BIT_DEVICE_CONFIG_RESET_MASK 0x01
#define | BIT_CHIP_CONFIG_RESET_MASK BIT_DEVICE_CONFIG_RESET_MASK
#define | BIT_CHIP_CONFIG_RESET_POS BIT_DEVICE_CONFIG_RESET_POS
#define | BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS 4
#define | BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS)
#define | BIT_INT_CONFIG_INT2_POLARITY_POS 3
#define | BIT_INT_CONFIG_INT2_POLARITY_MASK (0x01 << BIT_INT_CONFIG_INT2_POLARITY_POS)
#define | BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS 1
#define | BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS)
#define | BIT_INT_CONFIG_INT1_POLARITY_POS 0
#define | BIT_INT_CONFIG_INT1_POLARITY_MASK 0x01
#define | BIT_FIFO_CONFIG_MODE_POS 6
#define | BIT_FIFO_CONFIG_MODE_MASK (0x03 << BIT_FIFO_CONFIG_MODE_POS)
#define | IXM42XXX_FIFO_CONFIG_MODE_SNAPSHOT = IXM42XXX_FIFO_CONFIG_MODE_STOP_ON_FULL;
#define | BIT_INT_STATUS_UI_FSYNC 0x40
#define | BIT_INT_STATUS_PLL_RDY 0x20
#define | BIT_INT_STATUS_RESET_DONE 0x10
#define | BIT_INT_STATUS_DRDY 0x08
#define | BIT_INT_STATUS_FIFO_THS 0x04
#define | BIT_INT_STATUS_FIFO_FULL 0x02
#define | BIT_INT_STATUS_AGC_RDY 0x01
#define | BIT_APEX_DATA3_ACTIVITY_CLASS_POS 0
#define | BIT_APEX_DATA3_ACTIVITY_CLASS_MASK 0x03
#define | BIT_APEX_DATA3_DMP_IDLE_POS 2
#define | BIT_APEX_DATA3_DMP_IDLE_MASK (0x01 << BIT_APEX_DATA3_DMP_IDLE_POS)
#define | BIT_APEX_DATA4_TAP_NUM_POS 3
#define | BIT_APEX_DATA4_TAP_NUM_MASK (0x03 << BIT_APEX_DATA4_TAP_NUM_POS)
#define | BIT_APEX_DATA4_TAP_AXIS_POS 1
#define | BIT_APEX_DATA4_TAP_AXIS_MASK (0x03 << BIT_APEX_DATA4_TAP_AXIS_POS)
#define | BIT_APEX_DATA4_TAP_DIR_POS 0
#define | BIT_APEX_DATA4_TAP_DIR_MASK 0x01
#define | BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS 0
#define | BIT_APEX_DATA5_DOUBLE_TAP_TIMING_MASK (0x3F << BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS)
#define | BIT_INT_STATUS2_SMD_INT 0x08
#define | BIT_INT_STATUS2_WOM_Z_INT 0x04
#define | BIT_INT_STATUS2_WOM_Y_INT 0x02
#define | BIT_INT_STATUS2_WOM_X_INT 0x01
#define | BIT_INT_STATUS3_STEP_DET 0x20
#define | BIT_INT_STATUS3_STEP_CNT_OVFL 0x10
#define | BIT_INT_STATUS3_TILT_DET 0x08
#define | BIT_INT_STATUS3_WAKE_DET 0x04
#define | BIT_INT_STATUS3_SLEEP_DET 0x02
#define | BIT_INT_STATUS3_TAP_DET 0x01
#define | BIT_SIGNAL_PATH_RESET_DMP_INIT_POS 6
#define | BIT_SIGNAL_PATH_RESET_DMP_INIT_MASK (0x01 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS)
#define | BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS 5
#define | BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_MASK (0x01 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS)
#define | BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS 2
#define | BIT_SIGNAL_PATH_RESET_TMST_STROBE_MASK (0x01 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS)
#define | BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS 1
#define | BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_MASK (0x01 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS)
#define | BIT_FIFO_SREG_INVALID_IND_POS 7
#define | BIT_FIFO_SREG_INVALID_IND_MASK (0x01 << BIT_FIFO_SREG_INVALID_IND_POS)
#define | BIT_FIFO_COUNT_REC_POS 6
#define | BIT_FIFO_COUNT_REC_MASK (0x01 << BIT_FIFO_COUNT_REC_POS)
#define | BIT_FIFO_COUNT_ENDIAN_POS 5
#define | BIT_FIFO_COUNT_ENDIAN_MASK (0x01 << BIT_FIFO_COUNT_ENDIAN_POS)
#define | BIT_DATA_ENDIAN_POS 4
#define | BIT_DATA_ENDIAN_MASK (0x01 << BIT_DATA_ENDIAN_POS)
#define | BIT_SPI_MODE_OIS2_POS 3
#define | BIT_SPI_MODE_OIS2_MASK (0x01 << BIT_SPI_MODE_OIS2_POS)
#define | BIT_SPI_MODE_OIS1_POS 2
#define | BIT_SPI_MODE_OIS1_MASK (0x01 << BIT_SPI_MODE_OIS1_POS)
#define | BIT_ACCEL_LP_CLK_SEL_POS 3
#define | BIT_ACCEL_LP_CLK_SEL_MASK (0x01 << BIT_ACCEL_LP_CLK_SEL_POS)
#define | BIT_RTC_MODE_POS 2
#define | BIT_RTC_MODE_MASK (0x01 << BIT_RTC_MODE_POS)
#define | BIT_PWR_MGMT_0_TEMP_POS 5
#define | BIT_PWR_MGMT_0_TEMP_MASK (0x01 << BIT_PWR_MGMT_0_TEMP_POS)
#define | BIT_PWR_MGMT_0_IDLE_POS 4
#define | BIT_PWR_MGMT_0_IDLE_MASK (0x01 << BIT_PWR_MGMT_0_IDLE_POS)
#define | BIT_PWR_MGMT_0_GYRO_MODE_POS 2
#define | BIT_PWR_MGMT_0_GYRO_MODE_MASK (0x03 << BIT_PWR_MGMT_0_GYRO_MODE_POS)
#define | BIT_PWR_MGMT_0_ACCEL_MODE_POS 0
#define | BIT_PWR_MGMT_0_ACCEL_MODE_MASK 0x03
#define | BIT_GYRO_CONFIG0_FS_SEL_POS 5
#define | BIT_GYRO_CONFIG0_FS_SEL_MASK (7 << BIT_GYRO_CONFIG0_FS_SEL_POS)
#define | BIT_GYRO_CONFIG0_ODR_POS 0
#define | BIT_GYRO_CONFIG0_ODR_MASK 0x0F
#define | BIT_ACCEL_CONFIG0_FS_SEL_POS 5
#define | BIT_ACCEL_CONFIG0_FS_SEL_MASK (0x7 << BIT_ACCEL_CONFIG0_FS_SEL_POS)
#define | BIT_ACCEL_CONFIG0_ODR_POS 0
#define | BIT_ACCEL_CONFIG0_ODR_MASK 0x0F
#define | BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS 5
#define | BIT_GYRO_CONFIG1_TEMP_FILT_BW_MASK (0x7 << BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS)
#define | BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS 2
#define | BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_MASK (0x3 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS)
#define | BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_POS 0
#define | BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_MASK 0x3
#define | BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS 4
#define | BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_MASK (0xF << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS)
#define | BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_POS 0
#define | BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_MASK 0x0F
#define | BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS 3
#define | BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS)
#define | BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS 1
#define | BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS)
#define | BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS 4
#define | BIT_TMST_CONFIG_TMST_TO_REGS_EN_MASK (0x1 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS)
#define | BIT_TMST_CONFIG_RESOL_POS 3
#define | BIT_TMST_CONFIG_RESOL_MASK (0x1 << BIT_TMST_CONFIG_RESOL_POS)
#define | BIT_TMST_CONFIG_TMST_FSYNC_POS 1
#define | BIT_TMST_CONFIG_TMST_FSYNC_MASK (0x1 << BIT_TMST_CONFIG_TMST_FSYNC_POS)
#define | BIT_TMST_CONFIG_TMST_EN_POS 0
#define | BIT_TMST_CONFIG_TMST_EN_MASK 0x1
#define | BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS 7
#define | BIT_APEX_CONFIG0_DMP_POWER_SAVE_MASK (0x1 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS)
#define | BIT_APEX_CONFIG0_TAP_ENABLE_POS 6
#define | BIT_APEX_CONFIG0_TAP_ENABLE_MASK (0x1 << BIT_APEX_CONFIG0_TAP_ENABLE_POS)
#define | BIT_APEX_CONFIG0_PEDO_EN_POS 5
#define | BIT_APEX_CONFIG0_PEDO_EN_MASK (0x1 << BIT_APEX_CONFIG0_PEDO_EN_POS)
#define | BIT_APEX_CONFIG0_R2W_EN_POS 3
#define | BIT_APEX_CONFIG0_R2W_EN_MASK (0x1 << BIT_APEX_CONFIG0_R2W_EN_POS)
#define | BIT_APEX_CONFIG0_TILT_EN_POS 4
#define | BIT_APEX_CONFIG0_TILT_EN_MASK (0x1 << BIT_APEX_CONFIG0_TILT_EN_POS)
#define | BIT_APEX_CONFIG0_DMP_ODR_POS 0
#define | BIT_APEX_CONFIG0_DMP_ODR_MASK (0x3 << BIT_APEX_CONFIG0_DMP_ODR_POS)
#define | BIT_SMD_CONFIG_WOM_INT_MODE_POS 3
#define | BIT_SMD_CONFIG_WOM_INT_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_INT_MODE_POS)
#define | BIT_SMD_CONFIG_WOM_MODE_POS 2
#define | BIT_SMD_CONFIG_WOM_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_MODE_POS)
#define | BIT_SMD_CONFIG_SMD_MODE_POS 0
#define | BIT_SMD_CONFIG_SMD_MODE_MASK 0x3
#define | BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS 6
#define | BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_MASK (0x1 << BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS)
#define | BIT_FIFO_CONFIG1_WM_GT_TH_POS 5
#define | BIT_FIFO_CONFIG1_WM_GT_TH_MASK (0x1 << BIT_FIFO_CONFIG1_WM_GT_TH_POS)
#define | BIT_FIFO_CONFIG1_HIRES_POS 4
#define | BIT_FIFO_CONFIG1_HIRES_MASK (0x1 << BIT_FIFO_CONFIG1_HIRES_POS)
#define | BIT_FIFO_CONFIG1_TMST_FSYNC_POS 3
#define | BIT_FIFO_CONFIG1_TMST_FSYNC_MASK (0x1 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS)
#define | BIT_FIFO_CONFIG1_TEMP_POS 2
#define | BIT_FIFO_CONFIG1_TEMP_MASK (0x1 << BIT_FIFO_CONFIG1_TEMP_POS)
#define | BIT_FIFO_CONFIG1_GYRO_POS 1
#define | BIT_FIFO_CONFIG1_GYRO_MASK (0x1 << BIT_FIFO_CONFIG1_GYRO_POS)
#define | BIT_FIFO_CONFIG1_ACCEL_POS 0
#define | BIT_FIFO_CONFIG1_ACCEL_MASK 0x1
#define | BIT_FSYNC_CONFIG_UI_SEL_POS 4
#define | BIT_FSYNC_CONFIG_UI_SEL_MASK (0x7 << BIT_FSYNC_CONFIG_UI_SEL_POS)
#define | BIT_INT_CONFIG1_ASY_RST_POS 4
#define | BIT_INT_CONFIG1_ASY_RST_MASK (0x1 << BIT_INT_CONFIG1_ASY_RST_POS)
#define | BIT_INT_UI_FSYNC_INT_EN_POS 6
#define | BIT_INT_PLL_RDY_INT_EN_POS 5
#define | BIT_INT_RESET_DONE_INT_EN_POS 4
#define | BIT_INT_UI_DRDY_INT_EN_POS 3
#define | BIT_INT_FIFO_THS_INT_EN_POS 2
#define | BIT_INT_FIFO_FULL_INT_EN_POS 1
#define | BIT_INT_UI_AGC_RDY_INT_EN_POS 0
#define | BIT_INT_SOURCE0_UI_FSYNC_INT1_EN 0x40
#define | BIT_INT_SOURCE0_PLL_RDY_INT1_EN 0x20
#define | BIT_INT_SOURCE0_RESET_DONE_INT1_EN 0x10
#define | BIT_INT_SOURCE0_UI_DRDY_INT1_EN 0x08
#define | BIT_INT_SOURCE0_FIFO_THS_INT1_EN 0x04
#define | BIT_INT_SOURCE0_FIFO_FULL_INT1_EN 0x02
#define | BIT_INT_SOURCE0_UI_AGC_RDY_INT1_EN 0x01
#define | BIT_INT_SMD_INT_EN_POS 3
#define | BIT_INT_WOM_Z_INT_EN_POS 2
#define | BIT_INT_WOM_Y_INT_EN_POS 1
#define | BIT_INT_WOM_X_INT_EN_POS 0
#define | BIT_INT_SOURCE1_SMD_INT1_EN 0x08
#define | BIT_INT_SOURCE1_WOM_Z_INT1_EN 0x04
#define | BIT_INT_SOURCE1_WOM_Y_INT1_EN 0x02
#define | BIT_INT_SOURCE1_WOM_X_INT1_EN 0x01
#define | BIT_INT_SOURCE2_OIS2_AGC_RDY_INT1_EN 0x20
#define | BIT_INT_SOURCE2_OIS2_FSYNC_INT1_EN 0x10
#define | BIT_INT_SOURCE2_OIS2_DRDY_INT1_EN 0x08
#define | BIT_INT_SOURCE2_OIS1_AGC_RDY_INT1_EN 0x04
#define | BIT_INT_SOURCE2_OIS1_FSYNC_INT1_EN 0x02
#define | BIT_INT_SOURCE2_OIS1_DRDY_INT1_EN 0x01
#define | BIT_INT_SOURCE3_UI_FSYNC_INT2_EN 0x40
#define | BIT_INT_SOURCE3_PLL_RDY_INT2_EN 0x20
#define | BIT_INT_SOURCE3_RESET_DONE_INT2_EN 0x10
#define | BIT_INT_SOURCE3_UI_DRDY_INT2_EN 0x08
#define | BIT_INT_SOURCE3_FIFO_THS_INT2_EN 0x04
#define | BIT_INT_SOURCE3_FIFO_FULL_INT2_EN 0x02
#define | BIT_INT_SOURCE3_UI_AGC_RDY_INT2_EN 0x01
#define | BIT_INT_SOURCE4_SMD_INT2_EN 0x08
#define | BIT_INT_SOURCE4_WOM_Z_INT2_EN 0x04
#define | BIT_INT_SOURCE4_WOM_Y_INT2_EN 0x02
#define | BIT_INT_SOURCE4_WOM_X_INT2_EN 0x01
#define | BIT_INT_SOURCE5_OIS2_AGC_RDY_INT2_EN 0x20
#define | BIT_INT_SOURCE5_OIS2_FSYNC_INT2_EN 0x10
#define | BIT_INT_SOURCE5_OIS2_DRDY_INT2_EN 0x08
#define | BIT_INT_SOURCE5_OIS1_AGC_RDY_INT2_EN 0x04
#define | BIT_INT_SOURCE5_OIS1_FSYNC_INT2_EN 0x02
#define | BIT_INT_SOURCE5_OIS1_DRDY_INT2_EN 0x01
#define | BIT_ST_REGULATOR_EN 0x40
#define | BIT_ACCEL_Z_ST_EN 0x20
#define | BIT_ACCEL_Y_ST_EN 0x10
#define | BIT_ACCEL_X_ST_EN 0x08
#define | BIT_GYRO_Z_ST_EN 0x04
#define | BIT_GYRO_Y_ST_EN 0x02
#define | BIT_GYRO_X_ST_EN 0x01
#define | BIT_DMP_MEM_ACCESS_EN 0x08
#define | BIT_MEM_OTP_ACCESS_EN 0x04
#define | BIT_FIFO_MEM_RD_SYS 0x02
#define | BIT_FIFO_MEM_WR_SER 0x01
#define | BIT_SENSOR_CONFIG2_OIS_MODE_POS 4
#define | BIT_SENSOR_CONFIG2_OIS_MODE_MASK (0x03 << BIT_SENSOR_CONFIG2_OIS_MODE_POS)
#define | BIT_GYRO_AAF_DIS_POS 1
#define | BIT_GYRO_AAF_DIS_MASK (0x01 << BIT_GYRO_AAF_DIS_POS)
#define | BIT_GYRO_NF_DIS_POS 0
#define | BIT_GYRO_NF_DIS_MASK (0x01 << BIT_GYRO_NF_DIS_POS)
#define | BIT_GYRO_AAF_DELT_POS 0
#define | BIT_GYRO_AAF_DELT_MASK (0x3F << BIT_GYRO_AAF_DELT_POS)
#define | BIT_GYRO_AAF_DELTSQR_POS_LO 0
#define | BIT_GYRO_AAF_DELTSQR_MASK_LO (0xFF << BIT_GYRO_AAF_DELTSQR_POS_LO)
#define | BIT_GYRO_AAF_DELTSQR_POS_HI 0
#define | BIT_GYRO_AAF_DELTSQR_MASK_HI (0x0F << BIT_GYRO_AAF_DELTSQR_POS_HI)
#define | BIT_GYRO_AAF_BITSHIFT_POS 4
#define | BIT_GYRO_AAF_BITSHIFT_MASK (0x0F << BIT_GYRO_AAF_BITSHIFT_POS)
#define | BIT_INTF_CONFIG4_AP_SPI_POS 1
#define | BIT_INTF_CONFIG4_AP_SPI_MASK (0x1 << BIT_INTF_CONFIG4_AP_SPI_POS)
#define | BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS 1
#define | BIT_INTF_CONFIG5_GPIO_PAD_SEL_MASK (0x3 << BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS)
#define | BIT_INTF_CONFIG6_I3C_DDR_EN_POS 1
#define | BIT_INTF_CONFIG6_I3C_DDR_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_DDR_EN_POS)
#define | BIT_INTF_CONFIG6_I3C_SDR_EN_POS 0
#define | BIT_INTF_CONFIG6_I3C_SDR_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_SDR_EN_POS)
#define | BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS 3
#define | BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS)
#define | BIT_INTF_CONFIG6_I3C_IBI_EN_POS 2
#define | BIT_INTF_CONFIG6_I3C_IBI_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_IBI_EN_POS)
#define | BIT_ACCEL_AAF_DIS_POS 0
#define | BIT_ACCEL_AAF_DIS_MASK (0x01 << BIT_ACCEL_AAF_DIS_POS)
#define | BIT_ACCEL_AAF_DELT_POS 1
#define | BIT_ACCEL_AAF_DELT_MASK (0x3F << BIT_ACCEL_AAF_DELT_POS)
#define | BIT_ACCEL_AAF_DELTSQR_POS_LO 0
#define | BIT_ACCEL_AAF_DELTSQR_MASK_LO (0xFF << BIT_ACCEL_AAF_DELTSQR_POS_LO)
#define | BIT_ACCEL_AAF_DELTSQR_POS_HI 0
#define | BIT_ACCEL_AAF_DELTSQR_MASK_HI (0x0F << BIT_ACCEL_AAF_DELTSQR_POS_HI)
#define | BIT_ACCEL_AAF_BITSHIFT_POS 4
#define | BIT_ACCEL_AAF_BITSHIFT_MASK (0x0F << BIT_ACCEL_AAF_BITSHIFT_POS)
#define | BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS 5
#define | BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_MASK (0x1 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS)
#define | BIT_OIS1_CONFIG1_DEC_POS 2
#define | BIT_OIS1_CONFIG1_DEC_MASK (0x7 << BIT_OIS1_CONFIG1_DEC_POS)
#define | BIT_OIS1_CONFIG1_GYRO_EN_POS 1
#define | BIT_OIS1_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS1_CONFIG1_GYRO_EN_POS)
#define | BIT_OIS1_CONFIG1_ACCEL_EN_POS 0
#define | BIT_OIS1_CONFIG1_ACCEL_EN_MASK (0x1 << BIT_OIS1_CONFIG1_ACCEL_EN_POS)
#define | BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS 3
#define | BIT_OIS1_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS)
#define | BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS 0
#define | BIT_OIS1_CONFIG2_ACCEL_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS)
#define | BIT_INT_STATUS_OIS1_FSYNC 0x04
#define | BIT_INT_STATUS_OIS1_DRDY 0x02
#define | BIT_INT_STATUS_OIS1_AGC_RDY 0x01
#define | BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS 5
#define | BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_MASK (0x1 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS)
#define | BIT_OIS2_CONFIG1_DEC_POS 2
#define | BIT_OIS2_CONFIG1_DEC_MASK (0x7 << BIT_OIS2_CONFIG1_DEC_POS)
#define | BIT_OIS2_CONFIG1_GYRO_EN_POS 1
#define | BIT_OIS2_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS2_CONFIG1_GYRO_EN_POS)
#define | BIT_OIS2_CONFIG1_ACCEL_EN_POS 0
#define | BIT_OIS2_CONFIG1_ACCEL_EN_MASK (0x1 << BIT_OIS2_CONFIG1_ACCEL_EN_POS)
#define | BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS 3
#define | BIT_OIS2_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS)
#define | BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS 0
#define | BIT_OIS2_CONFIG2_ACCEL_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS)
#define | BIT_INT_STATUS_OIS2_FSYNC 0x04
#define | BIT_INT_STATUS_OIS2_DRDY 0x02
#define | BIT_INT_STATUS_OIS2_AGC_RDY 0x01
#define | BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_POS 0
#define | BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_MASK 0x0F
#define | BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS 4
#define | BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_MASK (0x0F << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS)
#define | BIT_APEX_CONFIG2_PEDO_AMP_TH_POS 4
#define | BIT_APEX_CONFIG2_PEDO_AMP_TH_MASK (0x0F<<BIT_APEX_CONFIG2_PEDO_AMP_TH_POS)
#define | BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_POS 0
#define | BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_MASK 0x0F
#define | BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS 5
#define | BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_MASK (0x07<<BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS)
#define | BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS 2
#define | BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_MASK (0x07<<BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS)
#define | BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_POS 0
#define | BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_MASK 0x03
#define | BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS 6
#define | BIT_APEX_CONFIG4_TILT_WAIT_TIME_MASK (0x03<<BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS)
#define | BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS 3
#define | BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_MASK (0x07<<BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS)
#define | BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS 0
#define | BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_MASK (0x07<<BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS)
#define | BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS 0
#define | BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_MASK (0x07<<BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS)
#define | BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS 2
#define | BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_MASK (0x3F << BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS)
#define | IXM42XXX_APEX_CONFIG7_TAP_MIN_JERK_THR_281MG_DEFAULT 0x11
#define | BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_POS 0
#define | BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_MASK 0x3
#define | BIT_APEX_CONFIG8_TAP_TMAX_POS 5
#define | BIT_APEX_CONFIG8_TAP_TMAX_MASK (0x03 << BIT_APEX_CONFIG8_TAP_TMAX_POS)
#define | BIT_APEX_CONFIG8_TAP_TAVG_POS 3
#define | BIT_APEX_CONFIG8_TAP_TAVG_MASK (0x03 << BIT_APEX_CONFIG8_TAP_TAVG_POS)
#define | BIT_APEX_CONFIG8_TAP_TMIN_POS 0
#define | BIT_APEX_CONFIG8_TAP_TMIN_MASK 0x07
#define | BIT_APEX_CONFIG9_SENSITIVITY_MODE_POS 0
#define | BIT_APEX_CONFIG9_SENSITIVITY_MODE_MASK 0x01
#define | BIT_INT_STEP_DET_INT_EN_POS 5
#define | BIT_INT_STEP_CNT_OVFL_INT_EN_POS 4
#define | BIT_INT_TILT_DET_INT_EN_POS 3
#define | BIT_INT_WAKE_DET_INT_EN_POS 2
#define | BIT_INT_SLEEP_DET_INT_EN_POS 1
#define | BIT_INT_TAP_DET_INT_EN_POS 0
#define | BIT_INT_SOURCE6_STEP_DET_INT1_EN 0x20
#define | BIT_INT_SOURCE6_STEP_CNT_OVFL_INT1_EN 0x10
#define | BIT_INT_SOURCE6_TILT_DET_INT1_EN 0x8
#define | BIT_INT_SOURCE6_WAKE_DET_INT1_EN 0x4
#define | BIT_INT_SOURCE6_SLEEP_DET_INT1_EN 0x2
#define | BIT_INT_SOURCE6_TAP_DET_INT1_EN 0x1
#define | BIT_INT_SOURCE7_STEP_DET_INT2_EN 0x20
#define | BIT_INT_SOURCE7_STEP_CNT_OVFL_INT2_EN 0x10
#define | BIT_INT_SOURCE7_TILT_DET_INT2_EN 0x8
#define | BIT_INT_SOURCE7_WAKE_DET_INT2_EN 0x4
#define | BIT_INT_SOURCE7_SLEEP_DET_INT2_EN 0x2
#define | BIT_INT_SOURCE7_TAP_DET_INT2_EN 0x1
#define | BIT_INT_OIS1_DRDY_IBI_EN_POS 6
#define | BIT_INT_UI_FSYNC_IBI_EN_POS 5
#define | BIT_INT_PLL_RDY_IBI_EN_POS 4
#define | BIT_INT_UI_DRDY_IBI_EN_POS 3
#define | BIT_INT_FIFO_THS_IBI_EN_POS 2
#define | BIT_INT_FIFO_FULL_IBI_EN_POS 1
#define | BIT_INT_UI_AGC_RDY_IBI_EN_POS 0
#define | BIT_INT_SOURCE8_OIS1_DRDY_IBI_EN 0x40
#define | BIT_INT_SOURCE8_UI_FSYNC_IBI_EN 0x20
#define | BIT_INT_SOURCE8_PLL_RDY_IBI_EN 0x10
#define | BIT_INT_SOURCE8_UI_DRDY_IBI_EN 0x08
#define | BIT_INT_SOURCE8_FIFO_THS_IBI_EN 0x04
#define | BIT_INT_SOURCE8_FIFO_FULL_IBI_EN 0x02
#define | BIT_INT_SOURCE8_UI_AGC_RDY_IBI_EN 0x01
#define | BIT_INT_SMD_IBI_EN_POS 4
#define | BIT_INT_WOM_Z_IBI_EN_POS 3
#define | BIT_INT_WOM_Y_IBI_EN_POS 2
#define | BIT_INT_WOM_X_IBI_EN_POS 1
#define | BIT_INT_SOURCE9_SMD_IBI_EN 0x10
#define | BIT_INT_SOURCE9_WOM_Z_IBI_EN 0x08
#define | BIT_INT_SOURCE9_WOM_Y_IBI_EN 0x04
#define | BIT_INT_SOURCE9_WOM_X_IBI_EN 0x02
#define | BIT_INT_STEP_DET_IBI_EN_POS 5
#define | BIT_INT_STEP_CNT_OVFL_IBI_EN_POS 4
#define | BIT_INT_TILT_DET_IBI_EN_POS 3
#define | BIT_INT_WAKE_DET_IBI_EN_POS 2
#define | BIT_INT_SLEEP_DET_IBI_EN_POS 1
#define | BIT_INT_TAP_DET_IBI_EN_POS 0
#define | BIT_INT_SOURCE10_STEP_DET_IBI_EN 0x20
#define | BIT_INT_SOURCE10_STEP_CNT_OVFL_IBI_EN 0x10
#define | BIT_INT_SOURCE10_TILT_DET_IBI_EN 0x08
#define | BIT_INT_SOURCE10_WAKE_DET_IBI_EN 0x04
#define | BIT_INT_SOURCE10_SLEEP_DET_IBI_EN 0x02
#define | BIT_INT_SOURCE10_TAP_DET_IBI_EN 0x01
#define | BIT_GYRO_X_OFFUSER_POS_LO 0
#define | BIT_GYRO_X_OFFUSER_MASK_LO (0xFF << BIT_GYRO_X_OFFUSER_POS_LO)
#define | BIT_GYRO_X_OFFUSER_POS_HI 0
#define | BIT_GYRO_X_OFFUSER_MASK_HI (0x0F << BIT_GYRO_X_OFFUSER_POS_HI)
#define | BIT_GYRO_Y_OFFUSER_POS_HI 4
#define | BIT_GYRO_Y_OFFUSER_MASK_HI (0x0F << BIT_GYRO_Y_OFFUSER_POS_HI)
#define | BIT_GYRO_Y_OFFUSER_POS_LO 0
#define | BIT_GYRO_Y_OFFUSER_MASK_LO (0xFF << BIT_GYRO_Y_OFFUSER_POS_LO)
#define | BIT_GYRO_Z_OFFUSER_POS_LO 0
#define | BIT_GYRO_Z_OFFUSER_MASK_LO (0xFF << BIT_GYRO_Z_OFFUSER_POS_LO)
#define | BIT_GYRO_Z_OFFUSER_POS_HI 0
#define | BIT_GYRO_Z_OFFUSER_MASK_HI (0x0F << BIT_GYRO_Z_OFFUSER_POS_HI)
#define | BIT_ACCEL_X_OFFUSER_POS_HI 4
#define | BIT_ACCEL_X_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_X_OFFUSER_POS_HI)
#define | BIT_ACCEL_X_OFFUSER_POS_LO 0
#define | BIT_ACCEL_X_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_X_OFFUSER_POS_LO)
#define | BIT_ACCEL_Y_OFFUSER_POS_LO 0
#define | BIT_ACCEL_Y_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_Y_OFFUSER_POS_LO)
#define | BIT_ACCEL_Y_OFFUSER_POS_HI 0
#define | BIT_ACCEL_Y_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_Y_OFFUSER_POS_HI)
#define | BIT_ACCEL_Z_OFFUSER_POS_HI 4
#define | BIT_ACCEL_Z_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_Z_OFFUSER_POS_HI)
#define | BIT_ACCEL_Z_OFFUSER_POS_LO 0
#define | BIT_ACCEL_Z_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_Z_OFFUSER_POS_LO)

## Enumerations
enum | IXM42XXX_DEVICE_CONFIG_SPI_MODE_t { IXM42XXX_DEVICE_CONFIG_SPI_MODE_1_2 = (0x1 << BIT_DEVICE_CONFIG_SPI_MODE_POS), IXM42XXX_DEVICE_CONFIG_SPI_MODE_0_3 = (0x0 << BIT_DEVICE_CONFIG_SPI_MODE_POS) }
enum | IXM42XXX_CHIP_CONFIG_SPI_MODE_t { IXM42XXX_CHIP_CONFIG_SPI_MODE_1_2 = (0x1 << BIT_CHIP_CONFIG_SPI_MODE_POS), IXM42XXX_CHIP_CONFIG_SPI_MODE_0_3 = (0x0 << BIT_CHIP_CONFIG_SPI_MODE_POS) }
enum | IXM42XXX_DEVICE_CONFIG_RESET_t { IXM42XXX_DEVICE_CONFIG_RESET_EN = 0x01, IXM42XXX_DEVICE_CONFIG_RESET_NONE = 0x00 }
enum | IXM42XXX_CHIP_CONFIG_RESET_t { IXM42XXX_CHIP_CONFIG_RESET_EN = 0x01, IXM42XXX_CHIP_CONFIG_RESET_NONE = 0x00 }
enum | IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_t { IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_PP = (0x01 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS), IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_OD = (0x00 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS) }
enum | IXM42XXX_INT_CONFIG_INT2_POLARITY_t { IXM42XXX_INT_CONFIG_INT2_POLARITY_HIGH = (0x01 << BIT_INT_CONFIG_INT2_POLARITY_POS), IXM42XXX_INT_CONFIG_INT2_POLARITY_LOW = (0x00 << BIT_INT_CONFIG_INT2_POLARITY_POS) }
enum | IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t { IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_PP = (0x01 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS), IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_OD = (0x00 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS) }
enum | IXM42XXX_INT_CONFIG_INT1_POLARITY_t { IXM42XXX_INT_CONFIG_INT1_POLARITY_HIGH = 0x01, IXM42XXX_INT_CONFIG_INT1_POLARITY_LOW = 0x00 }
enum | IXM42XXX_FIFO_CONFIG_MODE_t { IXM42XXX_FIFO_CONFIG_MODE_STOP_ON_FULL = (0x02 << BIT_FIFO_CONFIG_MODE_POS), IXM42XXX_FIFO_CONFIG_MODE_STREAM = (0x01 << BIT_FIFO_CONFIG_MODE_POS), IXM42XXX_FIFO_CONFIG_MODE_BYPASS = (0x00 << BIT_FIFO_CONFIG_MODE_POS) }
enum | IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_t { IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_OTHER = 0x0, IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_WALK = 0x1, IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_RUN = 0x2 }
enum | IXM42XXX_APEX_DATA3_DMP_IDLE_OFF_t { IXM42XXX_APEX_DATA3_DMP_IDLE_ON = (0x01 << BIT_APEX_DATA3_DMP_IDLE_POS), IXM42XXX_APEX_DATA3_DMP_IDLE_OFF = (0x00 << BIT_APEX_DATA3_DMP_IDLE_POS) }
enum | IXM42XXX_APEX_DATA4_TAP_NUM_t { IXM42XXX_APEX_DATA4_TAP_NUM_DOUBLE = (0x02 << BIT_APEX_DATA4_TAP_NUM_POS), IXM42XXX_APEX_DATA4_TAP_NUM_SINGLE = (0x01 << BIT_APEX_DATA4_TAP_NUM_POS) }
enum | IXM42XXX_APEX_DATA4_TAP_AXIS_t { IXM42XXX_APEX_DATA4_TAP_AXIS_Z = (0x02 << BIT_APEX_DATA4_TAP_AXIS_POS), IXM42XXX_APEX_DATA4_TAP_AXIS_Y = (0x01 << BIT_APEX_DATA4_TAP_AXIS_POS), IXM42XXX_APEX_DATA4_TAP_AXIS_X = (0x00 << BIT_APEX_DATA4_TAP_AXIS_POS) }
enum | IXM42XXX_APEX_DATA4_TAP_DIR_t { IXM42XXX_APEX_DATA4_TAP_DIR_POSITIVE = (0x01 << BIT_APEX_DATA4_TAP_DIR_POS), IXM42XXX_APEX_DATA4_TAP_DIR_NEGATIVE = (0x00 << BIT_APEX_DATA4_TAP_DIR_POS) }
enum | IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_t { IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_EN = (0x01 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS), IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS) }
enum | IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_t { IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN = (0x01 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS), IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS) }
enum | IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_t { IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_EN = (0x01 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS), IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS) }
enum | IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_t { IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_EN = (0x01 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS), IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS) }
enum | IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t { IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_DIS = (0x01 << BIT_FIFO_SREG_INVALID_IND_POS), IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_EN = (0x00 << BIT_FIFO_SREG_INVALID_IND_POS) }
enum | IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_t { IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_RECORD = (0x01 << BIT_FIFO_COUNT_REC_POS), IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_BYTE = (0x00 << BIT_FIFO_COUNT_REC_POS) }
enum | IXM42XXX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t { IXM42XXX_INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN = (0x01 << BIT_FIFO_COUNT_ENDIAN_POS), IXM42XXX_INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN = (0x00 << BIT_FIFO_COUNT_ENDIAN_POS) }
enum | IXM42XXX_INTF_CONFIG0_DATA_ENDIAN_t { IXM42XXX_INTF_CONFIG0_DATA_BIG_ENDIAN = (0x01 << BIT_DATA_ENDIAN_POS), IXM42XXX_INTF_CONFIG0_DATA_LITTLE_ENDIAN = (0x00 << BIT_DATA_ENDIAN_POS) }
enum | IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_t { IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_1_2 = (0x01 << BIT_SPI_MODE_OIS2_POS), IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_0_3 = (0x00 << BIT_SPI_MODE_OIS2_POS) }
enum | IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_t { IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_1_2 = (0x01 << BIT_SPI_MODE_OIS1_POS), IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_0_3 = (0x00 << BIT_SPI_MODE_OIS1_POS) }
enum | IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_t { IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_WUOSC = (0x00 << BIT_ACCEL_LP_CLK_SEL_POS), IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_RCOSC = (0x01 << BIT_ACCEL_LP_CLK_SEL_POS) }
enum | IXM42XXX_INTF_CONFIG1_RTC_MODE_t { IXM42XXX_INTF_CONFIG1_RTC_MODE_DIS = (0x00 << BIT_RTC_MODE_POS), IXM42XXX_INTF_CONFIG1_RTC_MODE_EN = (0x01 << BIT_RTC_MODE_POS) }
enum | IXM42XXX_PWR_MGMT_0_TEMP_t { IXM42XXX_PWR_MGMT_0_TEMP_DIS = (0x01 << BIT_PWR_MGMT_0_TEMP_POS), IXM42XXX_PWR_MGMT_0_TEMP_EN = (0x00 << BIT_PWR_MGMT_0_TEMP_POS) }
enum | IXM42XXX_PWR_MGMT_0_IDLE_t { IXM42XXX_PWR_MGMT_0_IDLE_DIS = (0x01 << BIT_PWR_MGMT_0_IDLE_POS), IXM42XXX_PWR_MGMT_0_IDLE_EN = (0x00 << BIT_PWR_MGMT_0_IDLE_POS) }
enum | IXM42XXX_PWR_MGMT_0_GYRO_MODE_t { IXM42XXX_PWR_MGMT_0_GYRO_MODE_LN = (0x03 << BIT_PWR_MGMT_0_GYRO_MODE_POS), IXM42XXX_PWR_MGMT_0_GYRO_MODE_STANDBY = (0x01 << BIT_PWR_MGMT_0_GYRO_MODE_POS), IXM42XXX_PWR_MGMT_0_GYRO_MODE_OFF = (0x00 << BIT_PWR_MGMT_0_GYRO_MODE_POS) }
enum | IXM42XXX_PWR_MGMT_0_ACCEL_MODE_t { IXM42XXX_PWR_MGMT_0_ACCEL_MODE_LN = 0x03, IXM42XXX_PWR_MGMT_0_ACCEL_MODE_LP = 0x02, IXM42XXX_PWR_MGMT_0_ACCEL_MODE_OFF = 0x00 }
enum | IXM42XXX_GYRO_CONFIG0_FS_SEL_t { IXM42XXX_GYRO_CONFIG0_FS_SEL_16dps = (7 << BIT_GYRO_CONFIG0_FS_SEL_POS), IXM42XXX_GYRO_CONFIG0_FS_SEL_31dps = (6 << BIT_GYRO_CONFIG0_FS_SEL_POS), IXM42XXX_GYRO_CONFIG0_FS_SEL_62dps = (5 << BIT_GYRO_CONFIG0_FS_SEL_POS), IXM42XXX_GYRO_CONFIG0_FS_SEL_125dps = (4 << BIT_GYRO_CONFIG0_FS_SEL_POS), IXM42XXX_GYRO_CONFIG0_FS_SEL_250dps = (3 << BIT_GYRO_CONFIG0_FS_SEL_POS), IXM42XXX_GYRO_CONFIG0_FS_SEL_500dps = (2 << BIT_GYRO_CONFIG0_FS_SEL_POS), IXM42XXX_GYRO_CONFIG0_FS_SEL_1000dps = (1 << BIT_GYRO_CONFIG0_FS_SEL_POS), IXM42XXX_GYRO_CONFIG0_FS_SEL_2000dps = (0 << BIT_GYRO_CONFIG0_FS_SEL_POS) }
| Gyroscope FSR selection. More...
enum | IXM42XXX_GYRO_CONFIG0_ODR_t { IXM42XXX_GYRO_CONFIG0_ODR_500_HZ = 0x0F, IXM42XXX_GYRO_CONFIG0_ODR_12_5_HZ = 0x0B, IXM42XXX_GYRO_CONFIG0_ODR_25_HZ = 0x0A, IXM42XXX_GYRO_CONFIG0_ODR_50_HZ = 0x09, IXM42XXX_GYRO_CONFIG0_ODR_100_HZ = 0x08, IXM42XXX_GYRO_CONFIG0_ODR_200_HZ = 0x07, IXM42XXX_GYRO_CONFIG0_ODR_1_KHZ = 0x06, IXM42XXX_GYRO_CONFIG0_ODR_2_KHZ = 0x05, IXM42XXX_GYRO_CONFIG0_ODR_4_KHZ = 0x04, IXM42XXX_GYRO_CONFIG0_ODR_8_KHZ = 0x03, IXM42XXX_GYRO_CONFIG0_ODR_16_KHZ = 0x02, IXM42XXX_GYRO_CONFIG0_ODR_32_KHZ = 0x01 }
| Gyroscope ODR selection. More...
enum | IXM42XXX_ACCEL_CONFIG0_FS_SEL_t { IXM42XXX_ACCEL_CONFIG0_FS_SEL_RESERVED = (0x4 << BIT_ACCEL_CONFIG0_FS_SEL_POS), IXM42XXX_ACCEL_CONFIG0_FS_SEL_2g = (0x3 << BIT_ACCEL_CONFIG0_FS_SEL_POS), IXM42XXX_ACCEL_CONFIG0_FS_SEL_4g = (0x2 << BIT_ACCEL_CONFIG0_FS_SEL_POS), IXM42XXX_ACCEL_CONFIG0_FS_SEL_8g = (0x1 << BIT_ACCEL_CONFIG0_FS_SEL_POS), IXM42XXX_ACCEL_CONFIG0_FS_SEL_16g = (0x0 << BIT_ACCEL_CONFIG0_FS_SEL_POS) }
| Accelerometer FSR selection. More...
enum | IXM42XXX_ACCEL_CONFIG0_ODR_t { IXM42XXX_ACCEL_CONFIG0_ODR_500_HZ = 0xF, IXM42XXX_ACCEL_CONFIG0_ODR_1_5625_HZ = 0xE, IXM42XXX_ACCEL_CONFIG0_ODR_3_125_HZ = 0xD, IXM42XXX_ACCEL_CONFIG0_ODR_6_25_HZ = 0xC, IXM42XXX_ACCEL_CONFIG0_ODR_12_5_HZ = 0xB, IXM42XXX_ACCEL_CONFIG0_ODR_25_HZ = 0xA, IXM42XXX_ACCEL_CONFIG0_ODR_50_HZ = 0x9, IXM42XXX_ACCEL_CONFIG0_ODR_100_HZ = 0x8, IXM42XXX_ACCEL_CONFIG0_ODR_200_HZ = 0x7, IXM42XXX_ACCEL_CONFIG0_ODR_1_KHZ = 0x6, IXM42XXX_ACCEL_CONFIG0_ODR_2_KHZ = 0x5, IXM42XXX_ACCEL_CONFIG0_ODR_4_KHZ = 0x4, IXM42XXX_ACCEL_CONFIG0_ODR_8_KHZ = 0x3, IXM42XXX_ACCEL_CONFIG0_ODR_16_KHZ = 0x2, IXM42XXX_ACCEL_CONFIG0_ODR_32_KHZ = 0x1 }
| Accelerometer ODR selection. More...
enum | IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_t { IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_1ST_ORDER = (0x0 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS), IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_2ND_ORDER = (0x1 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS), IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_3RD_ORDER = (0x2 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS) }
enum | IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t { IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_40 = (0x7 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS), IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_20 = (0x6 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS), IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_16 = (0x5 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS), IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_10 = (0x4 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS), IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_8 = (0x3 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS), IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_5 = (0x2 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS), IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_4 = (0x1 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS), IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_2 = (0x0 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS) }
enum | IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t { IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_16 = (0x6 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS), IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_1 = (0x1 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS) }
enum | IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t { IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_40 = 0x07, IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_20 = 0x06, IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_16 = 0x05, IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_10 = 0x04, IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_8 = 0x03, IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_5 = 0x02, IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_4 = 0x01, IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_2 = 0x00 }
enum | IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_t { IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_1ST_ORDER = (0x0 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS), IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_2ND_ORDER = (0x1 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS), IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_3RD_ORDER = (0x2 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS) }
enum | IXM42XXX_TMST_CONFIG_TMST_TO_REGS_EN_t { IXM42XXX_TMST_CONFIG_TMST_TO_REGS_EN = (0x1 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS), IXM42XXX_TMST_CONFIG_TMST_TO_REGS_DIS = (0x0 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS) }
enum | IXM42XXX_TMST_CONFIG_RESOL_t { IXM42XXX_TMST_CONFIG_RESOL_16us = (0x01 << BIT_TMST_CONFIG_RESOL_POS), IXM42XXX_TMST_CONFIG_RESOL_1us = (0x00 << BIT_TMST_CONFIG_RESOL_POS) }
enum | IXM42XXX_TMST_CONFIG_TMST_FSYNC_EN_t { IXM42XXX_TMST_CONFIG_TMST_FSYNC_EN = (0x01 << BIT_TMST_CONFIG_TMST_FSYNC_POS), IXM42XXX_TMST_CONFIG_TMST_FSYNC_DIS = (0x00 << BIT_TMST_CONFIG_TMST_FSYNC_POS) }
enum | IXM42XXX_TMST_CONFIG_TMST_EN_t { IXM42XXX_TMST_CONFIG_TMST_EN = 0x01, IXM42XXX_TMST_CONFIG_TMST_DIS = 0x00 }
enum | IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_t { IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_EN = (0x1 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS), IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_DIS = (0x0 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS) }
enum | IXM42XXX_APEX_CONFIG0_TAP_ENABLE_t { IXM42XXX_APEX_CONFIG0_TAP_ENABLE_EN = (0x1 << BIT_APEX_CONFIG0_TAP_ENABLE_POS), IXM42XXX_APEX_CONFIG0_TAP_ENABLE_DIS = (0x0 << BIT_APEX_CONFIG0_TAP_ENABLE_POS) }
enum | IXM42XXX_APEX_CONFIG0_PEDO_EN_t { IXM42XXX_APEX_CONFIG0_PEDO_EN_EN = (0x1 << BIT_APEX_CONFIG0_PEDO_EN_POS), IXM42XXX_APEX_CONFIG0_PEDO_EN_DIS = (0x0 << BIT_APEX_CONFIG0_PEDO_EN_POS) }
enum | IXM42XXX_APEX_CONFIG0_R2W_EN_t { IXM42XXX_APEX_CONFIG0_R2W_EN_EN = (0x1 << BIT_APEX_CONFIG0_R2W_EN_POS), IXM42XXX_APEX_CONFIG0_R2W_EN_DIS = (0x0 << BIT_APEX_CONFIG0_R2W_EN_POS) }
enum | IXM42XXX_APEX_CONFIG0_TILT_EN_t { IXM42XXX_APEX_CONFIG0_TILT_EN_EN = (0x1 << BIT_APEX_CONFIG0_TILT_EN_POS), IXM42XXX_APEX_CONFIG0_TILT_EN_DIS = (0x0 << BIT_APEX_CONFIG0_TILT_EN_POS) }
enum | IXM42XXX_APEX_CONFIG0_DMP_ODR_t { IXM42XXX_APEX_CONFIG0_DMP_ODR_25Hz = (0x0 << BIT_APEX_CONFIG0_DMP_ODR_POS), IXM42XXX_APEX_CONFIG0_DMP_ODR_50Hz = (0x2 << BIT_APEX_CONFIG0_DMP_ODR_POS), IXM42XXX_APEX_CONFIG0_DMP_ODR_RESERVED = (0x3 << BIT_APEX_CONFIG0_DMP_ODR_POS) }
| DMP ODR selection. More...
enum | IXM42XXX_SMD_CONFIG_WOM_INT_MODE_t { IXM42XXX_SMD_CONFIG_WOM_INT_MODE_ANDED = (0x01 << BIT_SMD_CONFIG_WOM_INT_MODE_POS), IXM42XXX_SMD_CONFIG_WOM_INT_MODE_ORED = (0x00 << BIT_SMD_CONFIG_WOM_INT_MODE_POS) }
enum | IXM42XXX_SMD_CONFIG_WOM_MODE_t { IXM42XXX_SMD_CONFIG_WOM_MODE_CMP_PREV = (0x01 << BIT_SMD_CONFIG_WOM_MODE_POS), IXM42XXX_SMD_CONFIG_WOM_MODE_CMP_INIT = (0x00 << BIT_SMD_CONFIG_WOM_MODE_POS) }
enum | IXM42XXX_SMD_CONFIG_SMD_MODE_t { IXM42XXX_SMD_CONFIG_SMD_MODE_LONG = 0x03, IXM42XXX_SMD_CONFIG_SMD_MODE_SHORT = 0x02, IXM42XXX_SMD_CONFIG_SMD_MODE_WOM = 0x01, IXM42XXX_SMD_CONFIG_SMD_MODE_DISABLED = 0x00 }
enum | IXM42XXX_FIFO_CONFIG1_WM_GT_t { IXM42XXX_FIFO_CONFIG1_WM_GT_TH_EN = (0x1 << BIT_FIFO_CONFIG1_WM_GT_TH_POS), IXM42XXX_FIFO_CONFIG1_WM_GT_TH_DIS = (0x0 << BIT_FIFO_CONFIG1_WM_GT_TH_POS) }
enum | IXM42XXX_FIFO_CONFIG1_HIRES_t { IXM42XXX_FIFO_CONFIG1_HIRES_EN = (0x1 << BIT_FIFO_CONFIG1_HIRES_POS), IXM42XXX_FIFO_CONFIG1_HIRES_DIS = (0x0 << BIT_FIFO_CONFIG1_HIRES_POS) }
enum | IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_t { IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_EN = (0x1 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS), IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_DIS = (0x0 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS) }
enum | IXM42XXX_FIFO_CONFIG1_TEMP_t { IXM42XXX_FIFO_CONFIG1_TEMP_EN = (0x1 << BIT_FIFO_CONFIG1_TEMP_POS), IXM42XXX_FIFO_CONFIG1_TEMP_DIS = (0x0 << BIT_FIFO_CONFIG1_TEMP_POS) }
enum | IXM42XXX_FIFO_CONFIG1_GYRO_t { IXM42XXX_FIFO_CONFIG1_GYRO_EN = (0x1 << BIT_FIFO_CONFIG1_GYRO_POS), IXM42XXX_FIFO_CONFIG1_GYRO_DIS = (0x0 << BIT_FIFO_CONFIG1_GYRO_POS) }
enum | IXM42XXX_FIFO_CONFIG1_ACCEL_t { IXM42XXX_FIFO_CONFIG1_ACCEL_EN = 0x01, IXM42XXX_FIFO_CONFIG1_ACCEL_DIS = 0x00 }
enum | IXM42XXX_FSYNC_CONFIG_UI_SEL_t { IXM42XXX_FSYNC_CONFIG_UI_SEL_NO = (0x0 << BIT_FSYNC_CONFIG_UI_SEL_POS), IXM42XXX_FSYNC_CONFIG_UI_SEL_TEMP = (0x1 << BIT_FSYNC_CONFIG_UI_SEL_POS), IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_X = (0x2 << BIT_FSYNC_CONFIG_UI_SEL_POS), IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_Y = (0x3 << BIT_FSYNC_CONFIG_UI_SEL_POS), IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_Z = (0x4 << BIT_FSYNC_CONFIG_UI_SEL_POS), IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_X = (0x5 << BIT_FSYNC_CONFIG_UI_SEL_POS), IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_Y = (0x6 << BIT_FSYNC_CONFIG_UI_SEL_POS), IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_Z = (0x7 << BIT_FSYNC_CONFIG_UI_SEL_POS) }
enum | IXM42XXX_INT_CONFIG1_ASY_RST_t { IXM42XXX_INT_CONFIG1_ASY_RST_DISABLED = (0x1 << BIT_INT_CONFIG1_ASY_RST_POS), IXM42XXX_INT_CONFIG1_ASY_RST_ENABLED = (0x0 << BIT_INT_CONFIG1_ASY_RST_POS) }
enum | IXM42XXX_SENSOR_CONFIG2_OIS_MODE_t { IXM42XXX_SENSOR_CONFIG2_OIS_MODE_32KHZ = (0x2 << BIT_SENSOR_CONFIG2_OIS_MODE_POS), IXM42XXX_SENSOR_CONFIG2_OIS_MODE_8KHZ = (0x1 << BIT_SENSOR_CONFIG2_OIS_MODE_POS), IXM42XXX_SENSOR_CONFIG2_OIS_MODE_DIS = (0x0 << BIT_SENSOR_CONFIG2_OIS_MODE_POS) }
enum | IXM42XXX_GYRO_AAF_DIS_t { IXM42XXX_GYRO_AAF_EN = (0x0 << BIT_GYRO_AAF_DIS_POS), IXM42XXX_GYRO_AAF_DIS = (0x1 << BIT_GYRO_AAF_DIS_POS) }
enum | IXM42XXX_GYRO_NF_DIS_t { IXM42XXX_GYRO_NF_EN = (0x0 << BIT_GYRO_NF_DIS_POS), IXM42XXX_GYRO_NF_DIS = (0x1 << BIT_GYRO_NF_DIS_POS) }
enum | IXM42XXX_INTF_CONFIG4_AP_SPI_t { IXM42XXX_INTF_CONFIG4_AP_SPI4W = (0x1 << BIT_INTF_CONFIG4_AP_SPI_POS), IXM42XXX_INTF_CONFIG4_AP_SPI3W = (0x0 << BIT_INTF_CONFIG4_AP_SPI_POS) }
enum | IXM42XXX_ACCEL_AAF_DIS_t { IXM42XXX_ACCEL_AAF_EN = (0x0 << BIT_ACCEL_AAF_DIS_POS), IXM42XXX_ACCEL_AAF_DIS = (0x1 << BIT_ACCEL_AAF_DIS_POS) }
enum | IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_t { IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC = (0x0 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS), IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC = (0x1 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS) }
enum | IXM42XXX_OIS1_CONFIG1_DEC_t { IXM42XXX_OIS1_CONFIG1_DEC_1 = (0x0 << BIT_OIS1_CONFIG1_DEC_POS), IXM42XXX_OIS1_CONFIG1_DEC_2 = (0x1 << BIT_OIS1_CONFIG1_DEC_POS), IXM42XXX_OIS1_CONFIG1_DEC_4 = (0x2 << BIT_OIS1_CONFIG1_DEC_POS), IXM42XXX_OIS1_CONFIG1_DEC_8 = (0x3 << BIT_OIS1_CONFIG1_DEC_POS), IXM42XXX_OIS1_CONFIG1_DEC_16 = (0x4 << BIT_OIS1_CONFIG1_DEC_POS), IXM42XXX_OIS1_CONFIG1_DEC_32 = (0x5 << BIT_OIS1_CONFIG1_DEC_POS) }
| OIS1 rate selection (base clock fixed by OTP divided by decimator value) More...
enum | IXM42XXX_OIS1_CONFIG1_GYRO_EN_t { IXM42XXX_OIS1_CONFIG1_GYRO_EN = (0x1 << BIT_OIS1_CONFIG1_GYRO_EN_POS), IXM42XXX_OIS1_CONFIG1_GYRO_DIS = (0x0 << BIT_OIS1_CONFIG1_GYRO_EN_POS) }
enum | IXM42XXX_OIS1_CONFIG1_ACCEL_EN_t { IXM42XXX_OIS1_CONFIG1_ACCEL_EN = (0x1 << BIT_OIS1_CONFIG1_ACCEL_EN_POS), IXM42XXX_OIS1_CONFIG1_ACCEL_DIS = (0x0 << BIT_OIS1_CONFIG1_ACCEL_EN_POS) }
enum | IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_t { IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_16dps = (0x7 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS), IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_31dps = (0x6 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS), IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_62dps = (0x5 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS), IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_125dps = (0x4 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS), IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_250dps = (0x3 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS), IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_500dps = (0x2 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS), IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_1000dps = (0x1 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS), IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_2000dps = (0x0 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS) }
| OIS1 gyroscope FSR selection. More...
enum | IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_t { IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_RESERVED = (0x4 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS), IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_2g = (0x3 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS), IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_4g = (0x2 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS), IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_8g = (0x1 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS), IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_16g = (0x0 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS) }
| OIS1 accelerometer FSR selection. More...
enum | IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_t { IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC = (0x0 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS), IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC = (0x1 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS) }
enum | IXM42XXX_OIS2_CONFIG1_DEC_t { IXM42XXX_OIS2_CONFIG1_DEC_1 = (0x0 << BIT_OIS2_CONFIG1_DEC_POS), IXM42XXX_OIS2_CONFIG1_DEC_2 = (0x1 << BIT_OIS2_CONFIG1_DEC_POS), IXM42XXX_OIS2_CONFIG1_DEC_4 = (0x2 << BIT_OIS2_CONFIG1_DEC_POS), IXM42XXX_OIS2_CONFIG1_DEC_8 = (0x3 << BIT_OIS2_CONFIG1_DEC_POS), IXM42XXX_OIS2_CONFIG1_DEC_16 = (0x4 << BIT_OIS2_CONFIG1_DEC_POS), IXM42XXX_OIS2_CONFIG1_DEC_32 = (0x5 << BIT_OIS2_CONFIG1_DEC_POS) }
| OIS2 rate selection (base clock fixed by OTP divided by decimator value) More...
enum | IXM42XXX_OIS2_CONFIG1_GYRO_EN_t { IXM42XXX_OIS2_CONFIG1_GYRO_EN = (0x1 << BIT_OIS2_CONFIG1_GYRO_EN_POS), IXM42XXX_OIS2_CONFIG1_GYRO_DIS = (0x0 << BIT_OIS2_CONFIG1_GYRO_EN_POS) }
enum | IXM42XXX_OIS2_CONFIG1_ACCEL_EN_t { IXM42XXX_OIS2_CONFIG1_ACCEL_EN = (0x1 << BIT_OIS2_CONFIG1_ACCEL_EN_POS), IXM42XXX_OIS2_CONFIG1_ACCEL_DIS = (0x0 << BIT_OIS2_CONFIG1_ACCEL_EN_POS) }
enum | IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_t { IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_16dps = (0x7 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS), IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_31dps = (0x6 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS), IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_62dps = (0x5 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS), IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_125dps = (0x4 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS), IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_250dps = (0x3 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS), IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_500dps = (0x2 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS), IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_1000dps = (0x1 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS), IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_2000dps = (0x0 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS) }
| OIS2 gyroscope FSR selection. More...
enum | IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_t { IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_RESERVED = (0x4 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS), IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_2g = (0x3 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS), IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_4g = (0x2 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS), IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_8g = (0x1 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS), IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_16g = (0x0 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS) }
| OIS2 accelerometer FSR selection. More...
enum | IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t { IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_0S = 0x0, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_4S = 0x1, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_8S = 0x2, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_12S = 0x3, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_16S = 0x4, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_20S = 0x5, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_24S = 0x6, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_28S = 0x7, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_32S = 0x8, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_36S = 0x9, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_40S = 0xA, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_44S = 0xB, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_48S = 0xC, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_52S = 0xD, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_56S = 0xE, IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_60S = 0xF }
enum | IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t { IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1006632MG = (0 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1174405MG = (1 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1342177MG = (2 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1509949MG = (3 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1677721MG = (4 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1845493MG = (5 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2013265MG = (6 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2181038MG = (7 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2348810MG = (8 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2516582MG = (9 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2684354MG = (10 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2852126MG = (11 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3019898MG = (12 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3187671MG = (13 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3355443MG = (14 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS), IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3523215MG = (15 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS) }
enum | IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_t { IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1006632_MG = (0 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1140850_MG = (1 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1275068_MG = (2 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1409286_MG = (3 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1543503_MG = (4 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1677721_MG = (5 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1811939_MG = (6 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1946157_MG = (7 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2080374_MG = (8 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2214592_MG = (9 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2348810_MG = (10 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2483027_MG = (11 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2617245_MG = (12 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2751463_MG = (13 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2885681_MG = (14 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS), IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_3019898_MG = (15 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS) }
enum | IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t { IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_50_SAMPLES = (0 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS), IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_75_SAMPLES = (1 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS), IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_100_SAMPLES = (2 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS), IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_125_SAMPLES = (3 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS), IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_150_SAMPLES = (4 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS), IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_175_SAMPLES = (5 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS), IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_200_SAMPLES = (6 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS), IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_225_SAMPLES = (7 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS) }
enum | IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t { IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_90 = 0x0, IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_107 = 0x1, IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_136 = 0x2, IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_159 = 0x3 }
enum | IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_t { IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_0 = (0 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS), IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_2S = (1 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS), IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_4S = (2 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS), IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_6S = (3 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS) }
enum | IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t { IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_1_28S = (0 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS), IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_2_56S = (1 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS), IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_3_84S = (2 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS), IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_5_12S = (3 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS), IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_6_4S = (4 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS), IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_7_68S = (5 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS), IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_8_96S = (6 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS), IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_10_24S = (7 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS) }
enum | IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t { IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_0 = (0 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS), IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_1 = (1 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS), IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_2 = (2 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS), IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_3 = (3 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS), IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_4 = (4 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS), IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_5 = (5 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS), IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_6 = (6 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS), IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_7 = (7 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS) }
enum | IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t { IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_32S = (0 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS), IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_64S = (1 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS), IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_96S = (2 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS), IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_28S = (3 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS), IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_6S = (4 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS), IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_92S = (5 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS), IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_24S = (6 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS), IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_56S = (7 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS) }
enum | IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t { IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_12 = 0x0, IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_25 = 0x1, IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_37 = 0x2, IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_50 = 0x3 }
enum | IXM42XXX_APEX_CONFIG8_TAP_TMAX_t { IXM42XXX_APEX_CONFIG8_TAP_TMAX_250MS = (0 << BIT_APEX_CONFIG8_TAP_TMAX_POS), IXM42XXX_APEX_CONFIG8_TAP_TMAX_375MS = (1 << BIT_APEX_CONFIG8_TAP_TMAX_POS), IXM42XXX_APEX_CONFIG8_TAP_TMAX_500MS = (2 << BIT_APEX_CONFIG8_TAP_TMAX_POS), IXM42XXX_APEX_CONFIG8_TAP_TMAX_625MS = (3 << BIT_APEX_CONFIG8_TAP_TMAX_POS) }
enum | IXM42XXX_APEX_CONFIG8_TAP_TAVG_t { IXM42XXX_APEX_CONFIG8_TAP_TAVG_1SAMPLE = (0 << BIT_APEX_CONFIG8_TAP_TAVG_POS), IXM42XXX_APEX_CONFIG8_TAP_TAVG_2SAMPLE = (1 << BIT_APEX_CONFIG8_TAP_TAVG_POS), IXM42XXX_APEX_CONFIG8_TAP_TAVG_4SAMPLE = (2 << BIT_APEX_CONFIG8_TAP_TAVG_POS), IXM42XXX_APEX_CONFIG8_TAP_TAVG_8SAMPLE = (3 << BIT_APEX_CONFIG8_TAP_TAVG_POS) }
enum | IXM42XXX_APEX_CONFIG8_TAP_TMIN_t { IXM42XXX_APEX_CONFIG8_TAP_TMIN_125MS = 0x0, IXM42XXX_APEX_CONFIG8_TAP_TMIN_140MS = 0x1, IXM42XXX_APEX_CONFIG8_TAP_TMIN_156MS = 0x2, IXM42XXX_APEX_CONFIG8_TAP_TMIN_171MS = 0x3, IXM42XXX_APEX_CONFIG8_TAP_TMIN_187MS = 0x4, IXM42XXX_APEX_CONFIG8_TAP_TMIN_203MS = 0x5, IXM42XXX_APEX_CONFIG8_TAP_TMIN_218MS = 0x6, IXM42XXX_APEX_CONFIG8_TAP_TMIN_234MS = 0x7 }
enum | IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_t { IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_NORMAL = 0x00, IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_RESERVED = 0x01 }

## Detailed Description

File exposing the device register map

Definition in file Ixm42xxxDefs.h.

## Macro Definition Documentation

## ◆ ACCEL_DATA_SIZE

#define ACCEL_DATA_SIZE 6

Definition at line 211 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_AAF_BITSHIFT_MASK

#define BIT_ACCEL_AAF_BITSHIFT_MASK (0x0F << BIT_ACCEL_AAF_BITSHIFT_POS)

Definition at line 1393 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_AAF_BITSHIFT_POS

#define BIT_ACCEL_AAF_BITSHIFT_POS 4

Definition at line 1392 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_AAF_DELT_MASK

#define BIT_ACCEL_AAF_DELT_MASK (0x3F << BIT_ACCEL_AAF_DELT_POS)

Definition at line 1371 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_AAF_DELT_POS

#define BIT_ACCEL_AAF_DELT_POS 1

Definition at line 1370 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_AAF_DELTSQR_MASK_HI

#define BIT_ACCEL_AAF_DELTSQR_MASK_HI (0x0F << BIT_ACCEL_AAF_DELTSQR_POS_HI)

Definition at line 1389 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_AAF_DELTSQR_MASK_LO

#define BIT_ACCEL_AAF_DELTSQR_MASK_LO (0xFF << BIT_ACCEL_AAF_DELTSQR_POS_LO)

Definition at line 1380 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_AAF_DELTSQR_POS_HI

#define BIT_ACCEL_AAF_DELTSQR_POS_HI 0

Definition at line 1388 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_AAF_DELTSQR_POS_LO

#define BIT_ACCEL_AAF_DELTSQR_POS_LO 0

Definition at line 1379 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_AAF_DIS_MASK

#define BIT_ACCEL_AAF_DIS_MASK (0x01 << BIT_ACCEL_AAF_DIS_POS)

Definition at line 1361 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_AAF_DIS_POS

#define BIT_ACCEL_AAF_DIS_POS 0

Definition at line 1360 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_CONFIG0_FS_SEL_MASK

#define BIT_ACCEL_CONFIG0_FS_SEL_MASK (0x7 << BIT_ACCEL_CONFIG0_FS_SEL_POS)

Definition at line 745 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_CONFIG0_FS_SEL_POS

#define BIT_ACCEL_CONFIG0_FS_SEL_POS 5

Definition at line 744 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_CONFIG0_ODR_MASK

#define BIT_ACCEL_CONFIG0_ODR_MASK 0x0F

Definition at line 768 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_CONFIG0_ODR_POS

#define BIT_ACCEL_CONFIG0_ODR_POS 0

Definition at line 767 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_MASK

#define BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS)

Definition at line 877 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS

#define BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS 1

Definition at line 876 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_MASK

#define BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS)

Definition at line 866 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS

#define BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS 3

Definition at line 865 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_LP_CLK_SEL_MASK

#define BIT_ACCEL_LP_CLK_SEL_MASK (0x01 << BIT_ACCEL_LP_CLK_SEL_POS)

Definition at line 617 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_LP_CLK_SEL_POS

#define BIT_ACCEL_LP_CLK_SEL_POS 3

Definition at line 616 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_X_OFFUSER_MASK_HI

#define BIT_ACCEL_X_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_X_OFFUSER_POS_HI)

Definition at line 2014 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_X_OFFUSER_MASK_LO

#define BIT_ACCEL_X_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_X_OFFUSER_POS_LO)

Definition at line 2022 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_X_OFFUSER_POS_HI

#define BIT_ACCEL_X_OFFUSER_POS_HI 4

Definition at line 2013 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_X_OFFUSER_POS_LO

#define BIT_ACCEL_X_OFFUSER_POS_LO 0

Definition at line 2021 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_X_ST_EN

#define BIT_ACCEL_X_ST_EN 0x08

Definition at line 1216 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_Y_OFFUSER_MASK_HI

#define BIT_ACCEL_Y_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_Y_OFFUSER_POS_HI)

Definition at line 2040 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_Y_OFFUSER_MASK_LO

#define BIT_ACCEL_Y_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_Y_OFFUSER_POS_LO)

Definition at line 2031 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_Y_OFFUSER_POS_HI

#define BIT_ACCEL_Y_OFFUSER_POS_HI 0

Definition at line 2039 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_Y_OFFUSER_POS_LO

#define BIT_ACCEL_Y_OFFUSER_POS_LO 0

Definition at line 2030 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_Y_ST_EN

#define BIT_ACCEL_Y_ST_EN 0x10

Definition at line 1215 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_Z_OFFUSER_MASK_HI

#define BIT_ACCEL_Z_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_Z_OFFUSER_POS_HI)

Definition at line 2044 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_Z_OFFUSER_MASK_LO

#define BIT_ACCEL_Z_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_Z_OFFUSER_POS_LO)

Definition at line 2053 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_Z_OFFUSER_POS_HI

#define BIT_ACCEL_Z_OFFUSER_POS_HI 4

Definition at line 2043 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_Z_OFFUSER_POS_LO

#define BIT_ACCEL_Z_OFFUSER_POS_LO 0

Definition at line 2052 of file Ixm42xxxDefs.h.

## ◆ BIT_ACCEL_Z_ST_EN

#define BIT_ACCEL_Z_ST_EN 0x20

Definition at line 1214 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG0_DMP_ODR_MASK

#define BIT_APEX_CONFIG0_DMP_ODR_MASK (0x3 << BIT_APEX_CONFIG0_DMP_ODR_POS)

Definition at line 981 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG0_DMP_ODR_POS

#define BIT_APEX_CONFIG0_DMP_ODR_POS 0

Definition at line 980 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG0_DMP_POWER_SAVE_MASK

#define BIT_APEX_CONFIG0_DMP_POWER_SAVE_MASK (0x1 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS)

Definition at line 931 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS

#define BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS 7

Definition at line 930 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG0_PEDO_EN_MASK

#define BIT_APEX_CONFIG0_PEDO_EN_MASK (0x1 << BIT_APEX_CONFIG0_PEDO_EN_POS)

Definition at line 951 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG0_PEDO_EN_POS

#define BIT_APEX_CONFIG0_PEDO_EN_POS 5

Definition at line 950 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG0_R2W_EN_MASK

#define BIT_APEX_CONFIG0_R2W_EN_MASK (0x1 << BIT_APEX_CONFIG0_R2W_EN_POS)

Definition at line 961 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG0_R2W_EN_POS

#define BIT_APEX_CONFIG0_R2W_EN_POS 3

Definition at line 960 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG0_TAP_ENABLE_MASK

#define BIT_APEX_CONFIG0_TAP_ENABLE_MASK (0x1 << BIT_APEX_CONFIG0_TAP_ENABLE_POS)

Definition at line 941 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG0_TAP_ENABLE_POS

#define BIT_APEX_CONFIG0_TAP_ENABLE_POS 6

Definition at line 940 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG0_TILT_EN_MASK

#define BIT_APEX_CONFIG0_TILT_EN_MASK (0x1 << BIT_APEX_CONFIG0_TILT_EN_POS)

Definition at line 971 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG0_TILT_EN_POS

#define BIT_APEX_CONFIG0_TILT_EN_POS 4

Definition at line 970 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_MASK

#define BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_MASK 0x0F

Definition at line 1604 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_POS

#define BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_POS 0

Definition at line 1603 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_MASK

#define BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_MASK (0x0F << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS)

Definition at line 1629 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS

#define BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS 4

Definition at line 1628 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG2_PEDO_AMP_TH_MASK

#define BIT_APEX_CONFIG2_PEDO_AMP_TH_MASK (0x0F<<BIT_APEX_CONFIG2_PEDO_AMP_TH_POS)

Definition at line 1659 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG2_PEDO_AMP_TH_POS

#define BIT_APEX_CONFIG2_PEDO_AMP_TH_POS 4

Definition at line 1658 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_MASK

#define BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_MASK 0x0F

Definition at line 1684 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_POS

#define BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_POS 0

Definition at line 1683 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_MASK

#define BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_MASK 0x03

Definition at line 1716 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_POS

#define BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_POS 0

Definition at line 1715 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_MASK

#define BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_MASK (0x07<<BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS)

Definition at line 1699 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS

#define BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS 2

Definition at line 1698 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_MASK

#define BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_MASK (0x07<<BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS)

Definition at line 1694 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS

#define BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS 5

Definition at line 1693 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_MASK

#define BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_MASK (0x07<<BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS)

Definition at line 1747 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS

#define BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS 3

Definition at line 1746 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG4_TILT_WAIT_TIME_MASK

#define BIT_APEX_CONFIG4_TILT_WAIT_TIME_MASK (0x03<<BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS)

Definition at line 1734 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS

#define BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS 6

Definition at line 1733 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_MASK

#define BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_MASK (0x07<<BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS)

Definition at line 1769 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS

#define BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS 0

Definition at line 1768 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_MASK

#define BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_MASK (0x07<<BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS)

Definition at line 1791 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS

#define BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS 0

Definition at line 1790 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_MASK

#define BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_MASK 0x3

Definition at line 1818 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_POS

#define BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_POS 0

Definition at line 1817 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_MASK

#define BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_MASK (0x3F << BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS)

Definition at line 1812 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS

#define BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS 2

Definition at line 1811 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG8_TAP_TAVG_MASK

#define BIT_APEX_CONFIG8_TAP_TAVG_MASK (0x03 << BIT_APEX_CONFIG8_TAP_TAVG_POS)

Definition at line 1847 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG8_TAP_TAVG_POS

#define BIT_APEX_CONFIG8_TAP_TAVG_POS 3

Definition at line 1846 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG8_TAP_TMAX_MASK

#define BIT_APEX_CONFIG8_TAP_TMAX_MASK (0x03 << BIT_APEX_CONFIG8_TAP_TMAX_POS)

Definition at line 1835 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG8_TAP_TMAX_POS

#define BIT_APEX_CONFIG8_TAP_TMAX_POS 5

Definition at line 1834 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG8_TAP_TMIN_MASK

#define BIT_APEX_CONFIG8_TAP_TMIN_MASK 0x07

Definition at line 1859 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG8_TAP_TMIN_POS

#define BIT_APEX_CONFIG8_TAP_TMIN_POS 0

Definition at line 1858 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG9_SENSITIVITY_MODE_MASK

#define BIT_APEX_CONFIG9_SENSITIVITY_MODE_MASK 0x01

Definition at line 1878 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_CONFIG9_SENSITIVITY_MODE_POS

#define BIT_APEX_CONFIG9_SENSITIVITY_MODE_POS 0

Definition at line 1877 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_DATA3_ACTIVITY_CLASS_MASK

#define BIT_APEX_DATA3_ACTIVITY_CLASS_MASK 0x03

Definition at line 413 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_DATA3_ACTIVITY_CLASS_POS

#define BIT_APEX_DATA3_ACTIVITY_CLASS_POS 0

Definition at line 412 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_DATA3_DMP_IDLE_MASK

#define BIT_APEX_DATA3_DMP_IDLE_MASK (0x01 << BIT_APEX_DATA3_DMP_IDLE_POS)

Definition at line 424 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_DATA3_DMP_IDLE_POS

#define BIT_APEX_DATA3_DMP_IDLE_POS 2

Definition at line 423 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_DATA4_TAP_AXIS_MASK

#define BIT_APEX_DATA4_TAP_AXIS_MASK (0x03 << BIT_APEX_DATA4_TAP_AXIS_POS)

Definition at line 454 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_DATA4_TAP_AXIS_POS

#define BIT_APEX_DATA4_TAP_AXIS_POS 1

Definition at line 453 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_DATA4_TAP_DIR_MASK

#define BIT_APEX_DATA4_TAP_DIR_MASK 0x01

Definition at line 464 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_DATA4_TAP_DIR_POS

#define BIT_APEX_DATA4_TAP_DIR_POS 0

Definition at line 463 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_DATA4_TAP_NUM_MASK

#define BIT_APEX_DATA4_TAP_NUM_MASK (0x03 << BIT_APEX_DATA4_TAP_NUM_POS)

Definition at line 445 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_DATA4_TAP_NUM_POS

#define BIT_APEX_DATA4_TAP_NUM_POS 3

TAP status flags: non-zero value - tap detected bit0 - positive or negative edge bit1 and 2 - axis detected : 0-X ; 1-Y ; 2-Z bit3 and 4 - tap type : 1-single ; 2 -double

Definition at line 444 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_DATA5_DOUBLE_TAP_TIMING_MASK

#define BIT_APEX_DATA5_DOUBLE_TAP_TIMING_MASK (0x3F << BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS)

Definition at line 478 of file Ixm42xxxDefs.h.

## ◆ BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS

#define BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS 0

Definition at line 477 of file Ixm42xxxDefs.h.

## ◆ BIT_CHIP_CONFIG_RESET_MASK

#define BIT_CHIP_CONFIG_RESET_MASK BIT_DEVICE_CONFIG_RESET_MASK

Definition at line 311 of file Ixm42xxxDefs.h.

## ◆ BIT_CHIP_CONFIG_RESET_POS

#define BIT_CHIP_CONFIG_RESET_POS BIT_DEVICE_CONFIG_RESET_POS

Definition at line 312 of file Ixm42xxxDefs.h.

## ◆ BIT_CHIP_CONFIG_SPI_MODE_MASK

#define BIT_CHIP_CONFIG_SPI_MODE_MASK BIT_DEVICE_CONFIG_SPI_MODE_MASK

Definition at line 292 of file Ixm42xxxDefs.h.

## ◆ BIT_CHIP_CONFIG_SPI_MODE_POS

#define BIT_CHIP_CONFIG_SPI_MODE_POS BIT_DEVICE_CONFIG_SPI_MODE_POS

Definition at line 293 of file Ixm42xxxDefs.h.

## ◆ BIT_DATA_ENDIAN_MASK

#define BIT_DATA_ENDIAN_MASK (0x01 << BIT_DATA_ENDIAN_POS)

Definition at line 582 of file Ixm42xxxDefs.h.

## ◆ BIT_DATA_ENDIAN_POS

#define BIT_DATA_ENDIAN_POS 4

Definition at line 581 of file Ixm42xxxDefs.h.

## ◆ BIT_DEVICE_CONFIG_RESET_MASK

#define BIT_DEVICE_CONFIG_RESET_MASK 0x01

Definition at line 310 of file Ixm42xxxDefs.h.

## ◆ BIT_DEVICE_CONFIG_RESET_POS

#define BIT_DEVICE_CONFIG_RESET_POS 0

Definition at line 309 of file Ixm42xxxDefs.h.

## ◆ BIT_DEVICE_CONFIG_SPI_MODE_MASK

#define BIT_DEVICE_CONFIG_SPI_MODE_MASK (0x1 << BIT_DEVICE_CONFIG_SPI_MODE_POS)

Definition at line 291 of file Ixm42xxxDefs.h.

## ◆ BIT_DEVICE_CONFIG_SPI_MODE_POS

#define BIT_DEVICE_CONFIG_SPI_MODE_POS 4

Definition at line 290 of file Ixm42xxxDefs.h.

## ◆ BIT_DMP_MEM_ACCESS_EN

#define BIT_DMP_MEM_ACCESS_EN 0x08

Definition at line 1226 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG1_ACCEL_MASK

#define BIT_FIFO_CONFIG1_ACCEL_MASK 0x1

Definition at line 1088 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG1_ACCEL_POS

#define BIT_FIFO_CONFIG1_ACCEL_POS 0

Definition at line 1087 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG1_GYRO_MASK

#define BIT_FIFO_CONFIG1_GYRO_MASK (0x1 << BIT_FIFO_CONFIG1_GYRO_POS)

Definition at line 1078 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG1_GYRO_POS

#define BIT_FIFO_CONFIG1_GYRO_POS 1

Definition at line 1077 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG1_HIRES_MASK

#define BIT_FIFO_CONFIG1_HIRES_MASK (0x1 << BIT_FIFO_CONFIG1_HIRES_POS)

Definition at line 1048 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG1_HIRES_POS

#define BIT_FIFO_CONFIG1_HIRES_POS 4

Definition at line 1047 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_MASK

#define BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_MASK (0x1 << BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS)

Definition at line 1034 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS

#define BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS 6

Definition at line 1033 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG1_TEMP_MASK

#define BIT_FIFO_CONFIG1_TEMP_MASK (0x1 << BIT_FIFO_CONFIG1_TEMP_POS)

Definition at line 1068 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG1_TEMP_POS

#define BIT_FIFO_CONFIG1_TEMP_POS 2

Definition at line 1067 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG1_TMST_FSYNC_MASK

#define BIT_FIFO_CONFIG1_TMST_FSYNC_MASK (0x1 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS)

Definition at line 1058 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG1_TMST_FSYNC_POS

#define BIT_FIFO_CONFIG1_TMST_FSYNC_POS 3

Definition at line 1057 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG1_WM_GT_TH_MASK

#define BIT_FIFO_CONFIG1_WM_GT_TH_MASK (0x1 << BIT_FIFO_CONFIG1_WM_GT_TH_POS)

Definition at line 1038 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG1_WM_GT_TH_POS

#define BIT_FIFO_CONFIG1_WM_GT_TH_POS 5

Definition at line 1037 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG_MODE_MASK

#define BIT_FIFO_CONFIG_MODE_MASK (0x03 << BIT_FIFO_CONFIG_MODE_POS)

Definition at line 378 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_CONFIG_MODE_POS

#define BIT_FIFO_CONFIG_MODE_POS 6

Definition at line 377 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_COUNT_ENDIAN_MASK

#define BIT_FIFO_COUNT_ENDIAN_MASK (0x01 << BIT_FIFO_COUNT_ENDIAN_POS)

Definition at line 572 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_COUNT_ENDIAN_POS

#define BIT_FIFO_COUNT_ENDIAN_POS 5

Definition at line 571 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_COUNT_REC_MASK

#define BIT_FIFO_COUNT_REC_MASK (0x01 << BIT_FIFO_COUNT_REC_POS)

Definition at line 562 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_COUNT_REC_POS

#define BIT_FIFO_COUNT_REC_POS 6

Definition at line 561 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_MEM_RD_SYS

#define BIT_FIFO_MEM_RD_SYS 0x02

Definition at line 1228 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_MEM_WR_SER

#define BIT_FIFO_MEM_WR_SER 0x01

Definition at line 1229 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_SREG_INVALID_IND_MASK

#define BIT_FIFO_SREG_INVALID_IND_MASK (0x01 << BIT_FIFO_SREG_INVALID_IND_POS)

Definition at line 552 of file Ixm42xxxDefs.h.

## ◆ BIT_FIFO_SREG_INVALID_IND_POS

#define BIT_FIFO_SREG_INVALID_IND_POS 7

Definition at line 551 of file Ixm42xxxDefs.h.

## ◆ BIT_FSYNC_CONFIG_UI_SEL_MASK

#define BIT_FSYNC_CONFIG_UI_SEL_MASK (0x7 << BIT_FSYNC_CONFIG_UI_SEL_POS)

Definition at line 1103 of file Ixm42xxxDefs.h.

## ◆ BIT_FSYNC_CONFIG_UI_SEL_POS

#define BIT_FSYNC_CONFIG_UI_SEL_POS 4

Definition at line 1102 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_AAF_BITSHIFT_MASK

#define BIT_GYRO_AAF_BITSHIFT_MASK (0x0F << BIT_GYRO_AAF_BITSHIFT_POS)

Definition at line 1298 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_AAF_BITSHIFT_POS

#define BIT_GYRO_AAF_BITSHIFT_POS 4

Definition at line 1297 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_AAF_DELT_MASK

#define BIT_GYRO_AAF_DELT_MASK (0x3F << BIT_GYRO_AAF_DELT_POS)

Definition at line 1277 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_AAF_DELT_POS

#define BIT_GYRO_AAF_DELT_POS 0

Definition at line 1276 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_AAF_DELTSQR_MASK_HI

#define BIT_GYRO_AAF_DELTSQR_MASK_HI (0x0F << BIT_GYRO_AAF_DELTSQR_POS_HI)

Definition at line 1294 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_AAF_DELTSQR_MASK_LO

#define BIT_GYRO_AAF_DELTSQR_MASK_LO (0xFF << BIT_GYRO_AAF_DELTSQR_POS_LO)

Definition at line 1286 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_AAF_DELTSQR_POS_HI

#define BIT_GYRO_AAF_DELTSQR_POS_HI 0

Definition at line 1293 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_AAF_DELTSQR_POS_LO

#define BIT_GYRO_AAF_DELTSQR_POS_LO 0

Definition at line 1285 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_AAF_DIS_MASK

#define BIT_GYRO_AAF_DIS_MASK (0x01 << BIT_GYRO_AAF_DIS_POS)

Definition at line 1253 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_AAF_DIS_POS

#define BIT_GYRO_AAF_DIS_POS 1

Definition at line 1252 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_MASK

#define BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_MASK (0xF << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS)

Definition at line 823 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS

#define BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS 4

Definition at line 822 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_MASK

#define BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_MASK 0x0F

Definition at line 845 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_POS

#define BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_POS 0

Definition at line 844 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_CONFIG0_FS_SEL_MASK

#define BIT_GYRO_CONFIG0_FS_SEL_MASK (7 << BIT_GYRO_CONFIG0_FS_SEL_POS)

Definition at line 689 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_CONFIG0_FS_SEL_POS

#define BIT_GYRO_CONFIG0_FS_SEL_POS 5

Definition at line 688 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_CONFIG0_ODR_MASK

#define BIT_GYRO_CONFIG0_ODR_MASK 0x0F

Definition at line 718 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_CONFIG0_ODR_POS

#define BIT_GYRO_CONFIG0_ODR_POS 0

Definition at line 717 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_MASK

#define BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_MASK 0x3

Definition at line 813 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_POS

#define BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_POS 0

Definition at line 812 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_MASK

#define BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_MASK (0x3 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS)

Definition at line 802 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS

#define BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS 2

Definition at line 801 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_CONFIG1_TEMP_FILT_BW_MASK

#define BIT_GYRO_CONFIG1_TEMP_FILT_BW_MASK (0x7 << BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS)

Definition at line 798 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS

#define BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS 5

Definition at line 797 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_NF_DIS_MASK

#define BIT_GYRO_NF_DIS_MASK (0x01 << BIT_GYRO_NF_DIS_POS)

Definition at line 1263 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_NF_DIS_POS

#define BIT_GYRO_NF_DIS_POS 0

Definition at line 1262 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_X_OFFUSER_MASK_HI

#define BIT_GYRO_X_OFFUSER_MASK_HI (0x0F << BIT_GYRO_X_OFFUSER_POS_HI)

Definition at line 1981 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_X_OFFUSER_MASK_LO

#define BIT_GYRO_X_OFFUSER_MASK_LO (0xFF << BIT_GYRO_X_OFFUSER_POS_LO)

Definition at line 1973 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_X_OFFUSER_POS_HI

#define BIT_GYRO_X_OFFUSER_POS_HI 0

Definition at line 1980 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_X_OFFUSER_POS_LO

#define BIT_GYRO_X_OFFUSER_POS_LO 0

Definition at line 1972 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_X_ST_EN

#define BIT_GYRO_X_ST_EN 0x01

Definition at line 1219 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_Y_OFFUSER_MASK_HI

#define BIT_GYRO_Y_OFFUSER_MASK_HI (0x0F << BIT_GYRO_Y_OFFUSER_POS_HI)

Definition at line 1985 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_Y_OFFUSER_MASK_LO

#define BIT_GYRO_Y_OFFUSER_MASK_LO (0xFF << BIT_GYRO_Y_OFFUSER_POS_LO)

Definition at line 1993 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_Y_OFFUSER_POS_HI

#define BIT_GYRO_Y_OFFUSER_POS_HI 4

Definition at line 1984 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_Y_OFFUSER_POS_LO

#define BIT_GYRO_Y_OFFUSER_POS_LO 0

Definition at line 1992 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_Y_ST_EN

#define BIT_GYRO_Y_ST_EN 0x02

Definition at line 1218 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_Z_OFFUSER_MASK_HI

#define BIT_GYRO_Z_OFFUSER_MASK_HI (0x0F << BIT_GYRO_Z_OFFUSER_POS_HI)

Definition at line 2010 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_Z_OFFUSER_MASK_LO

#define BIT_GYRO_Z_OFFUSER_MASK_LO (0xFF << BIT_GYRO_Z_OFFUSER_POS_LO)

Definition at line 2002 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_Z_OFFUSER_POS_HI

#define BIT_GYRO_Z_OFFUSER_POS_HI 0

Definition at line 2009 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_Z_OFFUSER_POS_LO

#define BIT_GYRO_Z_OFFUSER_POS_LO 0

Definition at line 2001 of file Ixm42xxxDefs.h.

## ◆ BIT_GYRO_Z_ST_EN

#define BIT_GYRO_Z_ST_EN 0x04

Definition at line 1217 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_CONFIG1_ASY_RST_MASK

#define BIT_INT_CONFIG1_ASY_RST_MASK (0x1 << BIT_INT_CONFIG1_ASY_RST_POS)

Definition at line 1124 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_CONFIG1_ASY_RST_POS

#define BIT_INT_CONFIG1_ASY_RST_POS 4

Definition at line 1123 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_MASK

#define BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS)

Definition at line 353 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS

#define BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS 1

Definition at line 352 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_CONFIG_INT1_POLARITY_MASK

#define BIT_INT_CONFIG_INT1_POLARITY_MASK 0x01

Definition at line 363 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_CONFIG_INT1_POLARITY_POS

#define BIT_INT_CONFIG_INT1_POLARITY_POS 0

Definition at line 362 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_MASK

#define BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS)

Definition at line 333 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS

#define BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS 4

Definition at line 332 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_CONFIG_INT2_POLARITY_MASK

#define BIT_INT_CONFIG_INT2_POLARITY_MASK (0x01 << BIT_INT_CONFIG_INT2_POLARITY_POS)

Definition at line 343 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_CONFIG_INT2_POLARITY_POS

#define BIT_INT_CONFIG_INT2_POLARITY_POS 3

Definition at line 342 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_FIFO_FULL_IBI_EN_POS

#define BIT_INT_FIFO_FULL_IBI_EN_POS 1

Definition at line 1923 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_FIFO_FULL_INT_EN_POS

#define BIT_INT_FIFO_FULL_INT_EN_POS 1

Definition at line 1141 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_FIFO_THS_IBI_EN_POS

#define BIT_INT_FIFO_THS_IBI_EN_POS 2

Definition at line 1922 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_FIFO_THS_INT_EN_POS

#define BIT_INT_FIFO_THS_INT_EN_POS 2

Definition at line 1140 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_OIS1_DRDY_IBI_EN_POS

#define BIT_INT_OIS1_DRDY_IBI_EN_POS 6

Definition at line 1918 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_PLL_RDY_IBI_EN_POS

#define BIT_INT_PLL_RDY_IBI_EN_POS 4

Definition at line 1920 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_PLL_RDY_INT_EN_POS

#define BIT_INT_PLL_RDY_INT_EN_POS 5

Definition at line 1137 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_RESET_DONE_INT_EN_POS

#define BIT_INT_RESET_DONE_INT_EN_POS 4

Definition at line 1138 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SLEEP_DET_IBI_EN_POS

#define BIT_INT_SLEEP_DET_IBI_EN_POS 1

Definition at line 1956 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SLEEP_DET_INT_EN_POS

#define BIT_INT_SLEEP_DET_INT_EN_POS 1

Definition at line 1893 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SMD_IBI_EN_POS

#define BIT_INT_SMD_IBI_EN_POS 4

Definition at line 1938 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SMD_INT_EN_POS

#define BIT_INT_SMD_INT_EN_POS 3

Definition at line 1156 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE0_FIFO_FULL_INT1_EN

#define BIT_INT_SOURCE0_FIFO_FULL_INT1_EN 0x02

Definition at line 1149 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE0_FIFO_THS_INT1_EN

#define BIT_INT_SOURCE0_FIFO_THS_INT1_EN 0x04

Definition at line 1148 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE0_PLL_RDY_INT1_EN

#define BIT_INT_SOURCE0_PLL_RDY_INT1_EN 0x20

Definition at line 1145 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE0_RESET_DONE_INT1_EN

#define BIT_INT_SOURCE0_RESET_DONE_INT1_EN 0x10

Definition at line 1146 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE0_UI_AGC_RDY_INT1_EN

#define BIT_INT_SOURCE0_UI_AGC_RDY_INT1_EN 0x01

Definition at line 1150 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE0_UI_DRDY_INT1_EN

#define BIT_INT_SOURCE0_UI_DRDY_INT1_EN 0x08

Definition at line 1147 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE0_UI_FSYNC_INT1_EN

#define BIT_INT_SOURCE0_UI_FSYNC_INT1_EN 0x40

Definition at line 1144 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE10_SLEEP_DET_IBI_EN

#define BIT_INT_SOURCE10_SLEEP_DET_IBI_EN 0x02

Definition at line 1963 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE10_STEP_CNT_OVFL_IBI_EN

#define BIT_INT_SOURCE10_STEP_CNT_OVFL_IBI_EN 0x10

Definition at line 1960 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE10_STEP_DET_IBI_EN

#define BIT_INT_SOURCE10_STEP_DET_IBI_EN 0x20

Definition at line 1959 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE10_TAP_DET_IBI_EN

#define BIT_INT_SOURCE10_TAP_DET_IBI_EN 0x01

Definition at line 1964 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE10_TILT_DET_IBI_EN

#define BIT_INT_SOURCE10_TILT_DET_IBI_EN 0x08

Definition at line 1961 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE10_WAKE_DET_IBI_EN

#define BIT_INT_SOURCE10_WAKE_DET_IBI_EN 0x04

Definition at line 1962 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE1_SMD_INT1_EN

#define BIT_INT_SOURCE1_SMD_INT1_EN 0x08

Definition at line 1161 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE1_WOM_X_INT1_EN

#define BIT_INT_SOURCE1_WOM_X_INT1_EN 0x01

Definition at line 1164 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE1_WOM_Y_INT1_EN

#define BIT_INT_SOURCE1_WOM_Y_INT1_EN 0x02

Definition at line 1163 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE1_WOM_Z_INT1_EN

#define BIT_INT_SOURCE1_WOM_Z_INT1_EN 0x04

Definition at line 1162 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE2_OIS1_AGC_RDY_INT1_EN

#define BIT_INT_SOURCE2_OIS1_AGC_RDY_INT1_EN 0x04

Definition at line 1173 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE2_OIS1_DRDY_INT1_EN

#define BIT_INT_SOURCE2_OIS1_DRDY_INT1_EN 0x01

Definition at line 1175 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE2_OIS1_FSYNC_INT1_EN

#define BIT_INT_SOURCE2_OIS1_FSYNC_INT1_EN 0x02

Definition at line 1174 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE2_OIS2_AGC_RDY_INT1_EN

#define BIT_INT_SOURCE2_OIS2_AGC_RDY_INT1_EN 0x20

Definition at line 1170 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE2_OIS2_DRDY_INT1_EN

#define BIT_INT_SOURCE2_OIS2_DRDY_INT1_EN 0x08

Definition at line 1172 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE2_OIS2_FSYNC_INT1_EN

#define BIT_INT_SOURCE2_OIS2_FSYNC_INT1_EN 0x10

Definition at line 1171 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE3_FIFO_FULL_INT2_EN

#define BIT_INT_SOURCE3_FIFO_FULL_INT2_EN 0x02

Definition at line 1186 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE3_FIFO_THS_INT2_EN

#define BIT_INT_SOURCE3_FIFO_THS_INT2_EN 0x04

Definition at line 1185 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE3_PLL_RDY_INT2_EN

#define BIT_INT_SOURCE3_PLL_RDY_INT2_EN 0x20

Definition at line 1182 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE3_RESET_DONE_INT2_EN

#define BIT_INT_SOURCE3_RESET_DONE_INT2_EN 0x10

Definition at line 1183 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE3_UI_AGC_RDY_INT2_EN

#define BIT_INT_SOURCE3_UI_AGC_RDY_INT2_EN 0x01

Definition at line 1187 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE3_UI_DRDY_INT2_EN

#define BIT_INT_SOURCE3_UI_DRDY_INT2_EN 0x08

Definition at line 1184 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE3_UI_FSYNC_INT2_EN

#define BIT_INT_SOURCE3_UI_FSYNC_INT2_EN 0x40

Definition at line 1181 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE4_SMD_INT2_EN

#define BIT_INT_SOURCE4_SMD_INT2_EN 0x08

Definition at line 1193 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE4_WOM_X_INT2_EN

#define BIT_INT_SOURCE4_WOM_X_INT2_EN 0x01

Definition at line 1196 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE4_WOM_Y_INT2_EN

#define BIT_INT_SOURCE4_WOM_Y_INT2_EN 0x02

Definition at line 1195 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE4_WOM_Z_INT2_EN

#define BIT_INT_SOURCE4_WOM_Z_INT2_EN 0x04

Definition at line 1194 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE5_OIS1_AGC_RDY_INT2_EN

#define BIT_INT_SOURCE5_OIS1_AGC_RDY_INT2_EN 0x04

Definition at line 1205 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE5_OIS1_DRDY_INT2_EN

#define BIT_INT_SOURCE5_OIS1_DRDY_INT2_EN 0x01

Definition at line 1207 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE5_OIS1_FSYNC_INT2_EN

#define BIT_INT_SOURCE5_OIS1_FSYNC_INT2_EN 0x02

Definition at line 1206 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE5_OIS2_AGC_RDY_INT2_EN

#define BIT_INT_SOURCE5_OIS2_AGC_RDY_INT2_EN 0x20

Definition at line 1202 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE5_OIS2_DRDY_INT2_EN

#define BIT_INT_SOURCE5_OIS2_DRDY_INT2_EN 0x08

Definition at line 1204 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE5_OIS2_FSYNC_INT2_EN

#define BIT_INT_SOURCE5_OIS2_FSYNC_INT2_EN 0x10

Definition at line 1203 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE6_SLEEP_DET_INT1_EN

#define BIT_INT_SOURCE6_SLEEP_DET_INT1_EN 0x2

Definition at line 1900 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE6_STEP_CNT_OVFL_INT1_EN

#define BIT_INT_SOURCE6_STEP_CNT_OVFL_INT1_EN 0x10

Definition at line 1897 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE6_STEP_DET_INT1_EN

#define BIT_INT_SOURCE6_STEP_DET_INT1_EN 0x20

Definition at line 1896 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE6_TAP_DET_INT1_EN

#define BIT_INT_SOURCE6_TAP_DET_INT1_EN 0x1

Definition at line 1901 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE6_TILT_DET_INT1_EN

#define BIT_INT_SOURCE6_TILT_DET_INT1_EN 0x8

Definition at line 1898 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE6_WAKE_DET_INT1_EN

#define BIT_INT_SOURCE6_WAKE_DET_INT1_EN 0x4

Definition at line 1899 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE7_SLEEP_DET_INT2_EN

#define BIT_INT_SOURCE7_SLEEP_DET_INT2_EN 0x2

Definition at line 1911 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE7_STEP_CNT_OVFL_INT2_EN

#define BIT_INT_SOURCE7_STEP_CNT_OVFL_INT2_EN 0x10

Definition at line 1908 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE7_STEP_DET_INT2_EN

#define BIT_INT_SOURCE7_STEP_DET_INT2_EN 0x20

Definition at line 1907 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE7_TAP_DET_INT2_EN

#define BIT_INT_SOURCE7_TAP_DET_INT2_EN 0x1

Definition at line 1912 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE7_TILT_DET_INT2_EN

#define BIT_INT_SOURCE7_TILT_DET_INT2_EN 0x8

Definition at line 1909 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE7_WAKE_DET_INT2_EN

#define BIT_INT_SOURCE7_WAKE_DET_INT2_EN 0x4

Definition at line 1910 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE8_FIFO_FULL_IBI_EN

#define BIT_INT_SOURCE8_FIFO_FULL_IBI_EN 0x02

Definition at line 1931 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE8_FIFO_THS_IBI_EN

#define BIT_INT_SOURCE8_FIFO_THS_IBI_EN 0x04

Definition at line 1930 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE8_OIS1_DRDY_IBI_EN

#define BIT_INT_SOURCE8_OIS1_DRDY_IBI_EN 0x40

Definition at line 1926 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE8_PLL_RDY_IBI_EN

#define BIT_INT_SOURCE8_PLL_RDY_IBI_EN 0x10

Definition at line 1928 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE8_UI_AGC_RDY_IBI_EN

#define BIT_INT_SOURCE8_UI_AGC_RDY_IBI_EN 0x01

Definition at line 1932 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE8_UI_DRDY_IBI_EN

#define BIT_INT_SOURCE8_UI_DRDY_IBI_EN 0x08

Definition at line 1929 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE8_UI_FSYNC_IBI_EN

#define BIT_INT_SOURCE8_UI_FSYNC_IBI_EN 0x20

Definition at line 1927 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE9_SMD_IBI_EN

#define BIT_INT_SOURCE9_SMD_IBI_EN 0x10

Definition at line 1943 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE9_WOM_X_IBI_EN

#define BIT_INT_SOURCE9_WOM_X_IBI_EN 0x02

Definition at line 1946 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE9_WOM_Y_IBI_EN

#define BIT_INT_SOURCE9_WOM_Y_IBI_EN 0x04

Definition at line 1945 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_SOURCE9_WOM_Z_IBI_EN

#define BIT_INT_SOURCE9_WOM_Z_IBI_EN 0x08

Definition at line 1944 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS2_SMD_INT

#define BIT_INT_STATUS2_SMD_INT 0x08

Definition at line 484 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS2_WOM_X_INT

#define BIT_INT_STATUS2_WOM_X_INT 0x01

Definition at line 487 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS2_WOM_Y_INT

#define BIT_INT_STATUS2_WOM_Y_INT 0x02

Definition at line 486 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS2_WOM_Z_INT

#define BIT_INT_STATUS2_WOM_Z_INT 0x04

Definition at line 485 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS3_SLEEP_DET

#define BIT_INT_STATUS3_SLEEP_DET 0x02

Definition at line 497 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS3_STEP_CNT_OVFL

#define BIT_INT_STATUS3_STEP_CNT_OVFL 0x10

Definition at line 494 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS3_STEP_DET

#define BIT_INT_STATUS3_STEP_DET 0x20

Definition at line 493 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS3_TAP_DET

#define BIT_INT_STATUS3_TAP_DET 0x01

Definition at line 498 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS3_TILT_DET

#define BIT_INT_STATUS3_TILT_DET 0x08

Definition at line 495 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS3_WAKE_DET

#define BIT_INT_STATUS3_WAKE_DET 0x04

Definition at line 496 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS_AGC_RDY

#define BIT_INT_STATUS_AGC_RDY 0x01

Definition at line 398 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS_DRDY

#define BIT_INT_STATUS_DRDY 0x08

Definition at line 395 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS_FIFO_FULL

#define BIT_INT_STATUS_FIFO_FULL 0x02

Definition at line 397 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS_FIFO_THS

#define BIT_INT_STATUS_FIFO_THS 0x04

Definition at line 396 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS_OIS1_AGC_RDY

#define BIT_INT_STATUS_OIS1_AGC_RDY 0x01

Definition at line 1490 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS_OIS1_DRDY

#define BIT_INT_STATUS_OIS1_DRDY 0x02

Definition at line 1489 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS_OIS1_FSYNC

#define BIT_INT_STATUS_OIS1_FSYNC 0x04

Definition at line 1488 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS_OIS2_AGC_RDY

#define BIT_INT_STATUS_OIS2_AGC_RDY 0x01

Definition at line 1588 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS_OIS2_DRDY

#define BIT_INT_STATUS_OIS2_DRDY 0x02

Definition at line 1587 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS_OIS2_FSYNC

#define BIT_INT_STATUS_OIS2_FSYNC 0x04

Definition at line 1586 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS_PLL_RDY

#define BIT_INT_STATUS_PLL_RDY 0x20

Definition at line 393 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS_RESET_DONE

#define BIT_INT_STATUS_RESET_DONE 0x10

Definition at line 394 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STATUS_UI_FSYNC

#define BIT_INT_STATUS_UI_FSYNC 0x40

Definition at line 392 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STEP_CNT_OVFL_IBI_EN_POS

#define BIT_INT_STEP_CNT_OVFL_IBI_EN_POS 4

Definition at line 1953 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STEP_CNT_OVFL_INT_EN_POS

#define BIT_INT_STEP_CNT_OVFL_INT_EN_POS 4

Definition at line 1890 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STEP_DET_IBI_EN_POS

#define BIT_INT_STEP_DET_IBI_EN_POS 5

Definition at line 1952 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_STEP_DET_INT_EN_POS

#define BIT_INT_STEP_DET_INT_EN_POS 5

Definition at line 1889 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_TAP_DET_IBI_EN_POS

#define BIT_INT_TAP_DET_IBI_EN_POS 0

Definition at line 1957 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_TAP_DET_INT_EN_POS

#define BIT_INT_TAP_DET_INT_EN_POS 0

Definition at line 1894 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_TILT_DET_IBI_EN_POS

#define BIT_INT_TILT_DET_IBI_EN_POS 3

Definition at line 1954 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_TILT_DET_INT_EN_POS

#define BIT_INT_TILT_DET_INT_EN_POS 3

Definition at line 1891 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_UI_AGC_RDY_IBI_EN_POS

#define BIT_INT_UI_AGC_RDY_IBI_EN_POS 0

Definition at line 1924 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_UI_AGC_RDY_INT_EN_POS

#define BIT_INT_UI_AGC_RDY_INT_EN_POS 0

Definition at line 1142 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_UI_DRDY_IBI_EN_POS

#define BIT_INT_UI_DRDY_IBI_EN_POS 3

Definition at line 1921 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_UI_DRDY_INT_EN_POS

#define BIT_INT_UI_DRDY_INT_EN_POS 3

Definition at line 1139 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_UI_FSYNC_IBI_EN_POS

#define BIT_INT_UI_FSYNC_IBI_EN_POS 5

Definition at line 1919 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_UI_FSYNC_INT_EN_POS

#define BIT_INT_UI_FSYNC_INT_EN_POS 6

Definition at line 1136 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_WAKE_DET_IBI_EN_POS

#define BIT_INT_WAKE_DET_IBI_EN_POS 2

Definition at line 1955 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_WAKE_DET_INT_EN_POS

#define BIT_INT_WAKE_DET_INT_EN_POS 2

Definition at line 1892 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_WOM_X_IBI_EN_POS

#define BIT_INT_WOM_X_IBI_EN_POS 1

Definition at line 1941 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_WOM_X_INT_EN_POS

#define BIT_INT_WOM_X_INT_EN_POS 0

Definition at line 1159 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_WOM_Y_IBI_EN_POS

#define BIT_INT_WOM_Y_IBI_EN_POS 2

Definition at line 1940 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_WOM_Y_INT_EN_POS

#define BIT_INT_WOM_Y_INT_EN_POS 1

Definition at line 1158 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_WOM_Z_IBI_EN_POS

#define BIT_INT_WOM_Z_IBI_EN_POS 3

Definition at line 1939 of file Ixm42xxxDefs.h.

## ◆ BIT_INT_WOM_Z_INT_EN_POS

#define BIT_INT_WOM_Z_INT_EN_POS 2

Definition at line 1157 of file Ixm42xxxDefs.h.

## ◆ BIT_INTF_CONFIG4_AP_SPI_MASK

#define BIT_INTF_CONFIG4_AP_SPI_MASK (0x1 << BIT_INTF_CONFIG4_AP_SPI_POS)

Definition at line 1307 of file Ixm42xxxDefs.h.

## ◆ BIT_INTF_CONFIG4_AP_SPI_POS

#define BIT_INTF_CONFIG4_AP_SPI_POS 1

Definition at line 1306 of file Ixm42xxxDefs.h.

## ◆ BIT_INTF_CONFIG5_GPIO_PAD_SEL_MASK

#define BIT_INTF_CONFIG5_GPIO_PAD_SEL_MASK (0x3 << BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS)

Definition at line 1322 of file Ixm42xxxDefs.h.

## ◆ BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS

#define BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS 1

Definition at line 1321 of file Ixm42xxxDefs.h.

## ◆ BIT_INTF_CONFIG6_I3C_DDR_EN_MASK

#define BIT_INTF_CONFIG6_I3C_DDR_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_DDR_EN_POS)

Definition at line 1331 of file Ixm42xxxDefs.h.

## ◆ BIT_INTF_CONFIG6_I3C_DDR_EN_POS

#define BIT_INTF_CONFIG6_I3C_DDR_EN_POS 1

Definition at line 1330 of file Ixm42xxxDefs.h.

## ◆ BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_MASK

#define BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS)

Definition at line 1344 of file Ixm42xxxDefs.h.

## ◆ BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS

#define BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS 3

Definition at line 1343 of file Ixm42xxxDefs.h.

## ◆ BIT_INTF_CONFIG6_I3C_IBI_EN_MASK

#define BIT_INTF_CONFIG6_I3C_IBI_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_IBI_EN_POS)

Definition at line 1348 of file Ixm42xxxDefs.h.

## ◆ BIT_INTF_CONFIG6_I3C_IBI_EN_POS

#define BIT_INTF_CONFIG6_I3C_IBI_EN_POS 2

Definition at line 1347 of file Ixm42xxxDefs.h.

## ◆ BIT_INTF_CONFIG6_I3C_SDR_EN_MASK

#define BIT_INTF_CONFIG6_I3C_SDR_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_SDR_EN_POS)

Definition at line 1335 of file Ixm42xxxDefs.h.

## ◆ BIT_INTF_CONFIG6_I3C_SDR_EN_POS

#define BIT_INTF_CONFIG6_I3C_SDR_EN_POS 0

Definition at line 1334 of file Ixm42xxxDefs.h.

## ◆ BIT_MEM_OTP_ACCESS_EN

#define BIT_MEM_OTP_ACCESS_EN 0x04

Definition at line 1227 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS1_CONFIG1_ACCEL_EN_MASK

#define BIT_OIS1_CONFIG1_ACCEL_EN_MASK (0x1 << BIT_OIS1_CONFIG1_ACCEL_EN_POS)

Definition at line 1438 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS1_CONFIG1_ACCEL_EN_POS

#define BIT_OIS1_CONFIG1_ACCEL_EN_POS 0

Definition at line 1437 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_MASK

#define BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_MASK (0x1 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS)

Definition at line 1402 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS

#define BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS 5

Definition at line 1401 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS1_CONFIG1_DEC_MASK

#define BIT_OIS1_CONFIG1_DEC_MASK (0x7 << BIT_OIS1_CONFIG1_DEC_POS)

Definition at line 1412 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS1_CONFIG1_DEC_POS

#define BIT_OIS1_CONFIG1_DEC_POS 2

Definition at line 1411 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS1_CONFIG1_GYRO_EN_MASK

#define BIT_OIS1_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS1_CONFIG1_GYRO_EN_POS)

Definition at line 1428 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS1_CONFIG1_GYRO_EN_POS

#define BIT_OIS1_CONFIG1_GYRO_EN_POS 1

Definition at line 1427 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS1_CONFIG2_ACCEL_FS_SEL_MASK

#define BIT_OIS1_CONFIG2_ACCEL_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS)

Definition at line 1471 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS

#define BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS 0

Definition at line 1470 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS1_CONFIG2_GYRO_FS_SEL_MASK

#define BIT_OIS1_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS)

Definition at line 1453 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS

#define BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS 3

Definition at line 1452 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS2_CONFIG1_ACCEL_EN_MASK

#define BIT_OIS2_CONFIG1_ACCEL_EN_MASK (0x1 << BIT_OIS2_CONFIG1_ACCEL_EN_POS)

Definition at line 1535 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS2_CONFIG1_ACCEL_EN_POS

#define BIT_OIS2_CONFIG1_ACCEL_EN_POS 0

Definition at line 1534 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_MASK

#define BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_MASK (0x1 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS)

Definition at line 1499 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS

#define BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS 5

Definition at line 1498 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS2_CONFIG1_DEC_MASK

#define BIT_OIS2_CONFIG1_DEC_MASK (0x7 << BIT_OIS2_CONFIG1_DEC_POS)

Definition at line 1509 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS2_CONFIG1_DEC_POS

#define BIT_OIS2_CONFIG1_DEC_POS 2

Definition at line 1508 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS2_CONFIG1_GYRO_EN_MASK

#define BIT_OIS2_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS2_CONFIG1_GYRO_EN_POS)

Definition at line 1525 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS2_CONFIG1_GYRO_EN_POS

#define BIT_OIS2_CONFIG1_GYRO_EN_POS 1

Definition at line 1524 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS2_CONFIG2_ACCEL_FS_SEL_MASK

#define BIT_OIS2_CONFIG2_ACCEL_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS)

Definition at line 1568 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS

#define BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS 0

Definition at line 1567 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS2_CONFIG2_GYRO_FS_SEL_MASK

#define BIT_OIS2_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS)

Definition at line 1550 of file Ixm42xxxDefs.h.

## ◆ BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS

#define BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS 3

Definition at line 1549 of file Ixm42xxxDefs.h.

## ◆ BIT_PWR_MGMT_0_ACCEL_MODE_MASK

#define BIT_PWR_MGMT_0_ACCEL_MODE_MASK 0x03

Definition at line 673 of file Ixm42xxxDefs.h.

## ◆ BIT_PWR_MGMT_0_ACCEL_MODE_POS

#define BIT_PWR_MGMT_0_ACCEL_MODE_POS 0

Definition at line 672 of file Ixm42xxxDefs.h.

## ◆ BIT_PWR_MGMT_0_GYRO_MODE_MASK

#define BIT_PWR_MGMT_0_GYRO_MODE_MASK (0x03 << BIT_PWR_MGMT_0_GYRO_MODE_POS)

Definition at line 662 of file Ixm42xxxDefs.h.

## ◆ BIT_PWR_MGMT_0_GYRO_MODE_POS

#define BIT_PWR_MGMT_0_GYRO_MODE_POS 2

Definition at line 661 of file Ixm42xxxDefs.h.

## ◆ BIT_PWR_MGMT_0_IDLE_MASK

#define BIT_PWR_MGMT_0_IDLE_MASK (0x01 << BIT_PWR_MGMT_0_IDLE_POS)

Definition at line 652 of file Ixm42xxxDefs.h.

## ◆ BIT_PWR_MGMT_0_IDLE_POS

#define BIT_PWR_MGMT_0_IDLE_POS 4

Definition at line 651 of file Ixm42xxxDefs.h.

## ◆ BIT_PWR_MGMT_0_TEMP_MASK

#define BIT_PWR_MGMT_0_TEMP_MASK (0x01 << BIT_PWR_MGMT_0_TEMP_POS)

Definition at line 642 of file Ixm42xxxDefs.h.

## ◆ BIT_PWR_MGMT_0_TEMP_POS

#define BIT_PWR_MGMT_0_TEMP_POS 5

Definition at line 641 of file Ixm42xxxDefs.h.

## ◆ BIT_RTC_MODE_MASK

#define BIT_RTC_MODE_MASK (0x01 << BIT_RTC_MODE_POS)

Definition at line 627 of file Ixm42xxxDefs.h.

## ◆ BIT_RTC_MODE_POS

#define BIT_RTC_MODE_POS 2

Definition at line 626 of file Ixm42xxxDefs.h.

## ◆ BIT_SENSOR_CONFIG2_OIS_MODE_MASK

#define BIT_SENSOR_CONFIG2_OIS_MODE_MASK (0x03 << BIT_SENSOR_CONFIG2_OIS_MODE_POS)

Definition at line 1236 of file Ixm42xxxDefs.h.

## ◆ BIT_SENSOR_CONFIG2_OIS_MODE_POS

#define BIT_SENSOR_CONFIG2_OIS_MODE_POS 4

Definition at line 1235 of file Ixm42xxxDefs.h.

## ◆ BIT_SIGNAL_PATH_RESET_DMP_INIT_MASK

#define BIT_SIGNAL_PATH_RESET_DMP_INIT_MASK (0x01 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS)

Definition at line 507 of file Ixm42xxxDefs.h.

## ◆ BIT_SIGNAL_PATH_RESET_DMP_INIT_POS

#define BIT_SIGNAL_PATH_RESET_DMP_INIT_POS 6

Definition at line 506 of file Ixm42xxxDefs.h.

## ◆ BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_MASK

#define BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_MASK (0x01 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS)

Definition at line 517 of file Ixm42xxxDefs.h.

## ◆ BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS

#define BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS 5

Definition at line 516 of file Ixm42xxxDefs.h.

## ◆ BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_MASK

#define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_MASK (0x01 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS)

Definition at line 537 of file Ixm42xxxDefs.h.

## ◆ BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS

#define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS 1

Definition at line 536 of file Ixm42xxxDefs.h.

## ◆ BIT_SIGNAL_PATH_RESET_TMST_STROBE_MASK

#define BIT_SIGNAL_PATH_RESET_TMST_STROBE_MASK (0x01 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS)

Definition at line 527 of file Ixm42xxxDefs.h.

## ◆ BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS

#define BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS 2

Definition at line 526 of file Ixm42xxxDefs.h.

## ◆ BIT_SMD_CONFIG_SMD_MODE_MASK

#define BIT_SMD_CONFIG_SMD_MODE_MASK 0x3

Definition at line 1019 of file Ixm42xxxDefs.h.

## ◆ BIT_SMD_CONFIG_SMD_MODE_POS

#define BIT_SMD_CONFIG_SMD_MODE_POS 0

Definition at line 1018 of file Ixm42xxxDefs.h.

## ◆ BIT_SMD_CONFIG_WOM_INT_MODE_MASK

#define BIT_SMD_CONFIG_WOM_INT_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_INT_MODE_POS)

Definition at line 999 of file Ixm42xxxDefs.h.

## ◆ BIT_SMD_CONFIG_WOM_INT_MODE_POS

#define BIT_SMD_CONFIG_WOM_INT_MODE_POS 3

Definition at line 998 of file Ixm42xxxDefs.h.

## ◆ BIT_SMD_CONFIG_WOM_MODE_MASK

#define BIT_SMD_CONFIG_WOM_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_MODE_POS)

Definition at line 1009 of file Ixm42xxxDefs.h.

## ◆ BIT_SMD_CONFIG_WOM_MODE_POS

#define BIT_SMD_CONFIG_WOM_MODE_POS 2

Definition at line 1008 of file Ixm42xxxDefs.h.

## ◆ BIT_SPI_MODE_OIS1_MASK

#define BIT_SPI_MODE_OIS1_MASK (0x01 << BIT_SPI_MODE_OIS1_POS)

Definition at line 602 of file Ixm42xxxDefs.h.

## ◆ BIT_SPI_MODE_OIS1_POS

#define BIT_SPI_MODE_OIS1_POS 2

Definition at line 601 of file Ixm42xxxDefs.h.

## ◆ BIT_SPI_MODE_OIS2_MASK

#define BIT_SPI_MODE_OIS2_MASK (0x01 << BIT_SPI_MODE_OIS2_POS)

Definition at line 592 of file Ixm42xxxDefs.h.

## ◆ BIT_SPI_MODE_OIS2_POS

#define BIT_SPI_MODE_OIS2_POS 3

Definition at line 591 of file Ixm42xxxDefs.h.

## ◆ BIT_ST_REGULATOR_EN

#define BIT_ST_REGULATOR_EN 0x40

Definition at line 1213 of file Ixm42xxxDefs.h.

## ◆ BIT_TMST_CONFIG_RESOL_MASK

#define BIT_TMST_CONFIG_RESOL_MASK (0x1 << BIT_TMST_CONFIG_RESOL_POS)

Definition at line 896 of file Ixm42xxxDefs.h.

## ◆ BIT_TMST_CONFIG_RESOL_POS

#define BIT_TMST_CONFIG_RESOL_POS 3

Definition at line 895 of file Ixm42xxxDefs.h.

## ◆ BIT_TMST_CONFIG_TMST_EN_MASK

#define BIT_TMST_CONFIG_TMST_EN_MASK 0x1

Definition at line 916 of file Ixm42xxxDefs.h.

## ◆ BIT_TMST_CONFIG_TMST_EN_POS

#define BIT_TMST_CONFIG_TMST_EN_POS 0

Definition at line 915 of file Ixm42xxxDefs.h.

## ◆ BIT_TMST_CONFIG_TMST_FSYNC_MASK

#define BIT_TMST_CONFIG_TMST_FSYNC_MASK (0x1 << BIT_TMST_CONFIG_TMST_FSYNC_POS)

Definition at line 906 of file Ixm42xxxDefs.h.

## ◆ BIT_TMST_CONFIG_TMST_FSYNC_POS

#define BIT_TMST_CONFIG_TMST_FSYNC_POS 1

Definition at line 905 of file Ixm42xxxDefs.h.

## ◆ BIT_TMST_CONFIG_TMST_TO_REGS_EN_MASK

#define BIT_TMST_CONFIG_TMST_TO_REGS_EN_MASK (0x1 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS)

Definition at line 886 of file Ixm42xxxDefs.h.

## ◆ BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS

#define BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS 4

Definition at line 885 of file Ixm42xxxDefs.h.

## ◆ FIFO_16BYTES_PACKET_SIZE

#define FIFO_16BYTES_PACKET_SIZE (FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + FIFO_TS_FSYNC_SIZE)

Definition at line 223 of file Ixm42xxxDefs.h.

## ◆ FIFO_20BYTES_PACKET_SIZE

#define FIFO_20BYTES_PACKET_SIZE

Value:
(FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + FIFO_TS_FSYNC_SIZE +\
FIFO_TEMP_HIGH_RES_SIZE + FIFO_ACCEL_GYRO_HIGH_RES_SIZE)

Definition at line 224 of file Ixm42xxxDefs.h.

## ◆ FIFO_ACCEL_DATA_SIZE

#define FIFO_ACCEL_DATA_SIZE ACCEL_DATA_SIZE

Definition at line 216 of file Ixm42xxxDefs.h.

## ◆ FIFO_ACCEL_GYRO_HIGH_RES_SIZE

#define FIFO_ACCEL_GYRO_HIGH_RES_SIZE 3

Definition at line 221 of file Ixm42xxxDefs.h.

## ◆ FIFO_GYRO_DATA_SIZE

#define FIFO_GYRO_DATA_SIZE GYRO_DATA_SIZE

Definition at line 217 of file Ixm42xxxDefs.h.

## ◆ FIFO_HEADER_ACC

#define FIFO_HEADER_ACC 0x40

Definition at line 233 of file Ixm42xxxDefs.h.

## ◆ FIFO_HEADER_FSYNC

#define FIFO_HEADER_FSYNC 0x04

Definition at line 229 of file Ixm42xxxDefs.h.

## ◆ FIFO_HEADER_GYRO

#define FIFO_HEADER_GYRO 0x20

Definition at line 232 of file Ixm42xxxDefs.h.

## ◆ FIFO_HEADER_HEADER_20

#define FIFO_HEADER_HEADER_20 0x10

Definition at line 231 of file Ixm42xxxDefs.h.

## ◆ FIFO_HEADER_MSG

#define FIFO_HEADER_MSG 0x80

Definition at line 234 of file Ixm42xxxDefs.h.

## ◆ FIFO_HEADER_ODR_ACCEL

#define FIFO_HEADER_ODR_ACCEL 0x01

Definition at line 227 of file Ixm42xxxDefs.h.

## ◆ FIFO_HEADER_ODR_GYRO

#define FIFO_HEADER_ODR_GYRO 0x02

Definition at line 228 of file Ixm42xxxDefs.h.

## ◆ FIFO_HEADER_SIZE

#define FIFO_HEADER_SIZE 1

Definition at line 215 of file Ixm42xxxDefs.h.

## ◆ FIFO_HEADER_TMST

#define FIFO_HEADER_TMST 0x08

Definition at line 230 of file Ixm42xxxDefs.h.

## ◆ FIFO_TEMP_DATA_SIZE

#define FIFO_TEMP_DATA_SIZE 1

Definition at line 218 of file Ixm42xxxDefs.h.

## ◆ FIFO_TEMP_HIGH_RES_SIZE

#define FIFO_TEMP_HIGH_RES_SIZE 1

Definition at line 220 of file Ixm42xxxDefs.h.

## ◆ FIFO_TS_FSYNC_SIZE

#define FIFO_TS_FSYNC_SIZE 2

Definition at line 219 of file Ixm42xxxDefs.h.

## ◆ GYRO_DATA_SIZE

#define GYRO_DATA_SIZE 6

Definition at line 212 of file Ixm42xxxDefs.h.

## ◆ I3C_IBI_PAYLOAD_ALL

#define I3C_IBI_PAYLOAD_ALL 0xFF

Definition at line 257 of file Ixm42xxxDefs.h.

## ◆ I3C_IBI_PAYLOAD_CAT_APEX1

#define I3C_IBI_PAYLOAD_CAT_APEX1 0x08

Definition at line 262 of file Ixm42xxxDefs.h.

## ◆ I3C_IBI_PAYLOAD_CAT_APEX2

#define I3C_IBI_PAYLOAD_CAT_APEX2 0x10

Definition at line 261 of file Ixm42xxxDefs.h.

## ◆ I3C_IBI_PAYLOAD_CAT_ERROR

#define I3C_IBI_PAYLOAD_CAT_ERROR 0x20

Definition at line 260 of file Ixm42xxxDefs.h.

## ◆ I3C_IBI_PAYLOAD_CAT_FIFO

#define I3C_IBI_PAYLOAD_CAT_FIFO 0x02

Definition at line 264 of file Ixm42xxxDefs.h.

## ◆ I3C_IBI_PAYLOAD_CAT_MISC

#define I3C_IBI_PAYLOAD_CAT_MISC 0x40

Definition at line 259 of file Ixm42xxxDefs.h.

## ◆ I3C_IBI_PAYLOAD_CAT_OIS1_DRDY

#define I3C_IBI_PAYLOAD_CAT_OIS1_DRDY 0x04

Definition at line 263 of file Ixm42xxxDefs.h.

## ◆ I3C_IBI_PAYLOAD_CAT_UI_DRDY

#define I3C_IBI_PAYLOAD_CAT_UI_DRDY 0x01

Definition at line 265 of file Ixm42xxxDefs.h.

## ◆ I3C_IBI_PAYLOAD_TIMEC

#define I3C_IBI_PAYLOAD_TIMEC 0x80

Definition at line 258 of file Ixm42xxxDefs.h.

## ◆ ICM40608_WHOAMI

#define ICM40608_WHOAMI 0x39

Definition at line 38 of file Ixm42xxxDefs.h.

## ◆ ICM42600_WHOAMI

#define ICM42600_WHOAMI 0x40

Definition at line 39 of file Ixm42xxxDefs.h.

## ◆ ICM42602_WHOAMI

#define ICM42602_WHOAMI 0x41

Definition at line 40 of file Ixm42xxxDefs.h.

## ◆ ICM42605_WHOAMI

#define ICM42605_WHOAMI 0x42

Definition at line 41 of file Ixm42xxxDefs.h.

## ◆ ICM42608_WHOAMI

#define ICM42608_WHOAMI 0x48

Definition at line 45 of file Ixm42xxxDefs.h.

## ◆ ICM42622_WHOAMI

#define ICM42622_WHOAMI 0x46

Definition at line 42 of file Ixm42xxxDefs.h.

## ◆ ICM42686_WHOAMI

#define ICM42686_WHOAMI 0x44

Definition at line 43 of file Ixm42xxxDefs.h.

## ◆ ICM42688_WHOAMI

#define ICM42688_WHOAMI 0x47

Definition at line 44 of file Ixm42xxxDefs.h.

## ◆ IIM42652_WHOAMI

#define IIM42652_WHOAMI 0x6F

Definition at line 46 of file Ixm42xxxDefs.h.

## ◆ INVALID_VALUE_FIFO

#define INVALID_VALUE_FIFO ((int16_t)0x8000)

Definition at line 237 of file Ixm42xxxDefs.h.

## ◆ INVALID_VALUE_FIFO_1B

#define INVALID_VALUE_FIFO_1B ((int8_t)0x80)

Definition at line 238 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG7_TAP_MIN_JERK_THR_281MG_DEFAULT

#define IXM42XXX_APEX_CONFIG7_TAP_MIN_JERK_THR_281MG_DEFAULT 0x11

Definition at line 1814 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_FIFO_CONFIG_MODE_SNAPSHOT

#define IXM42XXX_FIFO_CONFIG_MODE_SNAPSHOT = IXM42XXX_FIFO_CONFIG_MODE_STOP_ON_FULL;

Definition at line 387 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ACCEL_CONFIG0

#define MPUREG_ACCEL_CONFIG0 0x50

Definition at line 114 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ACCEL_CONFIG1

#define MPUREG_ACCEL_CONFIG1 0x53

Definition at line 117 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ACCEL_CONFIG_STATIC0_B2

#define MPUREG_ACCEL_CONFIG_STATIC0_B2 0x39

Definition at line 154 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ACCEL_CONFIG_STATIC2_B2

#define MPUREG_ACCEL_CONFIG_STATIC2_B2 0x03

Definition at line 151 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ACCEL_CONFIG_STATIC3_B2

#define MPUREG_ACCEL_CONFIG_STATIC3_B2 0x04

Definition at line 152 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ACCEL_CONFIG_STATIC4_B2

#define MPUREG_ACCEL_CONFIG_STATIC4_B2 0x05

Definition at line 153 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ACCEL_DATA_X0_OIS1_B2

#define MPUREG_ACCEL_DATA_X0_OIS1_B2 0x49

Definition at line 162 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ACCEL_DATA_X0_OIS2_B2

#define MPUREG_ACCEL_DATA_X0_OIS2_B2 0x5E

Definition at line 170 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ACCEL_DATA_X0_UI

#define MPUREG_ACCEL_DATA_X0_UI 0x1F

Definition at line 91 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ACCEL_GYRO_CONFIG0

#define MPUREG_ACCEL_GYRO_CONFIG0 0x52

Definition at line 116 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ACCEL_WOM_X_THR_B4

#define MPUREG_ACCEL_WOM_X_THR_B4 0x4A

Definition at line 186 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ACCEL_WOM_Y_THR_B4

#define MPUREG_ACCEL_WOM_Y_THR_B4 0x4B

Definition at line 187 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ACCEL_WOM_Z_THR_B4

#define MPUREG_ACCEL_WOM_Z_THR_B4 0x4C

Definition at line 188 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_CONFIG0

#define MPUREG_APEX_CONFIG0 0x56

Definition at line 119 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_CONFIG1_B4

#define MPUREG_APEX_CONFIG1_B4 0x40

Definition at line 177 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_CONFIG2_B4

#define MPUREG_APEX_CONFIG2_B4 0x41

Definition at line 178 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_CONFIG3_B4

#define MPUREG_APEX_CONFIG3_B4 0x42

Definition at line 179 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_CONFIG4_B4

#define MPUREG_APEX_CONFIG4_B4 0x43

Definition at line 180 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_CONFIG5_B4

#define MPUREG_APEX_CONFIG5_B4 0x44

Definition at line 181 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_CONFIG6_B4

#define MPUREG_APEX_CONFIG6_B4 0x45

Definition at line 182 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_CONFIG7_B4

#define MPUREG_APEX_CONFIG7_B4 0x46

Definition at line 183 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_CONFIG8_B4

#define MPUREG_APEX_CONFIG8_B4 0x47

Definition at line 184 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_CONFIG9_B4

#define MPUREG_APEX_CONFIG9_B4 0x48

Definition at line 185 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_DATA0

#define MPUREG_APEX_DATA0 0x31

Definition at line 101 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_DATA1

#define MPUREG_APEX_DATA1 0x32

Definition at line 102 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_DATA2

#define MPUREG_APEX_DATA2 0x33

Definition at line 103 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_DATA3

#define MPUREG_APEX_DATA3 0x34

Definition at line 104 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_DATA4

#define MPUREG_APEX_DATA4 0x35

Definition at line 105 of file Ixm42xxxDefs.h.

## ◆ MPUREG_APEX_DATA5

#define MPUREG_APEX_DATA5 0x36

Definition at line 106 of file Ixm42xxxDefs.h.

## ◆ MPUREG_CHIP_CONFIG

#define MPUREG_CHIP_CONFIG MPUREG_DEVICE_CONFIG

Definition at line 86 of file Ixm42xxxDefs.h.

## ◆ MPUREG_DEVICE_CONFIG

#define MPUREG_DEVICE_CONFIG 0x11

Definition at line 85 of file Ixm42xxxDefs.h.

## ◆ MPUREG_DRIVE_CONFIG

#define MPUREG_DRIVE_CONFIG 0x13

Definition at line 87 of file Ixm42xxxDefs.h.

## ◆ MPUREG_FIFO_BYTE_COUNT1

#define MPUREG_FIFO_BYTE_COUNT1 MPUREG_FIFO_COUNTH

Definition at line 97 of file Ixm42xxxDefs.h.

## ◆ MPUREG_FIFO_BYTE_COUNT2

#define MPUREG_FIFO_BYTE_COUNT2 MPUREG_FIFO_COUNTL

Definition at line 99 of file Ixm42xxxDefs.h.

## ◆ MPUREG_FIFO_CONFIG

#define MPUREG_FIFO_CONFIG 0x16

Definition at line 89 of file Ixm42xxxDefs.h.

## ◆ MPUREG_FIFO_CONFIG1

#define MPUREG_FIFO_CONFIG1 0x5F

Definition at line 121 of file Ixm42xxxDefs.h.

## ◆ MPUREG_FIFO_CONFIG2

#define MPUREG_FIFO_CONFIG2 0x60

Definition at line 122 of file Ixm42xxxDefs.h.

## ◆ MPUREG_FIFO_COUNTH

#define MPUREG_FIFO_COUNTH 0x2E

Definition at line 96 of file Ixm42xxxDefs.h.

## ◆ MPUREG_FIFO_COUNTL

#define MPUREG_FIFO_COUNTL 0x2F

Definition at line 98 of file Ixm42xxxDefs.h.

## ◆ MPUREG_FIFO_DATA

#define MPUREG_FIFO_DATA 0x30

Definition at line 100 of file Ixm42xxxDefs.h.

## ◆ MPUREG_FIFO_LOST_PKT0

#define MPUREG_FIFO_LOST_PKT0 0x6C

Definition at line 132 of file Ixm42xxxDefs.h.

## ◆ MPUREG_FSYNC_CONFIG

#define MPUREG_FSYNC_CONFIG 0x62

Definition at line 123 of file Ixm42xxxDefs.h.

## ◆ MPUREG_GYRO_CONFIG0

#define MPUREG_GYRO_CONFIG0 0x4F

Definition at line 113 of file Ixm42xxxDefs.h.

## ◆ MPUREG_GYRO_CONFIG1

#define MPUREG_GYRO_CONFIG1 0x51

Definition at line 115 of file Ixm42xxxDefs.h.

## ◆ MPUREG_GYRO_CONFIG_STATIC2_B1

#define MPUREG_GYRO_CONFIG_STATIC2_B1 0x0B

Definition at line 138 of file Ixm42xxxDefs.h.

## ◆ MPUREG_GYRO_CONFIG_STATIC3_B1

#define MPUREG_GYRO_CONFIG_STATIC3_B1 0x0C

Definition at line 139 of file Ixm42xxxDefs.h.

## ◆ MPUREG_GYRO_CONFIG_STATIC4_B1

#define MPUREG_GYRO_CONFIG_STATIC4_B1 0x0D

Definition at line 140 of file Ixm42xxxDefs.h.

## ◆ MPUREG_GYRO_CONFIG_STATIC5_B1

#define MPUREG_GYRO_CONFIG_STATIC5_B1 0x0E

Definition at line 141 of file Ixm42xxxDefs.h.

## ◆ MPUREG_GYRO_DATA_X0_OIS1_B2

#define MPUREG_GYRO_DATA_X0_OIS1_B2 0x4F

Definition at line 163 of file Ixm42xxxDefs.h.

## ◆ MPUREG_GYRO_DATA_X0_OIS2_B2

#define MPUREG_GYRO_DATA_X0_OIS2_B2 0x64

Definition at line 171 of file Ixm42xxxDefs.h.

## ◆ MPUREG_GYRO_DATA_X0_UI

#define MPUREG_GYRO_DATA_X0_UI 0x25

Definition at line 92 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_CONFIG

#define MPUREG_INT_CONFIG 0x14

Definition at line 88 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_CONFIG0

#define MPUREG_INT_CONFIG0 0x63

Definition at line 124 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_CONFIG1

#define MPUREG_INT_CONFIG1 0x64

Definition at line 125 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_SOURCE0

#define MPUREG_INT_SOURCE0 0x65

Definition at line 126 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_SOURCE1

#define MPUREG_INT_SOURCE1 0x66

Definition at line 127 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_SOURCE10_B4

#define MPUREG_INT_SOURCE10_B4 0x51

Definition at line 193 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_SOURCE2

#define MPUREG_INT_SOURCE2 0x67

Definition at line 128 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_SOURCE3

#define MPUREG_INT_SOURCE3 0x68

Definition at line 129 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_SOURCE4

#define MPUREG_INT_SOURCE4 0x69

Definition at line 130 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_SOURCE5

#define MPUREG_INT_SOURCE5 0x6A

Definition at line 131 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_SOURCE6_B4

#define MPUREG_INT_SOURCE6_B4 0x4D

Definition at line 189 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_SOURCE7_B4

#define MPUREG_INT_SOURCE7_B4 0x4E

Definition at line 190 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_SOURCE8_B4

#define MPUREG_INT_SOURCE8_B4 0x4F

Definition at line 191 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_SOURCE9_B4

#define MPUREG_INT_SOURCE9_B4 0x50

Definition at line 192 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_STATUS

#define MPUREG_INT_STATUS 0x2D

Definition at line 95 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_STATUS2

#define MPUREG_INT_STATUS2 0x37

Definition at line 107 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_STATUS3

#define MPUREG_INT_STATUS3 0x38

Definition at line 108 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_STATUS_OIS1_B2

#define MPUREG_INT_STATUS_OIS1_B2 0x57

Definition at line 164 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INT_STATUS_OIS2_B2

#define MPUREG_INT_STATUS_OIS2_B2 0x6C

Definition at line 172 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INTF_CONFIG0

#define MPUREG_INTF_CONFIG0 0x4C

Definition at line 110 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INTF_CONFIG1

#define MPUREG_INTF_CONFIG1 0x4D

Definition at line 111 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INTF_CONFIG4_B1

#define MPUREG_INTF_CONFIG4_B1 0x7A

Definition at line 146 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INTF_CONFIG5_B1

#define MPUREG_INTF_CONFIG5_B1 0x7B

Definition at line 147 of file Ixm42xxxDefs.h.

## ◆ MPUREG_INTF_CONFIG6_B1

#define MPUREG_INTF_CONFIG6_B1 0x7C

Definition at line 148 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OFFSET_USER_0_B4

#define MPUREG_OFFSET_USER_0_B4 0x77

Definition at line 194 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OFFSET_USER_1_B4

#define MPUREG_OFFSET_USER_1_B4 0x78

Definition at line 195 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OFFSET_USER_2_B4

#define MPUREG_OFFSET_USER_2_B4 0x79

Definition at line 196 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OFFSET_USER_3_B4

#define MPUREG_OFFSET_USER_3_B4 0x7A

Definition at line 197 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OFFSET_USER_4_B4

#define MPUREG_OFFSET_USER_4_B4 0x7B

Definition at line 198 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OFFSET_USER_5_B4

#define MPUREG_OFFSET_USER_5_B4 0x7C

Definition at line 199 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OFFSET_USER_6_B4

#define MPUREG_OFFSET_USER_6_B4 0x7D

Definition at line 200 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OFFSET_USER_7_B4

#define MPUREG_OFFSET_USER_7_B4 0x7E

Definition at line 201 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OFFSET_USER_8_B4

#define MPUREG_OFFSET_USER_8_B4 0x7F

Definition at line 202 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OIS1_CONFIG1_B2

#define MPUREG_OIS1_CONFIG1_B2 0x44

Definition at line 159 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OIS1_CONFIG2_B2

#define MPUREG_OIS1_CONFIG2_B2 0x45

Definition at line 160 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OIS1_CONFIG3_B2

#define MPUREG_OIS1_CONFIG3_B2 0x46

Definition at line 161 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OIS2_CONFIG1_B2

#define MPUREG_OIS2_CONFIG1_B2 0x59

Definition at line 167 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OIS2_CONFIG2_B2

#define MPUREG_OIS2_CONFIG2_B2 0x5A

Definition at line 168 of file Ixm42xxxDefs.h.

## ◆ MPUREG_OIS2_CONFIG3_B2

#define MPUREG_OIS2_CONFIG3_B2 0x5B

Definition at line 169 of file Ixm42xxxDefs.h.

## ◆ MPUREG_PWR_MGMT_0

#define MPUREG_PWR_MGMT_0 0x4E

Definition at line 112 of file Ixm42xxxDefs.h.

## ◆ MPUREG_REG_BANK_SEL

#define MPUREG_REG_BANK_SEL 0x76

Definition at line 135 of file Ixm42xxxDefs.h.

## ◆ MPUREG_SELF_TEST_CONFIG

#define MPUREG_SELF_TEST_CONFIG 0x70

Definition at line 133 of file Ixm42xxxDefs.h.

## ◆ MPUREG_SIGNAL_PATH_RESET

#define MPUREG_SIGNAL_PATH_RESET 0x4B

Definition at line 109 of file Ixm42xxxDefs.h.

## ◆ MPUREG_SMD_CONFIG

#define MPUREG_SMD_CONFIG 0x57

Definition at line 120 of file Ixm42xxxDefs.h.

## ◆ MPUREG_TEMP_DATA0_UI

#define MPUREG_TEMP_DATA0_UI 0x1D

Definition at line 90 of file Ixm42xxxDefs.h.

## ◆ MPUREG_TMST_CONFIG

#define MPUREG_TMST_CONFIG 0x54

Definition at line 118 of file Ixm42xxxDefs.h.

## ◆ MPUREG_TMST_FSYNC1

#define MPUREG_TMST_FSYNC1 MPUREG_TMST_FSYNCH

Definition at line 94 of file Ixm42xxxDefs.h.

## ◆ MPUREG_TMST_FSYNCH

#define MPUREG_TMST_FSYNCH 0x2B

Definition at line 93 of file Ixm42xxxDefs.h.

## ◆ MPUREG_TMST_VAL0_B1

#define MPUREG_TMST_VAL0_B1 0x62

Definition at line 145 of file Ixm42xxxDefs.h.

## ◆ MPUREG_WHO_AM_I

#define MPUREG_WHO_AM_I 0x75

Definition at line 134 of file Ixm42xxxDefs.h.

## ◆ MPUREG_XA_ST_DATA_B2

#define MPUREG_XA_ST_DATA_B2 0x3B

Definition at line 155 of file Ixm42xxxDefs.h.

## ◆ MPUREG_XG_ST_DATA_B1

#define MPUREG_XG_ST_DATA_B1 0x5F

Definition at line 142 of file Ixm42xxxDefs.h.

## ◆ MPUREG_YA_ST_DATA_B2

#define MPUREG_YA_ST_DATA_B2 0x3C

Definition at line 156 of file Ixm42xxxDefs.h.

## ◆ MPUREG_YG_ST_DATA_B1

#define MPUREG_YG_ST_DATA_B1 0x60

Definition at line 143 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ZA_ST_DATA_B2

#define MPUREG_ZA_ST_DATA_B2 0x3D

Definition at line 157 of file Ixm42xxxDefs.h.

## ◆ MPUREG_ZG_ST_DATA_B1

#define MPUREG_ZG_ST_DATA_B1 0x61

Definition at line 144 of file Ixm42xxxDefs.h.

## ◆ TEMP_DATA_SIZE

#define TEMP_DATA_SIZE 2

Definition at line 213 of file Ixm42xxxDefs.h.

## Enumeration Type Documentation

## ◆ IXM42XXX_ACCEL_AAF_DIS_t

enum IXM42XXX_ACCEL_AAF_DIS_t

Enumerator
IXM42XXX_ACCEL_AAF_EN |
IXM42XXX_ACCEL_AAF_DIS |

Definition at line 1363 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_ACCEL_CONFIG0_FS_SEL_t

enum IXM42XXX_ACCEL_CONFIG0_FS_SEL_t

Accelerometer FSR selection.

Enumerator
IXM42XXX_ACCEL_CONFIG0_FS_SEL_RESERVED |
IXM42XXX_ACCEL_CONFIG0_FS_SEL_2g | 2g
IXM42XXX_ACCEL_CONFIG0_FS_SEL_4g | 4g
IXM42XXX_ACCEL_CONFIG0_FS_SEL_8g | 8g
IXM42XXX_ACCEL_CONFIG0_FS_SEL_16g | 16g

Definition at line 749 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_ACCEL_CONFIG0_ODR_t

enum IXM42XXX_ACCEL_CONFIG0_ODR_t

Accelerometer ODR selection.

Enumerator
IXM42XXX_ACCEL_CONFIG0_ODR_500_HZ | 500 Hz (2 ms)
IXM42XXX_ACCEL_CONFIG0_ODR_1_5625_HZ | 1.5625 Hz (640 ms)
IXM42XXX_ACCEL_CONFIG0_ODR_3_125_HZ | 3.125 Hz (320 ms)
IXM42XXX_ACCEL_CONFIG0_ODR_6_25_HZ | 6.25 Hz (160 ms)
IXM42XXX_ACCEL_CONFIG0_ODR_12_5_HZ | 12.5 Hz (80 ms)
IXM42XXX_ACCEL_CONFIG0_ODR_25_HZ | 25 Hz (40 ms)
IXM42XXX_ACCEL_CONFIG0_ODR_50_HZ | 50 Hz (20 ms)
IXM42XXX_ACCEL_CONFIG0_ODR_100_HZ | 100 Hz (10 ms)
IXM42XXX_ACCEL_CONFIG0_ODR_200_HZ | 200 Hz (5 ms)
IXM42XXX_ACCEL_CONFIG0_ODR_1_KHZ | 1 KHz (1 ms)
IXM42XXX_ACCEL_CONFIG0_ODR_2_KHZ | 2 KHz (500 us)
IXM42XXX_ACCEL_CONFIG0_ODR_4_KHZ | 4 KHz (250 us)
IXM42XXX_ACCEL_CONFIG0_ODR_8_KHZ | 8 KHz (125 us)
IXM42XXX_ACCEL_CONFIG0_ODR_16_KHZ | 16 KHz (62.5 us)
IXM42XXX_ACCEL_CONFIG0_ODR_32_KHZ | 32 KHz (31.25 us)

Definition at line 772 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_t

enum IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_t

Enumerator
IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_1ST_ORDER |
IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_2ND_ORDER |
IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_3RD_ORDER |

Definition at line 868 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG0_DMP_ODR_t

enum IXM42XXX_APEX_CONFIG0_DMP_ODR_t

DMP ODR selection.

Enumerator
IXM42XXX_APEX_CONFIG0_DMP_ODR_25Hz | 25Hz (40ms)
IXM42XXX_APEX_CONFIG0_DMP_ODR_50Hz | 50Hz (20ms)
IXM42XXX_APEX_CONFIG0_DMP_ODR_RESERVED | Reserved

Definition at line 985 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_t

enum IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_t

Enumerator
IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_EN |
IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_DIS |

Definition at line 933 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG0_PEDO_EN_t

enum IXM42XXX_APEX_CONFIG0_PEDO_EN_t

Enumerator
IXM42XXX_APEX_CONFIG0_PEDO_EN_EN |
IXM42XXX_APEX_CONFIG0_PEDO_EN_DIS |

Definition at line 953 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG0_R2W_EN_t

enum IXM42XXX_APEX_CONFIG0_R2W_EN_t

Enumerator
IXM42XXX_APEX_CONFIG0_R2W_EN_EN |
IXM42XXX_APEX_CONFIG0_R2W_EN_DIS |

Definition at line 963 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG0_TAP_ENABLE_t

enum IXM42XXX_APEX_CONFIG0_TAP_ENABLE_t

Enumerator
IXM42XXX_APEX_CONFIG0_TAP_ENABLE_EN |
IXM42XXX_APEX_CONFIG0_TAP_ENABLE_DIS |

Definition at line 943 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG0_TILT_EN_t

enum IXM42XXX_APEX_CONFIG0_TILT_EN_t

Enumerator
IXM42XXX_APEX_CONFIG0_TILT_EN_EN |
IXM42XXX_APEX_CONFIG0_TILT_EN_DIS |

Definition at line 973 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t

enum IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t

Enumerator
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_0S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_4S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_8S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_12S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_16S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_20S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_24S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_28S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_32S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_36S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_40S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_44S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_48S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_52S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_56S |
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_60S |

Definition at line 1606 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t

enum IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t

Enumerator
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1006632MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1174405MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1342177MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1509949MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1677721MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1845493MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2013265MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2181038MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2348810MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2516582MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2684354MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2852126MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3019898MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3187671MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3355443MG |
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3523215MG |

Definition at line 1631 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_t

enum IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_t

Enumerator
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1006632_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1140850_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1275068_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1409286_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1543503_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1677721_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1811939_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1946157_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2080374_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2214592_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2348810_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2483027_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2617245_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2751463_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2885681_MG |
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_3019898_MG |

Definition at line 1661 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t

enum IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t

Enumerator
IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_90 |
IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_107 |
IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_136 |
IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_159 |

Definition at line 1718 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t

enum IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t

Enumerator
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_50_SAMPLES |
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_75_SAMPLES |
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_100_SAMPLES |
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_125_SAMPLES |
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_150_SAMPLES |
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_175_SAMPLES |
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_200_SAMPLES |
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_225_SAMPLES |

Definition at line 1701 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t

enum IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t

Enumerator
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_1_28S |
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_2_56S |
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_3_84S |
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_5_12S |
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_6_4S |
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_7_68S |
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_8_96S |
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_10_24S |

Definition at line 1749 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_t

enum IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_t

Enumerator
IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_0 |
IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_2S |
IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_4S |
IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_6S |

Definition at line 1736 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t

enum IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t

Enumerator
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_0 |
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_1 |
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_2 |
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_3 |
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_4 |
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_5 |
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_6 |
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_7 |

Definition at line 1771 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t

enum IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t

Enumerator
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_32S |
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_64S |
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_96S |
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_28S |
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_6S |
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_92S |
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_24S |
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_56S |

Definition at line 1793 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t

enum IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t

Enumerator
IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_12 |
IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_25 |
IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_37 |
IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_50 |

Definition at line 1820 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG8_TAP_TAVG_t

enum IXM42XXX_APEX_CONFIG8_TAP_TAVG_t

Enumerator
IXM42XXX_APEX_CONFIG8_TAP_TAVG_1SAMPLE |
IXM42XXX_APEX_CONFIG8_TAP_TAVG_2SAMPLE |
IXM42XXX_APEX_CONFIG8_TAP_TAVG_4SAMPLE |
IXM42XXX_APEX_CONFIG8_TAP_TAVG_8SAMPLE |

Definition at line 1849 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG8_TAP_TMAX_t

enum IXM42XXX_APEX_CONFIG8_TAP_TMAX_t

Enumerator
IXM42XXX_APEX_CONFIG8_TAP_TMAX_250MS |
IXM42XXX_APEX_CONFIG8_TAP_TMAX_375MS |
IXM42XXX_APEX_CONFIG8_TAP_TMAX_500MS |
IXM42XXX_APEX_CONFIG8_TAP_TMAX_625MS |

Definition at line 1837 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG8_TAP_TMIN_t

enum IXM42XXX_APEX_CONFIG8_TAP_TMIN_t

Enumerator
IXM42XXX_APEX_CONFIG8_TAP_TMIN_125MS |
IXM42XXX_APEX_CONFIG8_TAP_TMIN_140MS |
IXM42XXX_APEX_CONFIG8_TAP_TMIN_156MS |
IXM42XXX_APEX_CONFIG8_TAP_TMIN_171MS |
IXM42XXX_APEX_CONFIG8_TAP_TMIN_187MS |
IXM42XXX_APEX_CONFIG8_TAP_TMIN_203MS |
IXM42XXX_APEX_CONFIG8_TAP_TMIN_218MS |
IXM42XXX_APEX_CONFIG8_TAP_TMIN_234MS |

Definition at line 1861 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_t

enum IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_t

Enumerator
IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_NORMAL |
IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_RESERVED |

Definition at line 1879 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_t

enum IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_t

Enumerator
IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_OTHER |
IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_WALK |
IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_RUN |

Definition at line 415 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_DATA3_DMP_IDLE_OFF_t

enum IXM42XXX_APEX_DATA3_DMP_IDLE_OFF_t

Enumerator
IXM42XXX_APEX_DATA3_DMP_IDLE_ON |
IXM42XXX_APEX_DATA3_DMP_IDLE_OFF |

Definition at line 426 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_DATA4_TAP_AXIS_t

enum IXM42XXX_APEX_DATA4_TAP_AXIS_t

Enumerator
IXM42XXX_APEX_DATA4_TAP_AXIS_Z |
IXM42XXX_APEX_DATA4_TAP_AXIS_Y |
IXM42XXX_APEX_DATA4_TAP_AXIS_X |

Definition at line 455 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_DATA4_TAP_DIR_t

enum IXM42XXX_APEX_DATA4_TAP_DIR_t

Enumerator
IXM42XXX_APEX_DATA4_TAP_DIR_POSITIVE |
IXM42XXX_APEX_DATA4_TAP_DIR_NEGATIVE |

Definition at line 465 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_APEX_DATA4_TAP_NUM_t

enum IXM42XXX_APEX_DATA4_TAP_NUM_t

Enumerator
IXM42XXX_APEX_DATA4_TAP_NUM_DOUBLE |
IXM42XXX_APEX_DATA4_TAP_NUM_SINGLE |

Definition at line 446 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_CHIP_CONFIG_RESET_t

enum IXM42XXX_CHIP_CONFIG_RESET_t

Enumerator
IXM42XXX_CHIP_CONFIG_RESET_EN |
IXM42XXX_CHIP_CONFIG_RESET_NONE |

Definition at line 320 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_CHIP_CONFIG_SPI_MODE_t

enum IXM42XXX_CHIP_CONFIG_SPI_MODE_t

Enumerator
IXM42XXX_CHIP_CONFIG_SPI_MODE_1_2 |
IXM42XXX_CHIP_CONFIG_SPI_MODE_0_3 |

Definition at line 301 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_DEVICE_CONFIG_RESET_t

enum IXM42XXX_DEVICE_CONFIG_RESET_t

Enumerator
IXM42XXX_DEVICE_CONFIG_RESET_EN |
IXM42XXX_DEVICE_CONFIG_RESET_NONE |

Definition at line 314 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_DEVICE_CONFIG_SPI_MODE_t

enum IXM42XXX_DEVICE_CONFIG_SPI_MODE_t

Enumerator
IXM42XXX_DEVICE_CONFIG_SPI_MODE_1_2 |
IXM42XXX_DEVICE_CONFIG_SPI_MODE_0_3 |

Definition at line 295 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_FIFO_CONFIG1_ACCEL_t

enum IXM42XXX_FIFO_CONFIG1_ACCEL_t

Enumerator
IXM42XXX_FIFO_CONFIG1_ACCEL_EN |
IXM42XXX_FIFO_CONFIG1_ACCEL_DIS |

Definition at line 1090 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_FIFO_CONFIG1_GYRO_t

enum IXM42XXX_FIFO_CONFIG1_GYRO_t

Enumerator
IXM42XXX_FIFO_CONFIG1_GYRO_EN |
IXM42XXX_FIFO_CONFIG1_GYRO_DIS |

Definition at line 1080 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_FIFO_CONFIG1_HIRES_t

enum IXM42XXX_FIFO_CONFIG1_HIRES_t

Enumerator
IXM42XXX_FIFO_CONFIG1_HIRES_EN |
IXM42XXX_FIFO_CONFIG1_HIRES_DIS |

Definition at line 1050 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_FIFO_CONFIG1_TEMP_t

enum IXM42XXX_FIFO_CONFIG1_TEMP_t

Enumerator
IXM42XXX_FIFO_CONFIG1_TEMP_EN |
IXM42XXX_FIFO_CONFIG1_TEMP_DIS |

Definition at line 1070 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_t

enum IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_t

Enumerator
IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_EN |
IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_DIS |

Definition at line 1060 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_FIFO_CONFIG1_WM_GT_t

enum IXM42XXX_FIFO_CONFIG1_WM_GT_t

Enumerator
IXM42XXX_FIFO_CONFIG1_WM_GT_TH_EN |
IXM42XXX_FIFO_CONFIG1_WM_GT_TH_DIS |

Definition at line 1040 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_FIFO_CONFIG_MODE_t

enum IXM42XXX_FIFO_CONFIG_MODE_t

Enumerator
IXM42XXX_FIFO_CONFIG_MODE_STOP_ON_FULL |
IXM42XXX_FIFO_CONFIG_MODE_STREAM |
IXM42XXX_FIFO_CONFIG_MODE_BYPASS |

Definition at line 380 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_FSYNC_CONFIG_UI_SEL_t

enum IXM42XXX_FSYNC_CONFIG_UI_SEL_t

Enumerator
IXM42XXX_FSYNC_CONFIG_UI_SEL_NO |
IXM42XXX_FSYNC_CONFIG_UI_SEL_TEMP |
IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_X |
IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_Y |
IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_Z |
IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_X |
IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_Y |
IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_Z |

Definition at line 1105 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_GYRO_AAF_DIS_t

enum IXM42XXX_GYRO_AAF_DIS_t

Enumerator
IXM42XXX_GYRO_AAF_EN |
IXM42XXX_GYRO_AAF_DIS |

Definition at line 1255 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t

enum IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t

Enumerator
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_16 |
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_1 |

Definition at line 837 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t

enum IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t

Enumerator
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_40 |
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_20 |
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_16 |
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_10 |
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_8 |
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_5 |
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_4 |
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_2 |

Definition at line 825 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t

enum IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t

Enumerator
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_40 |
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_20 |
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_16 |
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_10 |
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_8 |
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_5 |
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_4 |
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_2 |

Definition at line 847 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_GYRO_CONFIG0_FS_SEL_t

enum IXM42XXX_GYRO_CONFIG0_FS_SEL_t

Gyroscope FSR selection.

Enumerator
IXM42XXX_GYRO_CONFIG0_FS_SEL_16dps | 16dps
IXM42XXX_GYRO_CONFIG0_FS_SEL_31dps | 31dps
IXM42XXX_GYRO_CONFIG0_FS_SEL_62dps | 62dps
IXM42XXX_GYRO_CONFIG0_FS_SEL_125dps | 125dps
IXM42XXX_GYRO_CONFIG0_FS_SEL_250dps | 250dps
IXM42XXX_GYRO_CONFIG0_FS_SEL_500dps | 500dps
IXM42XXX_GYRO_CONFIG0_FS_SEL_1000dps | 1000dps
IXM42XXX_GYRO_CONFIG0_FS_SEL_2000dps | 2000dps

Definition at line 693 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_GYRO_CONFIG0_ODR_t

enum IXM42XXX_GYRO_CONFIG0_ODR_t

Gyroscope ODR selection.

Enumerator
IXM42XXX_GYRO_CONFIG0_ODR_500_HZ | 500 Hz (2 ms)
IXM42XXX_GYRO_CONFIG0_ODR_12_5_HZ | 12.5 Hz (80 ms)
IXM42XXX_GYRO_CONFIG0_ODR_25_HZ | 25 Hz (40 ms)
IXM42XXX_GYRO_CONFIG0_ODR_50_HZ | 50 Hz (20 ms)
IXM42XXX_GYRO_CONFIG0_ODR_100_HZ | 100 Hz (10 ms)
IXM42XXX_GYRO_CONFIG0_ODR_200_HZ | 200 Hz (5 ms)
IXM42XXX_GYRO_CONFIG0_ODR_1_KHZ | 1 KHz (1 ms)
IXM42XXX_GYRO_CONFIG0_ODR_2_KHZ | 2 KHz (500 us)
IXM42XXX_GYRO_CONFIG0_ODR_4_KHZ | 4 KHz (250 us)
IXM42XXX_GYRO_CONFIG0_ODR_8_KHZ | 8 KHz (125 us)
IXM42XXX_GYRO_CONFIG0_ODR_16_KHZ | 16 KHz (62.5 us)
IXM42XXX_GYRO_CONFIG0_ODR_32_KHZ | 32 KHz (31.25 us)

Definition at line 722 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_t

enum IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_t

Enumerator
IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_1ST_ORDER |
IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_2ND_ORDER |
IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_3RD_ORDER |

Definition at line 804 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_GYRO_NF_DIS_t

enum IXM42XXX_GYRO_NF_DIS_t

Enumerator
IXM42XXX_GYRO_NF_EN |
IXM42XXX_GYRO_NF_DIS |

Definition at line 1264 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_INT_CONFIG1_ASY_RST_t

enum IXM42XXX_INT_CONFIG1_ASY_RST_t

Enumerator
IXM42XXX_INT_CONFIG1_ASY_RST_DISABLED |
IXM42XXX_INT_CONFIG1_ASY_RST_ENABLED |

Definition at line 1126 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t

enum IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t

Enumerator
IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_PP |
IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_OD |

Definition at line 355 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_INT_CONFIG_INT1_POLARITY_t

enum IXM42XXX_INT_CONFIG_INT1_POLARITY_t

Enumerator
IXM42XXX_INT_CONFIG_INT1_POLARITY_HIGH |
IXM42XXX_INT_CONFIG_INT1_POLARITY_LOW |

Definition at line 365 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_t

enum IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_t

Enumerator
IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_PP |
IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_OD |

Definition at line 335 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_INT_CONFIG_INT2_POLARITY_t

enum IXM42XXX_INT_CONFIG_INT2_POLARITY_t

Enumerator
IXM42XXX_INT_CONFIG_INT2_POLARITY_HIGH |
IXM42XXX_INT_CONFIG_INT2_POLARITY_LOW |

Definition at line 345 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_INTF_CONFIG0_DATA_ENDIAN_t

enum IXM42XXX_INTF_CONFIG0_DATA_ENDIAN_t

Enumerator
IXM42XXX_INTF_CONFIG0_DATA_BIG_ENDIAN |
IXM42XXX_INTF_CONFIG0_DATA_LITTLE_ENDIAN |

Definition at line 584 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t

enum IXM42XXX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t

Enumerator
IXM42XXX_INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN |
IXM42XXX_INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN |

Definition at line 574 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_t

enum IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_t

Enumerator
IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_RECORD |
IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_BYTE |

Definition at line 564 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t

enum IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t

Enumerator
IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_DIS |
IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_EN |

Definition at line 554 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_t

enum IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_t

Enumerator
IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_1_2 |
IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_0_3 |

Definition at line 604 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_t

enum IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_t

Enumerator
IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_1_2 |
IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_0_3 |

Definition at line 594 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_t

enum IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_t

Enumerator
IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_WUOSC |
IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_RCOSC |

Definition at line 619 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_INTF_CONFIG1_RTC_MODE_t

enum IXM42XXX_INTF_CONFIG1_RTC_MODE_t

Enumerator
IXM42XXX_INTF_CONFIG1_RTC_MODE_DIS |
IXM42XXX_INTF_CONFIG1_RTC_MODE_EN |

Definition at line 629 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_INTF_CONFIG4_AP_SPI_t

enum IXM42XXX_INTF_CONFIG4_AP_SPI_t

Enumerator
IXM42XXX_INTF_CONFIG4_AP_SPI4W |
IXM42XXX_INTF_CONFIG4_AP_SPI3W |

Definition at line 1309 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_OIS1_CONFIG1_ACCEL_EN_t

enum IXM42XXX_OIS1_CONFIG1_ACCEL_EN_t

Enumerator
IXM42XXX_OIS1_CONFIG1_ACCEL_EN |
IXM42XXX_OIS1_CONFIG1_ACCEL_DIS |

Definition at line 1440 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_t

enum IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_t

Enumerator
IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC |
IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC |

Definition at line 1404 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_OIS1_CONFIG1_DEC_t

enum IXM42XXX_OIS1_CONFIG1_DEC_t

OIS1 rate selection (base clock fixed by OTP divided by decimator value)

Enumerator
IXM42XXX_OIS1_CONFIG1_DEC_1 | OTP_OIS_clock / 1
IXM42XXX_OIS1_CONFIG1_DEC_2 | OTP_OIS_clock / 2
IXM42XXX_OIS1_CONFIG1_DEC_4 | OTP_OIS_clock / 4
IXM42XXX_OIS1_CONFIG1_DEC_8 | OTP_OIS_clock / 8
IXM42XXX_OIS1_CONFIG1_DEC_16 | OTP_OIS_clock / 16
IXM42XXX_OIS1_CONFIG1_DEC_32 | OTP_OIS_clock / 32

Definition at line 1416 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_OIS1_CONFIG1_GYRO_EN_t

enum IXM42XXX_OIS1_CONFIG1_GYRO_EN_t

Enumerator
IXM42XXX_OIS1_CONFIG1_GYRO_EN |
IXM42XXX_OIS1_CONFIG1_GYRO_DIS |

Definition at line 1430 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_t

enum IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_t

OIS1 accelerometer FSR selection.

Enumerator
IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_RESERVED |
IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_2g | 2g
IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_4g | 4g
IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_8g | 8g
IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_16g | 16g

Definition at line 1475 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_t

enum IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_t

OIS1 gyroscope FSR selection.

Enumerator
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_16dps | 15.625 dps
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_31dps | 31.25 dps
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_62dps | 62.5 dps
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_125dps | 125 dps
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_250dps | 250 dps
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_500dps | 500 dps
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_1000dps | 1000 dps
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_2000dps | 2000 dps

Definition at line 1457 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_OIS2_CONFIG1_ACCEL_EN_t

enum IXM42XXX_OIS2_CONFIG1_ACCEL_EN_t

Enumerator
IXM42XXX_OIS2_CONFIG1_ACCEL_EN |
IXM42XXX_OIS2_CONFIG1_ACCEL_DIS |

Definition at line 1537 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_t

enum IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_t

Enumerator
IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC |
IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC |

Definition at line 1501 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_OIS2_CONFIG1_DEC_t

enum IXM42XXX_OIS2_CONFIG1_DEC_t

OIS2 rate selection (base clock fixed by OTP divided by decimator value)

Enumerator
IXM42XXX_OIS2_CONFIG1_DEC_1 | OTP_OIS_clock / 1
IXM42XXX_OIS2_CONFIG1_DEC_2 | OTP_OIS_clock / 2
IXM42XXX_OIS2_CONFIG1_DEC_4 | OTP_OIS_clock / 4
IXM42XXX_OIS2_CONFIG1_DEC_8 | OTP_OIS_clock / 8
IXM42XXX_OIS2_CONFIG1_DEC_16 | OTP_OIS_clock / 16
IXM42XXX_OIS2_CONFIG1_DEC_32 | OTP_OIS_clock / 32

Definition at line 1513 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_OIS2_CONFIG1_GYRO_EN_t

enum IXM42XXX_OIS2_CONFIG1_GYRO_EN_t

Enumerator
IXM42XXX_OIS2_CONFIG1_GYRO_EN |
IXM42XXX_OIS2_CONFIG1_GYRO_DIS |

Definition at line 1527 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_t

enum IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_t

OIS2 accelerometer FSR selection.

Enumerator
IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_RESERVED |
IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_2g | 2g
IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_4g | 4g
IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_8g | 8g
IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_16g | 16g

Definition at line 1572 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_t

enum IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_t

OIS2 gyroscope FSR selection.

Enumerator
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_16dps | 15.625 dps
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_31dps | 31.25 dps
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_62dps | 62.5 dps
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_125dps | 125 dps
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_250dps | 250 dps
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_500dps | 500 dps
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_1000dps | 1000 dps
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_2000dps | 2000 dps

Definition at line 1554 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_PWR_MGMT_0_ACCEL_MODE_t

enum IXM42XXX_PWR_MGMT_0_ACCEL_MODE_t

Enumerator
IXM42XXX_PWR_MGMT_0_ACCEL_MODE_LN |
IXM42XXX_PWR_MGMT_0_ACCEL_MODE_LP |
IXM42XXX_PWR_MGMT_0_ACCEL_MODE_OFF |

Definition at line 675 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_PWR_MGMT_0_GYRO_MODE_t

enum IXM42XXX_PWR_MGMT_0_GYRO_MODE_t

Enumerator
IXM42XXX_PWR_MGMT_0_GYRO_MODE_LN |
IXM42XXX_PWR_MGMT_0_GYRO_MODE_STANDBY |
IXM42XXX_PWR_MGMT_0_GYRO_MODE_OFF |

Definition at line 664 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_PWR_MGMT_0_IDLE_t

enum IXM42XXX_PWR_MGMT_0_IDLE_t

Enumerator
IXM42XXX_PWR_MGMT_0_IDLE_DIS |
IXM42XXX_PWR_MGMT_0_IDLE_EN |

Definition at line 654 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_PWR_MGMT_0_TEMP_t

enum IXM42XXX_PWR_MGMT_0_TEMP_t

Enumerator
IXM42XXX_PWR_MGMT_0_TEMP_DIS |
IXM42XXX_PWR_MGMT_0_TEMP_EN |

Definition at line 644 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_SENSOR_CONFIG2_OIS_MODE_t

enum IXM42XXX_SENSOR_CONFIG2_OIS_MODE_t

Enumerator
IXM42XXX_SENSOR_CONFIG2_OIS_MODE_32KHZ |
IXM42XXX_SENSOR_CONFIG2_OIS_MODE_8KHZ |
IXM42XXX_SENSOR_CONFIG2_OIS_MODE_DIS |

Definition at line 1238 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_t

enum IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_t

Enumerator
IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_EN |
IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_DIS |

Definition at line 509 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_t

enum IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_t

Enumerator
IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN |
IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_DIS |

Definition at line 519 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_t

enum IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_t

Enumerator
IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_EN |
IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_DIS |

Definition at line 539 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_t

enum IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_t

Enumerator
IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_EN |
IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_DIS |

Definition at line 529 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_SMD_CONFIG_SMD_MODE_t

enum IXM42XXX_SMD_CONFIG_SMD_MODE_t

Enumerator
IXM42XXX_SMD_CONFIG_SMD_MODE_LONG |
IXM42XXX_SMD_CONFIG_SMD_MODE_SHORT |
IXM42XXX_SMD_CONFIG_SMD_MODE_WOM |
IXM42XXX_SMD_CONFIG_SMD_MODE_DISABLED |

Definition at line 1021 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_SMD_CONFIG_WOM_INT_MODE_t

enum IXM42XXX_SMD_CONFIG_WOM_INT_MODE_t

Enumerator
IXM42XXX_SMD_CONFIG_WOM_INT_MODE_ANDED |
IXM42XXX_SMD_CONFIG_WOM_INT_MODE_ORED |

Definition at line 1001 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_SMD_CONFIG_WOM_MODE_t

enum IXM42XXX_SMD_CONFIG_WOM_MODE_t

Enumerator
IXM42XXX_SMD_CONFIG_WOM_MODE_CMP_PREV |
IXM42XXX_SMD_CONFIG_WOM_MODE_CMP_INIT |

Definition at line 1011 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_TMST_CONFIG_RESOL_t

enum IXM42XXX_TMST_CONFIG_RESOL_t

Enumerator
IXM42XXX_TMST_CONFIG_RESOL_16us |
IXM42XXX_TMST_CONFIG_RESOL_1us |

Definition at line 898 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_TMST_CONFIG_TMST_EN_t

enum IXM42XXX_TMST_CONFIG_TMST_EN_t

Enumerator
IXM42XXX_TMST_CONFIG_TMST_EN |
IXM42XXX_TMST_CONFIG_TMST_DIS |

Definition at line 918 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_TMST_CONFIG_TMST_FSYNC_EN_t

enum IXM42XXX_TMST_CONFIG_TMST_FSYNC_EN_t

Enumerator
IXM42XXX_TMST_CONFIG_TMST_FSYNC_EN |
IXM42XXX_TMST_CONFIG_TMST_FSYNC_DIS |

Definition at line 908 of file Ixm42xxxDefs.h.

## ◆ IXM42XXX_TMST_CONFIG_TMST_TO_REGS_EN_t

enum IXM42XXX_TMST_CONFIG_TMST_TO_REGS_EN_t

Enumerator
IXM42XXX_TMST_CONFIG_TMST_TO_REGS_EN |
IXM42XXX_TMST_CONFIG_TMST_TO_REGS_DIS |

Definition at line 888 of file Ixm42xxxDefs.h.

FIFO_ACCEL_DATA_SIZE
#define FIFO_ACCEL_DATA_SIZE
Definition: Ixm42xxxDefs.h:216
FIFO_TEMP_DATA_SIZE
#define FIFO_TEMP_DATA_SIZE
Definition: Ixm42xxxDefs.h:218
FIFO_TS_FSYNC_SIZE
#define FIFO_TS_FSYNC_SIZE
Definition: Ixm42xxxDefs.h:219
FIFO_GYRO_DATA_SIZE
#define FIFO_GYRO_DATA_SIZE
Definition: Ixm42xxxDefs.h:217
FIFO_ACCEL_GYRO_HIGH_RES_SIZE
#define FIFO_ACCEL_GYRO_HIGH_RES_SIZE
Definition: Ixm42xxxDefs.h:221
FIFO_HEADER_SIZE
#define FIFO_HEADER_SIZE
Definition: Ixm42xxxDefs.h:215