| eMD IIM4265x Driver API 1.0.0

Ixm42xxxDefs.h
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1 /*
2 * ________________________________________________________________________________________________________
3 * Copyright (c) 2017 InvenSense Inc. All rights reserved.
4 *
5 * This software, related documentation and any modifications thereto (collectively “Software”) is subject
6 * to InvenSense and its licensors' intellectual property rights under U.S. and international copyright
7 * and other intellectual property rights laws.
8 *
9 * InvenSense and its licensors retain all intellectual property and proprietary rights in and to the Software
10 * and any use, reproduction, disclosure or distribution of the Software without an express license agreement
11 * from InvenSense is strictly prohibited.
12 *
13 * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE SOFTWARE IS
14 * PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
15 * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
16 * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL
17 * INVENSENSE BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY
18 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
19 * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THE SOFTWARE.
21 * ________________________________________________________________________________________________________
22 */
23
24 #ifndef _INV_IXM42XXX_DEFS_H_
25 #define _INV_IXM42XXX_DEFS_H_
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
35 #include <stdint.h>
36
37 /* List whoami values for all ixm42xxx variants*/
38 #define ICM40608_WHOAMI 0x39
39 #define ICM42600_WHOAMI 0x40
40 #define ICM42602_WHOAMI 0x41
41 #define ICM42605_WHOAMI 0x42
42 #define ICM42622_WHOAMI 0x46
43 #define ICM42686_WHOAMI 0x44
44 #define ICM42688_WHOAMI 0x47
45 #define ICM42608_WHOAMI 0x48
46 #define IIM42652_WHOAMI 0x6F
47
48 /* Define whoami value for the targeted product and make sure the target is valid */
49 #if defined(ICM42600)
50 #define ICM_WHOAMI ICM42600_WHOAMI
51 #elif defined(ICM42602)
52 #define ICM_WHOAMI ICM42602_WHOAMI
53 #elif defined(ICM42605)
54 #define ICM_WHOAMI ICM42605_WHOAMI
55 #elif defined(ICM42622)
56 #define ICM_WHOAMI ICM42622_WHOAMI
57 #elif defined(ICM42686)
58 #define ICM_WHOAMI ICM42686_WHOAMI
59 #elif defined(ICM42688)
60 #define ICM_WHOAMI ICM42688_WHOAMI
61 #elif defined(ICM42608)
62 #define ICM_WHOAMI ICM42608_WHOAMI
63 #elif defined(ICM40608)
64 #define ICM_WHOAMI ICM40608_WHOAMI
65 #elif defined(IIM42652)
66 #define ICM_WHOAMI IIM42652_WHOAMI
67 #else
68 #error "Please define which ICM variant is targeted. Possible values: ICM42600, ICM42602, ICM42605, ICM42686, ICM42688, ICM42622, ICM42608, ICM4068, IIM42652"
69 #endif
70
71
72 /* ----------------------------------------------------------------------------
73 * Device Register map
74 *
75 * Next macros defines address for all ixm42xxx registers as listed by device
76 * datasheet.
77 * Macros name is MPUREG_<REGISTER_NAME> with REGISTER_NAME being the name of
78 * the corresponding register in datasheet.
79 * Note that macro name is MPUREG_<REGISTER_NAME>_Bx with x being the bank
80 * number for registers that are in bank 1 and 2 (suffix is ommitted for
81 * bank0 registers)
82 * ---------------------------------------------------------------------------- */
83
84 /* Bank 0 */
85 #define MPUREG_DEVICE_CONFIG 0x11
86 #define MPUREG_CHIP_CONFIG MPUREG_DEVICE_CONFIG // Retro-compatibility
87 #define MPUREG_DRIVE_CONFIG 0x13
88 #define MPUREG_INT_CONFIG 0x14
89 #define MPUREG_FIFO_CONFIG 0x16
90 #define MPUREG_TEMP_DATA0_UI 0x1D
91 #define MPUREG_ACCEL_DATA_X0_UI 0x1F
92 #define MPUREG_GYRO_DATA_X0_UI 0x25
93 #define MPUREG_TMST_FSYNCH 0x2B
94 #define MPUREG_TMST_FSYNC1 MPUREG_TMST_FSYNCH // Retro-compatibility
95 #define MPUREG_INT_STATUS 0x2D
96 #define MPUREG_FIFO_COUNTH 0x2E
97 #define MPUREG_FIFO_BYTE_COUNT1 MPUREG_FIFO_COUNTH // Retro-compatibility
98 #define MPUREG_FIFO_COUNTL 0x2F
99 #define MPUREG_FIFO_BYTE_COUNT2 MPUREG_FIFO_COUNTL // Retro-compatibility
100 #define MPUREG_FIFO_DATA 0x30
101 #define MPUREG_APEX_DATA0 0x31
102 #define MPUREG_APEX_DATA1 0x32
103 #define MPUREG_APEX_DATA2 0x33
104 #define MPUREG_APEX_DATA3 0x34
105 #define MPUREG_APEX_DATA4 0x35
106 #define MPUREG_APEX_DATA5 0x36
107 #define MPUREG_INT_STATUS2 0x37
108 #define MPUREG_INT_STATUS3 0x38
109 #define MPUREG_SIGNAL_PATH_RESET 0x4B
110 #define MPUREG_INTF_CONFIG0 0x4C
111 #define MPUREG_INTF_CONFIG1 0x4D
112 #define MPUREG_PWR_MGMT_0 0x4E
113 #define MPUREG_GYRO_CONFIG0 0x4F
114 #define MPUREG_ACCEL_CONFIG0 0x50
115 #define MPUREG_GYRO_CONFIG1 0x51
116 #define MPUREG_ACCEL_GYRO_CONFIG0 0x52
117 #define MPUREG_ACCEL_CONFIG1 0x53
118 #define MPUREG_TMST_CONFIG 0x54
119 #define MPUREG_APEX_CONFIG0 0x56
120 #define MPUREG_SMD_CONFIG 0x57
121 #define MPUREG_FIFO_CONFIG1 0x5F
122 #define MPUREG_FIFO_CONFIG2 0x60
123 #define MPUREG_FSYNC_CONFIG 0x62
124 #define MPUREG_INT_CONFIG0 0x63
125 #define MPUREG_INT_CONFIG1 0x64
126 #define MPUREG_INT_SOURCE0 0x65
127 #define MPUREG_INT_SOURCE1 0x66
128 #define MPUREG_INT_SOURCE2 0x67
129 #define MPUREG_INT_SOURCE3 0x68
130 #define MPUREG_INT_SOURCE4 0x69
131 #define MPUREG_INT_SOURCE5 0x6A
132 #define MPUREG_FIFO_LOST_PKT0 0x6C
133 #define MPUREG_SELF_TEST_CONFIG 0x70
134 #define MPUREG_WHO_AM_I 0x75
135 #define MPUREG_REG_BANK_SEL 0x76
136
137 /* Bank 1 */
138 #define MPUREG_GYRO_CONFIG_STATIC2_B1 0x0B
139 #define MPUREG_GYRO_CONFIG_STATIC3_B1 0x0C
140 #define MPUREG_GYRO_CONFIG_STATIC4_B1 0x0D
141 #define MPUREG_GYRO_CONFIG_STATIC5_B1 0x0E
142 #define MPUREG_XG_ST_DATA_B1 0x5F
143 #define MPUREG_YG_ST_DATA_B1 0x60
144 #define MPUREG_ZG_ST_DATA_B1 0x61
145 #define MPUREG_TMST_VAL0_B1 0x62
146 #define MPUREG_INTF_CONFIG4_B1 0x7A
147 #define MPUREG_INTF_CONFIG5_B1 0x7B
148 #define MPUREG_INTF_CONFIG6_B1 0x7C
149
150 /* Bank 2 */
151 #define MPUREG_ACCEL_CONFIG_STATIC2_B2 0x03
152 #define MPUREG_ACCEL_CONFIG_STATIC3_B2 0x04
153 #define MPUREG_ACCEL_CONFIG_STATIC4_B2 0x05
154 #define MPUREG_ACCEL_CONFIG_STATIC0_B2 0x39
155 #define MPUREG_XA_ST_DATA_B2 0x3B
156 #define MPUREG_YA_ST_DATA_B2 0x3C
157 #define MPUREG_ZA_ST_DATA_B2 0x3D
158 /* Only accessible from AUX1 */
159 #define MPUREG_OIS1_CONFIG1_B2 0x44
160 #define MPUREG_OIS1_CONFIG2_B2 0x45
161 #define MPUREG_OIS1_CONFIG3_B2 0x46
162 #define MPUREG_ACCEL_DATA_X0_OIS1_B2 0x49
163 #define MPUREG_GYRO_DATA_X0_OIS1_B2 0x4F
164 #define MPUREG_INT_STATUS_OIS1_B2 0x57
165 /* End of Only accessible from AUX1 */
166 /* Only accessible from AUX2 */
167 #define MPUREG_OIS2_CONFIG1_B2 0x59
168 #define MPUREG_OIS2_CONFIG2_B2 0x5A
169 #define MPUREG_OIS2_CONFIG3_B2 0x5B
170 #define MPUREG_ACCEL_DATA_X0_OIS2_B2 0x5E
171 #define MPUREG_GYRO_DATA_X0_OIS2_B2 0x64
172 #define MPUREG_INT_STATUS_OIS2_B2 0x6C
173 /* End of Only accessible from AUX2 */
174
175
176 /* Bank 4 */
177 #define MPUREG_APEX_CONFIG1_B4 0x40
178 #define MPUREG_APEX_CONFIG2_B4 0x41
179 #define MPUREG_APEX_CONFIG3_B4 0x42
180 #define MPUREG_APEX_CONFIG4_B4 0x43
181 #define MPUREG_APEX_CONFIG5_B4 0x44
182 #define MPUREG_APEX_CONFIG6_B4 0x45
183 #define MPUREG_APEX_CONFIG7_B4 0x46
184 #define MPUREG_APEX_CONFIG8_B4 0x47
185 #define MPUREG_APEX_CONFIG9_B4 0x48
186 #define MPUREG_ACCEL_WOM_X_THR_B4 0x4A
187 #define MPUREG_ACCEL_WOM_Y_THR_B4 0x4B
188 #define MPUREG_ACCEL_WOM_Z_THR_B4 0x4C
189 #define MPUREG_INT_SOURCE6_B4 0x4D
190 #define MPUREG_INT_SOURCE7_B4 0x4E
191 #define MPUREG_INT_SOURCE8_B4 0x4F
192 #define MPUREG_INT_SOURCE9_B4 0x50
193 #define MPUREG_INT_SOURCE10_B4 0x51
194 #define MPUREG_OFFSET_USER_0_B4 0x77
195 #define MPUREG_OFFSET_USER_1_B4 0x78
196 #define MPUREG_OFFSET_USER_2_B4 0x79
197 #define MPUREG_OFFSET_USER_3_B4 0x7A
198 #define MPUREG_OFFSET_USER_4_B4 0x7B
199 #define MPUREG_OFFSET_USER_5_B4 0x7C
200 #define MPUREG_OFFSET_USER_6_B4 0x7D
201 #define MPUREG_OFFSET_USER_7_B4 0x7E
202 #define MPUREG_OFFSET_USER_8_B4 0x7F
203
204 /* ----------------------------------------------------------------------------
205 * Device features
206 *
207 * Next macros define some of the device features such as FIFO, sensor data
208 * size or whoami value.
209 * ---------------------------------------------------------------------------- */
210
211 #define ACCEL_DATA_SIZE 6
212 #define GYRO_DATA_SIZE 6
213 #define TEMP_DATA_SIZE 2
214
215 #define FIFO_HEADER_SIZE 1
216 #define FIFO_ACCEL_DATA_SIZE ACCEL_DATA_SIZE
217 #define FIFO_GYRO_DATA_SIZE GYRO_DATA_SIZE
218 #define FIFO_TEMP_DATA_SIZE 1
219 #define FIFO_TS_FSYNC_SIZE 2
220 #define FIFO_TEMP_HIGH_RES_SIZE 1
221 #define FIFO_ACCEL_GYRO_HIGH_RES_SIZE 3
222
223 #define FIFO_16BYTES_PACKET_SIZE (FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + FIFO_TS_FSYNC_SIZE)
224 #define FIFO_20BYTES_PACKET_SIZE (FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + FIFO_TS_FSYNC_SIZE +\
225 FIFO_TEMP_HIGH_RES_SIZE + FIFO_ACCEL_GYRO_HIGH_RES_SIZE)
226
227 #define FIFO_HEADER_ODR_ACCEL 0x01
228 #define FIFO_HEADER_ODR_GYRO 0x02
229 #define FIFO_HEADER_FSYNC 0x04
230 #define FIFO_HEADER_TMST 0x08
231 #define FIFO_HEADER_HEADER_20 0x10
232 #define FIFO_HEADER_GYRO 0x20
233 #define FIFO_HEADER_ACC 0x40
234 #define FIFO_HEADER_MSG 0x80
235
236
237 #define INVALID_VALUE_FIFO ((int16_t)0x8000)
238 #define INVALID_VALUE_FIFO_1B ((int8_t)0x80)
239
241 typedef union
242 {
243 unsigned char Byte;
244 struct
245 {
246 unsigned char gyro_odr_different : 1;
247 unsigned char accel_odr_different : 1;
248 unsigned char fsync_bit : 1;
249 unsigned char timestamp_bit : 1;
250 unsigned char twentybits_bit : 1;
251 unsigned char gyro_bit : 1;
252 unsigned char accel_bit : 1;
253 unsigned char msg_bit : 1;
254 }bits;
255 } fifo_header_t;
256
257 #define I3C_IBI_PAYLOAD_ALL 0xFF
258 #define I3C_IBI_PAYLOAD_TIMEC 0x80
259 #define I3C_IBI_PAYLOAD_CAT_MISC 0x40
260 #define I3C_IBI_PAYLOAD_CAT_ERROR 0x20
261 #define I3C_IBI_PAYLOAD_CAT_APEX2 0x10
262 #define I3C_IBI_PAYLOAD_CAT_APEX1 0x08
263 #define I3C_IBI_PAYLOAD_CAT_OIS1_DRDY 0x04
264 #define I3C_IBI_PAYLOAD_CAT_FIFO 0x02
265 #define I3C_IBI_PAYLOAD_CAT_UI_DRDY 0x01
266
267
268 /* ----------------------------------------------------------------------------
269 * Device registers description
270 *
271 * Next section defines some of the registers bitfield and declare corresponding
272 * accessors.
273 * Note that descriptors and accessors are not provided for all the registers
274 * but only for the most useful ones.
275 * For all details on registers and bitfields functionalities please refer to
276 * the device datasheet.
277 * ---------------------------------------------------------------------------- */
278
279
280 /* ---------------------------------------------------------------------------
281 * register bank 0
282 * ---------------------------------------------------------------------------- */
283
284 /*
285 * MPUREG_DEVICE_CONFIG
286 * Register Name : DEVICE_CONFIG
287 */
288
289 /* SPI_MODE */
290 #define BIT_DEVICE_CONFIG_SPI_MODE_POS 4
291 #define BIT_DEVICE_CONFIG_SPI_MODE_MASK (0x1 << BIT_DEVICE_CONFIG_SPI_MODE_POS)
292 #define BIT_CHIP_CONFIG_SPI_MODE_MASK BIT_DEVICE_CONFIG_SPI_MODE_MASK //retro-compatibility
293 #define BIT_CHIP_CONFIG_SPI_MODE_POS BIT_DEVICE_CONFIG_SPI_MODE_POS //retro-compatibility
294
295 typedef enum
296 {
297 IXM42XXX_DEVICE_CONFIG_SPI_MODE_1_2 = (0x1 << BIT_DEVICE_CONFIG_SPI_MODE_POS),
298 IXM42XXX_DEVICE_CONFIG_SPI_MODE_0_3 = (0x0 << BIT_DEVICE_CONFIG_SPI_MODE_POS),
299 } IXM42XXX_DEVICE_CONFIG_SPI_MODE_t;
300
301 typedef enum
302 {
303 IXM42XXX_CHIP_CONFIG_SPI_MODE_1_2 = (0x1 << BIT_CHIP_CONFIG_SPI_MODE_POS),
304 IXM42XXX_CHIP_CONFIG_SPI_MODE_0_3 = (0x0 << BIT_CHIP_CONFIG_SPI_MODE_POS),
305 } IXM42XXX_CHIP_CONFIG_SPI_MODE_t; //retro-compatibility
306
307
308 /* SOFT_RESET */
309 #define BIT_DEVICE_CONFIG_RESET_POS 0
310 #define BIT_DEVICE_CONFIG_RESET_MASK 0x01
311 #define BIT_CHIP_CONFIG_RESET_MASK BIT_DEVICE_CONFIG_RESET_MASK //retro-compatibility
312 #define BIT_CHIP_CONFIG_RESET_POS BIT_DEVICE_CONFIG_RESET_POS //retro-compatibility
313
314 typedef enum
315 {
316 IXM42XXX_DEVICE_CONFIG_RESET_EN = 0x01,
317 IXM42XXX_DEVICE_CONFIG_RESET_NONE = 0x00,
318 } IXM42XXX_DEVICE_CONFIG_RESET_t;
319
320 typedef enum
321 {
322 IXM42XXX_CHIP_CONFIG_RESET_EN = 0x01,
323 IXM42XXX_CHIP_CONFIG_RESET_NONE = 0x00,
324 } IXM42XXX_CHIP_CONFIG_RESET_t; //retro-compatibility
325
326 /*
327 * MPUREG_INT_CONFIG
328 * Register Name: INT_CONFIG
329 */
330
331 /* INT2_DRIVE_CIRCUIT */
332 #define BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS 4
333 #define BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS)
334
335 typedef enum
336 {
337 IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_PP = (0x01 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS),
338 IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_OD = (0x00 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS),
339 } IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_t;
340
341 /* INT2_POLARITY */
342 #define BIT_INT_CONFIG_INT2_POLARITY_POS 3
343 #define BIT_INT_CONFIG_INT2_POLARITY_MASK (0x01 << BIT_INT_CONFIG_INT2_POLARITY_POS)
344
345 typedef enum
346 {
347 IXM42XXX_INT_CONFIG_INT2_POLARITY_HIGH = (0x01 << BIT_INT_CONFIG_INT2_POLARITY_POS),
348 IXM42XXX_INT_CONFIG_INT2_POLARITY_LOW = (0x00 << BIT_INT_CONFIG_INT2_POLARITY_POS),
349 } IXM42XXX_INT_CONFIG_INT2_POLARITY_t;
350
351 /* INT1_DRIVE_CIRCUIT */
352 #define BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS 1
353 #define BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS)
354
355 typedef enum
356 {
357 IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_PP = (0x01 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS),
358 IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_OD = (0x00 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS),
359 } IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t;
360
361 /* INT1_POLARITY */
362 #define BIT_INT_CONFIG_INT1_POLARITY_POS 0
363 #define BIT_INT_CONFIG_INT1_POLARITY_MASK 0x01
364
365 typedef enum
366 {
367 IXM42XXX_INT_CONFIG_INT1_POLARITY_HIGH = 0x01,
368 IXM42XXX_INT_CONFIG_INT1_POLARITY_LOW = 0x00,
369 } IXM42XXX_INT_CONFIG_INT1_POLARITY_t;
370
371 /*
372 * MPUREG_FIFO_CONFIG
373 * Register Name: FIFO_CONFIG
374 */
375
376 /* FIFO_MODE */
377 #define BIT_FIFO_CONFIG_MODE_POS 6
378 #define BIT_FIFO_CONFIG_MODE_MASK (0x03 << BIT_FIFO_CONFIG_MODE_POS)
379
380 typedef enum
381 {
382 IXM42XXX_FIFO_CONFIG_MODE_STOP_ON_FULL = (0x02 << BIT_FIFO_CONFIG_MODE_POS),
383 IXM42XXX_FIFO_CONFIG_MODE_STREAM = (0x01 << BIT_FIFO_CONFIG_MODE_POS),
384 IXM42XXX_FIFO_CONFIG_MODE_BYPASS = (0x00 << BIT_FIFO_CONFIG_MODE_POS),
385 } IXM42XXX_FIFO_CONFIG_MODE_t;
386
387 #define IXM42XXX_FIFO_CONFIG_MODE_SNAPSHOT = IXM42XXX_FIFO_CONFIG_MODE_STOP_ON_FULL; // For retro-compatibility
388 /*
389 * MPUREG_INT_STATUS
390 * Register Name: INT_STATUS
391 */
392 #define BIT_INT_STATUS_UI_FSYNC 0x40
393 #define BIT_INT_STATUS_PLL_RDY 0x20
394 #define BIT_INT_STATUS_RESET_DONE 0x10
395 #define BIT_INT_STATUS_DRDY 0x08
396 #define BIT_INT_STATUS_FIFO_THS 0x04
397 #define BIT_INT_STATUS_FIFO_FULL 0x02
398 #define BIT_INT_STATUS_AGC_RDY 0x01
399
400 /*
401 * MPUREG_APEX_DATA0
402 * MPUREG_APEX_DATA1
403 * MPUREG_APEX_DATA2
404 * MPUREG_APEX_DATA3
405 * Register Name: APEX_DATA0
406 * Register Name: APEX_DATA1
407 * Register Name: APEX_DATA2
408 * Register Name: APEX_DATA3
409 */
410
411 /* ACTIVITY_CLASS */
412 #define BIT_APEX_DATA3_ACTIVITY_CLASS_POS 0
413 #define BIT_APEX_DATA3_ACTIVITY_CLASS_MASK 0x03
414
415 typedef enum
416 {
417 IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_OTHER = 0x0,
418 IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_WALK = 0x1,
419 IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_RUN = 0x2,
420 } IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_t;
421
422 /* DMP_IDLE */
423 #define BIT_APEX_DATA3_DMP_IDLE_POS 2
424 #define BIT_APEX_DATA3_DMP_IDLE_MASK (0x01 << BIT_APEX_DATA3_DMP_IDLE_POS)
425
426 typedef enum
427 {
428 IXM42XXX_APEX_DATA3_DMP_IDLE_ON = (0x01 << BIT_APEX_DATA3_DMP_IDLE_POS),
429 IXM42XXX_APEX_DATA3_DMP_IDLE_OFF = (0x00 << BIT_APEX_DATA3_DMP_IDLE_POS),
430 } IXM42XXX_APEX_DATA3_DMP_IDLE_OFF_t;
431
432 /*
433 * MPUREG_APEX_DATA4
434 * Register Name: APEX_DATA4
435 */
436
443 /* TAP_NUM */
444 #define BIT_APEX_DATA4_TAP_NUM_POS 3
445 #define BIT_APEX_DATA4_TAP_NUM_MASK (0x03 << BIT_APEX_DATA4_TAP_NUM_POS)
446 typedef enum
447 {
448 IXM42XXX_APEX_DATA4_TAP_NUM_DOUBLE = (0x02 << BIT_APEX_DATA4_TAP_NUM_POS),
449 IXM42XXX_APEX_DATA4_TAP_NUM_SINGLE = (0x01 << BIT_APEX_DATA4_TAP_NUM_POS),
450 } IXM42XXX_APEX_DATA4_TAP_NUM_t;
451
452 /* TAP_AXIS */
453 #define BIT_APEX_DATA4_TAP_AXIS_POS 1
454 #define BIT_APEX_DATA4_TAP_AXIS_MASK (0x03 << BIT_APEX_DATA4_TAP_AXIS_POS)
455 typedef enum
456 {
457 IXM42XXX_APEX_DATA4_TAP_AXIS_Z = (0x02 << BIT_APEX_DATA4_TAP_AXIS_POS),
458 IXM42XXX_APEX_DATA4_TAP_AXIS_Y = (0x01 << BIT_APEX_DATA4_TAP_AXIS_POS),
459 IXM42XXX_APEX_DATA4_TAP_AXIS_X = (0x00 << BIT_APEX_DATA4_TAP_AXIS_POS),
460 } IXM42XXX_APEX_DATA4_TAP_AXIS_t;
461
462 /* TAP_DIR */
463 #define BIT_APEX_DATA4_TAP_DIR_POS 0
464 #define BIT_APEX_DATA4_TAP_DIR_MASK 0x01
465 typedef enum
466 {
467 IXM42XXX_APEX_DATA4_TAP_DIR_POSITIVE = (0x01 << BIT_APEX_DATA4_TAP_DIR_POS),
468 IXM42XXX_APEX_DATA4_TAP_DIR_NEGATIVE = (0x00 << BIT_APEX_DATA4_TAP_DIR_POS),
469 } IXM42XXX_APEX_DATA4_TAP_DIR_t;
470
471 /*
472 * MPUREG_APEX_DATA5
473 * Register Name: APEX_DATA5
474 */
475
476 /* DOUBLE_TAP_TIMING */
477 #define BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS 0
478 #define BIT_APEX_DATA5_DOUBLE_TAP_TIMING_MASK (0x3F << BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS)
479
480 /*
481 * MPUREG_INT_STATUS2
482 * Register Name: INT_STATUS2
483 */
484 #define BIT_INT_STATUS2_SMD_INT 0x08
485 #define BIT_INT_STATUS2_WOM_Z_INT 0x04
486 #define BIT_INT_STATUS2_WOM_Y_INT 0x02
487 #define BIT_INT_STATUS2_WOM_X_INT 0x01
488
489 /*
490 * MPUREG_INT_STATUS3
491 * Register Name: INT_STATUS3
492 */
493 #define BIT_INT_STATUS3_STEP_DET 0x20
494 #define BIT_INT_STATUS3_STEP_CNT_OVFL 0x10
495 #define BIT_INT_STATUS3_TILT_DET 0x08
496 #define BIT_INT_STATUS3_WAKE_DET 0x04
497 #define BIT_INT_STATUS3_SLEEP_DET 0x02
498 #define BIT_INT_STATUS3_TAP_DET 0x01
499
500 /*
501 * MPUREG_SIGNAL_PATH_RESET
502 * Register Name: SIGNAL_PATH_RESET
503 */
504
505 /* DMP_INIT_EN */
506 #define BIT_SIGNAL_PATH_RESET_DMP_INIT_POS 6
507 #define BIT_SIGNAL_PATH_RESET_DMP_INIT_MASK (0x01 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS)
508
509 typedef enum
510 {
511 IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_EN = (0x01 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS),
512 IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS),
513 } IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_t;
514
515 /* DMP_MEM_RESET_EN */
516 #define BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS 5
517 #define BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_MASK (0x01 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS)
518
519 typedef enum
520 {
521 IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN = (0x01 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS),
522 IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS),
523 } IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_t;
524
525 /* TMST_STROBE */
526 #define BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS 2
527 #define BIT_SIGNAL_PATH_RESET_TMST_STROBE_MASK (0x01 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS)
528
529 typedef enum
530 {
531 IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_EN = (0x01 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS),
532 IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS),
533 } IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_t;
534
535 /* FIFO_FLUSH */
536 #define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS 1
537 #define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_MASK (0x01 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS)
538
539 typedef enum
540 {
541 IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_EN = (0x01 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS),
542 IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS),
543 } IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_t;
544
545 /*
546 * MPUREG_INTF_CONFIG0
547 * Register Name: INTF_CONFIG0
548 */
549
550 /* FIFO_SREG_INVALID_IND */
551 #define BIT_FIFO_SREG_INVALID_IND_POS 7
552 #define BIT_FIFO_SREG_INVALID_IND_MASK (0x01 << BIT_FIFO_SREG_INVALID_IND_POS)
553
554 typedef enum
555 {
556 IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_DIS = (0x01 << BIT_FIFO_SREG_INVALID_IND_POS),
557 IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_EN = (0x00 << BIT_FIFO_SREG_INVALID_IND_POS),
558 } IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t;
559
560 /* FIFO_COUNT_REC */
561 #define BIT_FIFO_COUNT_REC_POS 6
562 #define BIT_FIFO_COUNT_REC_MASK (0x01 << BIT_FIFO_COUNT_REC_POS)
563
564 typedef enum
565 {
566 IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_RECORD = (0x01 << BIT_FIFO_COUNT_REC_POS),
567 IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_BYTE = (0x00 << BIT_FIFO_COUNT_REC_POS),
568 } IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_t;
569
570 /* FIFO_COUNT_ENDIAN */
571 #define BIT_FIFO_COUNT_ENDIAN_POS 5
572 #define BIT_FIFO_COUNT_ENDIAN_MASK (0x01 << BIT_FIFO_COUNT_ENDIAN_POS)
573
574 typedef enum
575 {
576 IXM42XXX_INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN = (0x01 << BIT_FIFO_COUNT_ENDIAN_POS),
577 IXM42XXX_INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN = (0x00 << BIT_FIFO_COUNT_ENDIAN_POS),
578 } IXM42XXX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t;
579
580 /* DATA_ENDIAN */
581 #define BIT_DATA_ENDIAN_POS 4
582 #define BIT_DATA_ENDIAN_MASK (0x01 << BIT_DATA_ENDIAN_POS)
583
584 typedef enum
585 {
586 IXM42XXX_INTF_CONFIG0_DATA_BIG_ENDIAN = (0x01 << BIT_DATA_ENDIAN_POS),
587 IXM42XXX_INTF_CONFIG0_DATA_LITTLE_ENDIAN = (0x00 << BIT_DATA_ENDIAN_POS),
588 } IXM42XXX_INTF_CONFIG0_DATA_ENDIAN_t;
589
590 /* SPI_MODE_OIS2 */
591 #define BIT_SPI_MODE_OIS2_POS 3
592 #define BIT_SPI_MODE_OIS2_MASK (0x01 << BIT_SPI_MODE_OIS2_POS)
593
594 typedef enum
595 {
596 IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_1_2 = (0x01 << BIT_SPI_MODE_OIS2_POS),
597 IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_0_3 = (0x00 << BIT_SPI_MODE_OIS2_POS),
598 } IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_t;
599
600 /* SPI_MODE_AUX1 */
601 #define BIT_SPI_MODE_OIS1_POS 2
602 #define BIT_SPI_MODE_OIS1_MASK (0x01 << BIT_SPI_MODE_OIS1_POS)
603
604 typedef enum
605 {
606 IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_1_2 = (0x01 << BIT_SPI_MODE_OIS1_POS),
607 IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_0_3 = (0x00 << BIT_SPI_MODE_OIS1_POS),
608 } IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_t;
609
610 /*
611 * MPUREG_INTF_CONFIG1
612 * Register Name: INTF_CONFIG1
613 */
614
615 /* ACCEL_LP_CLK_SEL */
616 #define BIT_ACCEL_LP_CLK_SEL_POS 3
617 #define BIT_ACCEL_LP_CLK_SEL_MASK (0x01 << BIT_ACCEL_LP_CLK_SEL_POS)
618
619 typedef enum
620 {
621 IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_WUOSC = (0x00 << BIT_ACCEL_LP_CLK_SEL_POS),
622 IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_RCOSC = (0x01 << BIT_ACCEL_LP_CLK_SEL_POS),
623 } IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_t;
624
625 /* RTC_MODE */
626 #define BIT_RTC_MODE_POS 2
627 #define BIT_RTC_MODE_MASK (0x01 << BIT_RTC_MODE_POS)
628
629 typedef enum
630 {
631 IXM42XXX_INTF_CONFIG1_RTC_MODE_DIS = (0x00 << BIT_RTC_MODE_POS),
632 IXM42XXX_INTF_CONFIG1_RTC_MODE_EN = (0x01 << BIT_RTC_MODE_POS),
633 } IXM42XXX_INTF_CONFIG1_RTC_MODE_t;
634
635 /*
636 * MPUREG_PWR_MGMT_0
637 * Register Name: PWR_MGMT_0
638 */
639
640 /* TEMP_DIS */
641 #define BIT_PWR_MGMT_0_TEMP_POS 5
642 #define BIT_PWR_MGMT_0_TEMP_MASK (0x01 << BIT_PWR_MGMT_0_TEMP_POS)
643
644 typedef enum
645 {
646 IXM42XXX_PWR_MGMT_0_TEMP_DIS = (0x01 << BIT_PWR_MGMT_0_TEMP_POS),
647 IXM42XXX_PWR_MGMT_0_TEMP_EN = (0x00 << BIT_PWR_MGMT_0_TEMP_POS),
648 } IXM42XXX_PWR_MGMT_0_TEMP_t;
649
650 /* IDLE */
651 #define BIT_PWR_MGMT_0_IDLE_POS 4
652 #define BIT_PWR_MGMT_0_IDLE_MASK (0x01 << BIT_PWR_MGMT_0_IDLE_POS)
653
654 typedef enum
655 {
656 IXM42XXX_PWR_MGMT_0_IDLE_DIS = (0x01 << BIT_PWR_MGMT_0_IDLE_POS),
657 IXM42XXX_PWR_MGMT_0_IDLE_EN = (0x00 << BIT_PWR_MGMT_0_IDLE_POS),
658 } IXM42XXX_PWR_MGMT_0_IDLE_t;
659
660 /* GYRO_MODE */
661 #define BIT_PWR_MGMT_0_GYRO_MODE_POS 2
662 #define BIT_PWR_MGMT_0_GYRO_MODE_MASK (0x03 << BIT_PWR_MGMT_0_GYRO_MODE_POS)
663
664 typedef enum
665 {
666 IXM42XXX_PWR_MGMT_0_GYRO_MODE_LN = (0x03 << BIT_PWR_MGMT_0_GYRO_MODE_POS),
667 IXM42XXX_PWR_MGMT_0_GYRO_MODE_STANDBY = (0x01 << BIT_PWR_MGMT_0_GYRO_MODE_POS),
668 IXM42XXX_PWR_MGMT_0_GYRO_MODE_OFF = (0x00 << BIT_PWR_MGMT_0_GYRO_MODE_POS),
669 } IXM42XXX_PWR_MGMT_0_GYRO_MODE_t;
670
671 /* ACCEL_MODE */
672 #define BIT_PWR_MGMT_0_ACCEL_MODE_POS 0
673 #define BIT_PWR_MGMT_0_ACCEL_MODE_MASK 0x03
674
675 typedef enum
676 {
677 IXM42XXX_PWR_MGMT_0_ACCEL_MODE_LN = 0x03,
678 IXM42XXX_PWR_MGMT_0_ACCEL_MODE_LP = 0x02,
679 IXM42XXX_PWR_MGMT_0_ACCEL_MODE_OFF = 0x00,
680 } IXM42XXX_PWR_MGMT_0_ACCEL_MODE_t;
681
682 /*
683 * MPUREG_GYRO_CONFIG0
684 * Register Name: GYRO_CONFIG0
685 */
686
687 /* GYRO_FS_SEL*/
688 #define BIT_GYRO_CONFIG0_FS_SEL_POS 5
689 #define BIT_GYRO_CONFIG0_FS_SEL_MASK (7 << BIT_GYRO_CONFIG0_FS_SEL_POS)
690
693 typedef enum
694 {
695 #if defined(ICM42686)
696 IXM42XXX_GYRO_CONFIG0_FS_SEL_31dps = (7 << BIT_GYRO_CONFIG0_FS_SEL_POS),
697 IXM42XXX_GYRO_CONFIG0_FS_SEL_62dps = (6 << BIT_GYRO_CONFIG0_FS_SEL_POS),
698 IXM42XXX_GYRO_CONFIG0_FS_SEL_125dps = (5 << BIT_GYRO_CONFIG0_FS_SEL_POS),
699 IXM42XXX_GYRO_CONFIG0_FS_SEL_250dps = (4 << BIT_GYRO_CONFIG0_FS_SEL_POS),
700 IXM42XXX_GYRO_CONFIG0_FS_SEL_500dps = (3 << BIT_GYRO_CONFIG0_FS_SEL_POS),
701 IXM42XXX_GYRO_CONFIG0_FS_SEL_1000dps = (2 << BIT_GYRO_CONFIG0_FS_SEL_POS),
702 IXM42XXX_GYRO_CONFIG0_FS_SEL_2000dps = (1 << BIT_GYRO_CONFIG0_FS_SEL_POS),
703 IXM42XXX_GYRO_CONFIG0_FS_SEL_4000dps = (0 << BIT_GYRO_CONFIG0_FS_SEL_POS),
704 #else
705 IXM42XXX_GYRO_CONFIG0_FS_SEL_16dps = (7 << BIT_GYRO_CONFIG0_FS_SEL_POS),
706 IXM42XXX_GYRO_CONFIG0_FS_SEL_31dps = (6 << BIT_GYRO_CONFIG0_FS_SEL_POS),
707 IXM42XXX_GYRO_CONFIG0_FS_SEL_62dps = (5 << BIT_GYRO_CONFIG0_FS_SEL_POS),
708 IXM42XXX_GYRO_CONFIG0_FS_SEL_125dps = (4 << BIT_GYRO_CONFIG0_FS_SEL_POS),
709 IXM42XXX_GYRO_CONFIG0_FS_SEL_250dps = (3 << BIT_GYRO_CONFIG0_FS_SEL_POS),
710 IXM42XXX_GYRO_CONFIG0_FS_SEL_500dps = (2 << BIT_GYRO_CONFIG0_FS_SEL_POS),
711 IXM42XXX_GYRO_CONFIG0_FS_SEL_1000dps = (1 << BIT_GYRO_CONFIG0_FS_SEL_POS),
712 IXM42XXX_GYRO_CONFIG0_FS_SEL_2000dps = (0 << BIT_GYRO_CONFIG0_FS_SEL_POS),
713 #endif
714 } IXM42XXX_GYRO_CONFIG0_FS_SEL_t;
715
716 /* GYRO_ODR */
717 #define BIT_GYRO_CONFIG0_ODR_POS 0
718 #define BIT_GYRO_CONFIG0_ODR_MASK 0x0F
719
722 typedef enum
723 {
724 IXM42XXX_GYRO_CONFIG0_ODR_500_HZ = 0x0F,
725 IXM42XXX_GYRO_CONFIG0_ODR_12_5_HZ = 0x0B,
726 IXM42XXX_GYRO_CONFIG0_ODR_25_HZ = 0x0A,
727 IXM42XXX_GYRO_CONFIG0_ODR_50_HZ = 0x09,
728 IXM42XXX_GYRO_CONFIG0_ODR_100_HZ = 0x08,
729 IXM42XXX_GYRO_CONFIG0_ODR_200_HZ = 0x07,
730 IXM42XXX_GYRO_CONFIG0_ODR_1_KHZ = 0x06,
731 IXM42XXX_GYRO_CONFIG0_ODR_2_KHZ = 0x05,
732 IXM42XXX_GYRO_CONFIG0_ODR_4_KHZ = 0x04,
733 IXM42XXX_GYRO_CONFIG0_ODR_8_KHZ = 0x03,
734 IXM42XXX_GYRO_CONFIG0_ODR_16_KHZ = 0x02,
735 IXM42XXX_GYRO_CONFIG0_ODR_32_KHZ = 0x01,
736 } IXM42XXX_GYRO_CONFIG0_ODR_t;
737
738 /*
739 * MPUREG_ACCEL_CONFIG0
740 * Register Name: ACCEL_CONFIG0
741 */
742
743 /* ACCEL_FS_SEL */
744 #define BIT_ACCEL_CONFIG0_FS_SEL_POS 5
745 #define BIT_ACCEL_CONFIG0_FS_SEL_MASK (0x7 << BIT_ACCEL_CONFIG0_FS_SEL_POS)
746
749 typedef enum
750 {
751 #if defined(ICM42686)
752 IXM42XXX_ACCEL_CONFIG0_FS_SEL_2g = (0x4 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
753 IXM42XXX_ACCEL_CONFIG0_FS_SEL_4g = (0x3 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
754 IXM42XXX_ACCEL_CONFIG0_FS_SEL_8g = (0x2 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
755 IXM42XXX_ACCEL_CONFIG0_FS_SEL_16g = (0x1 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
756 IXM42XXX_ACCEL_CONFIG0_FS_SEL_32g = (0x0 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
757 #else
758 IXM42XXX_ACCEL_CONFIG0_FS_SEL_RESERVED = (0x4 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
759 IXM42XXX_ACCEL_CONFIG0_FS_SEL_2g = (0x3 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
760 IXM42XXX_ACCEL_CONFIG0_FS_SEL_4g = (0x2 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
761 IXM42XXX_ACCEL_CONFIG0_FS_SEL_8g = (0x1 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
762 IXM42XXX_ACCEL_CONFIG0_FS_SEL_16g = (0x0 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
763 #endif
764 } IXM42XXX_ACCEL_CONFIG0_FS_SEL_t;
765
766 /* ACCEL_ODR */
767 #define BIT_ACCEL_CONFIG0_ODR_POS 0
768 #define BIT_ACCEL_CONFIG0_ODR_MASK 0x0F
769
772 typedef enum
773 {
774 IXM42XXX_ACCEL_CONFIG0_ODR_500_HZ = 0xF,
775 IXM42XXX_ACCEL_CONFIG0_ODR_1_5625_HZ = 0xE,
776 IXM42XXX_ACCEL_CONFIG0_ODR_3_125_HZ = 0xD,
777 IXM42XXX_ACCEL_CONFIG0_ODR_6_25_HZ = 0xC,
778 IXM42XXX_ACCEL_CONFIG0_ODR_12_5_HZ = 0xB,
779 IXM42XXX_ACCEL_CONFIG0_ODR_25_HZ = 0xA,
780 IXM42XXX_ACCEL_CONFIG0_ODR_50_HZ = 0x9,
781 IXM42XXX_ACCEL_CONFIG0_ODR_100_HZ = 0x8,
782 IXM42XXX_ACCEL_CONFIG0_ODR_200_HZ = 0x7,
783 IXM42XXX_ACCEL_CONFIG0_ODR_1_KHZ = 0x6,
784 IXM42XXX_ACCEL_CONFIG0_ODR_2_KHZ = 0x5,
785 IXM42XXX_ACCEL_CONFIG0_ODR_4_KHZ = 0x4,
786 IXM42XXX_ACCEL_CONFIG0_ODR_8_KHZ = 0x3,
787 IXM42XXX_ACCEL_CONFIG0_ODR_16_KHZ = 0x2,
788 IXM42XXX_ACCEL_CONFIG0_ODR_32_KHZ = 0x1,
789 } IXM42XXX_ACCEL_CONFIG0_ODR_t;
790
791 /*
792 * MPUREG_GYRO_CONFIG1
793 * Register Name: GYRO_CONFIG1
794 */
795
796 /* TEMP_FILT_BW */
797 #define BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS 5
798 #define BIT_GYRO_CONFIG1_TEMP_FILT_BW_MASK (0x7 << BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS)
799
800 /* GYRO_UI_FILT_ORD */
801 #define BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS 2
802 #define BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_MASK (0x3 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS)
803
804 typedef enum
805 {
806 IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_1ST_ORDER = (0x0 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS),
807 IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_2ND_ORDER = (0x1 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS),
808 IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_3RD_ORDER = (0x2 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS),
809 } IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_t;
810
811 /* GYRO_DEC2_M2_ORD */
812 #define BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_POS 0
813 #define BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_MASK 0x3
814
815
816 /*
817 * MPUREG_ACCEL_GYRO_CONFIG0
818 * Register Name: GYRO_ACCEL_CONFIG0
819 */
820
821 /* ACCEL_UI_FILT_BW_IND */
822 #define BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS 4
823 #define BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_MASK (0xF << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS)
824
825 typedef enum
826 {
827 IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_40 = (0x7 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
828 IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_20 = (0x6 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
829 IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_16 = (0x5 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
830 IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_10 = (0x4 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
831 IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_8 = (0x3 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
832 IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_5 = (0x2 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
833 IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_4 = (0x1 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
834 IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_2 = (0x0 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
835 } IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t;
836
837 typedef enum
838 {
839 IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_16 = (0x6 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
840 IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_1 = (0x1 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
841 } IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t;
842
843 /* GYRO_UI_FILT_BW_IND */
844 #define BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_POS 0
845 #define BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_MASK 0x0F
846
847 typedef enum
848 {
849 IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_40 = 0x07,
850 IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_20 = 0x06,
851 IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_16 = 0x05,
852 IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_10 = 0x04,
853 IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_8 = 0x03,
854 IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_5 = 0x02,
855 IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_4 = 0x01,
856 IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_2 = 0x00,
857 } IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t;
858
859 /*
860 * MPUREG_ACCEL_CONFIG1
861 * Register Name: ACCEL_CONFIG1
862 */
863
864 /* ACCEL_UI_FILT_ORD */
865 #define BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS 3
866 #define BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS)
867
868 typedef enum
869 {
870 IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_1ST_ORDER = (0x0 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS),
871 IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_2ND_ORDER = (0x1 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS),
872 IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_3RD_ORDER = (0x2 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS),
873 } IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_t;
874
875 /* ACCEL_DEC2_M2_ORD */
876 #define BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS 1
877 #define BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS)
878
879 /*
880 * MPUREG_TMST_CONFIG
881 * Register Name: TMST_CONFIG
882 */
883
884 /* TMST_TO_REGS */
885 #define BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS 4
886 #define BIT_TMST_CONFIG_TMST_TO_REGS_EN_MASK (0x1 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS)
887
888 typedef enum
889 {
890 IXM42XXX_TMST_CONFIG_TMST_TO_REGS_EN = (0x1 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS),
891 IXM42XXX_TMST_CONFIG_TMST_TO_REGS_DIS = (0x0 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS),
892 } IXM42XXX_TMST_CONFIG_TMST_TO_REGS_EN_t;
893
894 /* TMST_RES */
895 #define BIT_TMST_CONFIG_RESOL_POS 3
896 #define BIT_TMST_CONFIG_RESOL_MASK (0x1 << BIT_TMST_CONFIG_RESOL_POS)
897
898 typedef enum
899 {
900 IXM42XXX_TMST_CONFIG_RESOL_16us = (0x01 << BIT_TMST_CONFIG_RESOL_POS),
901 IXM42XXX_TMST_CONFIG_RESOL_1us = (0x00 << BIT_TMST_CONFIG_RESOL_POS),
902 } IXM42XXX_TMST_CONFIG_RESOL_t;
903
904 /* TMST_FSYNC */
905 #define BIT_TMST_CONFIG_TMST_FSYNC_POS 1
906 #define BIT_TMST_CONFIG_TMST_FSYNC_MASK (0x1 << BIT_TMST_CONFIG_TMST_FSYNC_POS)
907
908 typedef enum
909 {
910 IXM42XXX_TMST_CONFIG_TMST_FSYNC_EN = (0x01 << BIT_TMST_CONFIG_TMST_FSYNC_POS),
911 IXM42XXX_TMST_CONFIG_TMST_FSYNC_DIS = (0x00 << BIT_TMST_CONFIG_TMST_FSYNC_POS),
912 } IXM42XXX_TMST_CONFIG_TMST_FSYNC_EN_t;
913
914 /* TMST_EN */
915 #define BIT_TMST_CONFIG_TMST_EN_POS 0
916 #define BIT_TMST_CONFIG_TMST_EN_MASK 0x1
917
918 typedef enum
919 {
920 IXM42XXX_TMST_CONFIG_TMST_EN = 0x01,
921 IXM42XXX_TMST_CONFIG_TMST_DIS = 0x00,
922 } IXM42XXX_TMST_CONFIG_TMST_EN_t;
923
924 /*
925 * MPUREG_APEX_CONFIG0
926 * Register Name: APEX_CONFIG0
927 */
928
929 /* DMP_POWER_SAVE_EN */
930 #define BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS 7
931 #define BIT_APEX_CONFIG0_DMP_POWER_SAVE_MASK (0x1 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS)
932
933 typedef enum
934 {
935 IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_EN = (0x1 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS),
936 IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_DIS = (0x0 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS),
937 } IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_t;
938
939 /* TAP_ENABLE */
940 #define BIT_APEX_CONFIG0_TAP_ENABLE_POS 6
941 #define BIT_APEX_CONFIG0_TAP_ENABLE_MASK (0x1 << BIT_APEX_CONFIG0_TAP_ENABLE_POS)
942
943 typedef enum
944 {
945 IXM42XXX_APEX_CONFIG0_TAP_ENABLE_EN = (0x1 << BIT_APEX_CONFIG0_TAP_ENABLE_POS),
946 IXM42XXX_APEX_CONFIG0_TAP_ENABLE_DIS = (0x0 << BIT_APEX_CONFIG0_TAP_ENABLE_POS),
947 } IXM42XXX_APEX_CONFIG0_TAP_ENABLE_t;
948
949 /* PEDO_EN */
950 #define BIT_APEX_CONFIG0_PEDO_EN_POS 5
951 #define BIT_APEX_CONFIG0_PEDO_EN_MASK (0x1 << BIT_APEX_CONFIG0_PEDO_EN_POS)
952
953 typedef enum
954 {
955 IXM42XXX_APEX_CONFIG0_PEDO_EN_EN = (0x1 << BIT_APEX_CONFIG0_PEDO_EN_POS),
956 IXM42XXX_APEX_CONFIG0_PEDO_EN_DIS = (0x0 << BIT_APEX_CONFIG0_PEDO_EN_POS),
957 } IXM42XXX_APEX_CONFIG0_PEDO_EN_t;
958
959 /* R2W_EN */
960 #define BIT_APEX_CONFIG0_R2W_EN_POS 3
961 #define BIT_APEX_CONFIG0_R2W_EN_MASK (0x1 << BIT_APEX_CONFIG0_R2W_EN_POS)
962
963 typedef enum
964 {
965 IXM42XXX_APEX_CONFIG0_R2W_EN_EN = (0x1 << BIT_APEX_CONFIG0_R2W_EN_POS),
966 IXM42XXX_APEX_CONFIG0_R2W_EN_DIS = (0x0 << BIT_APEX_CONFIG0_R2W_EN_POS),
967 } IXM42XXX_APEX_CONFIG0_R2W_EN_t;
968
969 /* TILT_EN */
970 #define BIT_APEX_CONFIG0_TILT_EN_POS 4
971 #define BIT_APEX_CONFIG0_TILT_EN_MASK (0x1 << BIT_APEX_CONFIG0_TILT_EN_POS)
972
973 typedef enum
974 {
975 IXM42XXX_APEX_CONFIG0_TILT_EN_EN = (0x1 << BIT_APEX_CONFIG0_TILT_EN_POS),
976 IXM42XXX_APEX_CONFIG0_TILT_EN_DIS = (0x0 << BIT_APEX_CONFIG0_TILT_EN_POS),
977 } IXM42XXX_APEX_CONFIG0_TILT_EN_t;
978
979 /* DMP_ODR */
980 #define BIT_APEX_CONFIG0_DMP_ODR_POS 0
981 #define BIT_APEX_CONFIG0_DMP_ODR_MASK (0x3 << BIT_APEX_CONFIG0_DMP_ODR_POS)
982
985 typedef enum
986 {
987 IXM42XXX_APEX_CONFIG0_DMP_ODR_25Hz = (0x0 << BIT_APEX_CONFIG0_DMP_ODR_POS),
988 IXM42XXX_APEX_CONFIG0_DMP_ODR_50Hz = (0x2 << BIT_APEX_CONFIG0_DMP_ODR_POS),
989 IXM42XXX_APEX_CONFIG0_DMP_ODR_RESERVED = (0x3 << BIT_APEX_CONFIG0_DMP_ODR_POS),
990 } IXM42XXX_APEX_CONFIG0_DMP_ODR_t;
991
992 /*
993 * MPUREG_SMD_CONFIG
994 * Register Name: SMD_CONFIG
995 */
996
997 /* WOM_INT_MODE */
998 #define BIT_SMD_CONFIG_WOM_INT_MODE_POS 3
999 #define BIT_SMD_CONFIG_WOM_INT_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_INT_MODE_POS)
1000
1001 typedef enum
1002 {
1003 IXM42XXX_SMD_CONFIG_WOM_INT_MODE_ANDED = (0x01 << BIT_SMD_CONFIG_WOM_INT_MODE_POS),
1004 IXM42XXX_SMD_CONFIG_WOM_INT_MODE_ORED = (0x00 << BIT_SMD_CONFIG_WOM_INT_MODE_POS),
1005 } IXM42XXX_SMD_CONFIG_WOM_INT_MODE_t;
1006
1007 /* WOM_MODE */
1008 #define BIT_SMD_CONFIG_WOM_MODE_POS 2
1009 #define BIT_SMD_CONFIG_WOM_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_MODE_POS)
1010
1011 typedef enum
1012 {
1013 IXM42XXX_SMD_CONFIG_WOM_MODE_CMP_PREV = (0x01 << BIT_SMD_CONFIG_WOM_MODE_POS),
1014 IXM42XXX_SMD_CONFIG_WOM_MODE_CMP_INIT = (0x00 << BIT_SMD_CONFIG_WOM_MODE_POS),
1015 } IXM42XXX_SMD_CONFIG_WOM_MODE_t;
1016
1017 /* SMD_MODE */
1018 #define BIT_SMD_CONFIG_SMD_MODE_POS 0
1019 #define BIT_SMD_CONFIG_SMD_MODE_MASK 0x3
1020
1021 typedef enum
1022 {
1023 IXM42XXX_SMD_CONFIG_SMD_MODE_LONG = 0x03,
1024 IXM42XXX_SMD_CONFIG_SMD_MODE_SHORT = 0x02,
1025 IXM42XXX_SMD_CONFIG_SMD_MODE_WOM = 0x01,
1026 IXM42XXX_SMD_CONFIG_SMD_MODE_DISABLED = 0x00,
1027 } IXM42XXX_SMD_CONFIG_SMD_MODE_t;
1028
1029 /*
1030 * MPUREG_FIFO_CONFIG1
1031 * Register Name: FIFO_CONFIG1
1032 */
1033 #define BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS 6
1034 #define BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_MASK (0x1 << BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS)
1035
1036 /* FIFO_WM_GT_TH */
1037 #define BIT_FIFO_CONFIG1_WM_GT_TH_POS 5
1038 #define BIT_FIFO_CONFIG1_WM_GT_TH_MASK (0x1 << BIT_FIFO_CONFIG1_WM_GT_TH_POS)
1039
1040 typedef enum
1041 {
1042 IXM42XXX_FIFO_CONFIG1_WM_GT_TH_EN = (0x1 << BIT_FIFO_CONFIG1_WM_GT_TH_POS),
1043 IXM42XXX_FIFO_CONFIG1_WM_GT_TH_DIS = (0x0 << BIT_FIFO_CONFIG1_WM_GT_TH_POS),
1044 } IXM42XXX_FIFO_CONFIG1_WM_GT_t;
1045
1046 /* FIFO_HIRES_EN */
1047 #define BIT_FIFO_CONFIG1_HIRES_POS 4
1048 #define BIT_FIFO_CONFIG1_HIRES_MASK (0x1 << BIT_FIFO_CONFIG1_HIRES_POS)
1049
1050 typedef enum
1051 {
1052 IXM42XXX_FIFO_CONFIG1_HIRES_EN = (0x1 << BIT_FIFO_CONFIG1_HIRES_POS),
1053 IXM42XXX_FIFO_CONFIG1_HIRES_DIS = (0x0 << BIT_FIFO_CONFIG1_HIRES_POS),
1054 } IXM42XXX_FIFO_CONFIG1_HIRES_t;
1055
1056 /* FIFO_TMST_FSYNC_EN */
1057 #define BIT_FIFO_CONFIG1_TMST_FSYNC_POS 3
1058 #define BIT_FIFO_CONFIG1_TMST_FSYNC_MASK (0x1 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS)
1059
1060 typedef enum
1061 {
1062 IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_EN = (0x1 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS),
1063 IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_DIS = (0x0 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS),
1064 } IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_t;
1065
1066 /* FIFO_TEMP_EN */
1067 #define BIT_FIFO_CONFIG1_TEMP_POS 2
1068 #define BIT_FIFO_CONFIG1_TEMP_MASK (0x1 << BIT_FIFO_CONFIG1_TEMP_POS)
1069
1070 typedef enum
1071 {
1072 IXM42XXX_FIFO_CONFIG1_TEMP_EN = (0x1 << BIT_FIFO_CONFIG1_TEMP_POS),
1073 IXM42XXX_FIFO_CONFIG1_TEMP_DIS = (0x0 << BIT_FIFO_CONFIG1_TEMP_POS),
1074 } IXM42XXX_FIFO_CONFIG1_TEMP_t;
1075
1076 /* FIFO_GYRO_EN */
1077 #define BIT_FIFO_CONFIG1_GYRO_POS 1
1078 #define BIT_FIFO_CONFIG1_GYRO_MASK (0x1 << BIT_FIFO_CONFIG1_GYRO_POS)
1079
1080 typedef enum
1081 {
1082 IXM42XXX_FIFO_CONFIG1_GYRO_EN = (0x1 << BIT_FIFO_CONFIG1_GYRO_POS),
1083 IXM42XXX_FIFO_CONFIG1_GYRO_DIS = (0x0 << BIT_FIFO_CONFIG1_GYRO_POS),
1084 } IXM42XXX_FIFO_CONFIG1_GYRO_t;
1085
1086 /* FIFO_ACCEL_EN*/
1087 #define BIT_FIFO_CONFIG1_ACCEL_POS 0
1088 #define BIT_FIFO_CONFIG1_ACCEL_MASK 0x1
1089
1090 typedef enum
1091 {
1092 IXM42XXX_FIFO_CONFIG1_ACCEL_EN = 0x01,
1093 IXM42XXX_FIFO_CONFIG1_ACCEL_DIS = 0x00,
1094 } IXM42XXX_FIFO_CONFIG1_ACCEL_t;
1095
1096 /*
1097 * MPUREG_FSYNC_CONFIG
1098 * Register Name: FSYNC_CONFIG
1099 */
1100
1101 /* FSYNC_UI_SEL */
1102 #define BIT_FSYNC_CONFIG_UI_SEL_POS 4
1103 #define BIT_FSYNC_CONFIG_UI_SEL_MASK (0x7 << BIT_FSYNC_CONFIG_UI_SEL_POS)
1104
1105 typedef enum
1106 {
1107 IXM42XXX_FSYNC_CONFIG_UI_SEL_NO = (0x0 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1108 IXM42XXX_FSYNC_CONFIG_UI_SEL_TEMP = (0x1 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1109 IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_X = (0x2 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1110 IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_Y = (0x3 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1111 IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_Z = (0x4 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1112 IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_X = (0x5 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1113 IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_Y = (0x6 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1114 IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_Z = (0x7 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1115 } IXM42XXX_FSYNC_CONFIG_UI_SEL_t;
1116
1117 /*
1118 * MPUREG_INT_CONFIG1
1119 * Register Name: INT_CONFIG1
1120 */
1121
1122 /* ASY_RESET_DISABLE */
1123 #define BIT_INT_CONFIG1_ASY_RST_POS 4
1124 #define BIT_INT_CONFIG1_ASY_RST_MASK (0x1 << BIT_INT_CONFIG1_ASY_RST_POS)
1125
1126 typedef enum
1127 {
1128 IXM42XXX_INT_CONFIG1_ASY_RST_DISABLED = (0x1 << BIT_INT_CONFIG1_ASY_RST_POS),
1129 IXM42XXX_INT_CONFIG1_ASY_RST_ENABLED = (0x0 << BIT_INT_CONFIG1_ASY_RST_POS),
1130 } IXM42XXX_INT_CONFIG1_ASY_RST_t;
1131
1132 /*
1133 * MPUREG_INT_SOURCE0
1134 * Register Name: INT_SOURCE0
1135 */
1136 #define BIT_INT_UI_FSYNC_INT_EN_POS 6
1137 #define BIT_INT_PLL_RDY_INT_EN_POS 5
1138 #define BIT_INT_RESET_DONE_INT_EN_POS 4
1139 #define BIT_INT_UI_DRDY_INT_EN_POS 3
1140 #define BIT_INT_FIFO_THS_INT_EN_POS 2
1141 #define BIT_INT_FIFO_FULL_INT_EN_POS 1
1142 #define BIT_INT_UI_AGC_RDY_INT_EN_POS 0
1143
1144 #define BIT_INT_SOURCE0_UI_FSYNC_INT1_EN 0x40
1145 #define BIT_INT_SOURCE0_PLL_RDY_INT1_EN 0x20
1146 #define BIT_INT_SOURCE0_RESET_DONE_INT1_EN 0x10
1147 #define BIT_INT_SOURCE0_UI_DRDY_INT1_EN 0x08
1148 #define BIT_INT_SOURCE0_FIFO_THS_INT1_EN 0x04
1149 #define BIT_INT_SOURCE0_FIFO_FULL_INT1_EN 0x02
1150 #define BIT_INT_SOURCE0_UI_AGC_RDY_INT1_EN 0x01
1151
1152 /*
1153 * MPUREG_INT_SOURCE1
1154 * Register Name: INT_SOURCE1
1155 */
1156 #define BIT_INT_SMD_INT_EN_POS 3
1157 #define BIT_INT_WOM_Z_INT_EN_POS 2
1158 #define BIT_INT_WOM_Y_INT_EN_POS 1
1159 #define BIT_INT_WOM_X_INT_EN_POS 0
1160
1161 #define BIT_INT_SOURCE1_SMD_INT1_EN 0x08
1162 #define BIT_INT_SOURCE1_WOM_Z_INT1_EN 0x04
1163 #define BIT_INT_SOURCE1_WOM_Y_INT1_EN 0x02
1164 #define BIT_INT_SOURCE1_WOM_X_INT1_EN 0x01
1165
1166 /*
1167 * MPUREG_INT_SOURCE2
1168 * Register Name: INT_SOURCE2
1169 */
1170 #define BIT_INT_SOURCE2_OIS2_AGC_RDY_INT1_EN 0x20
1171 #define BIT_INT_SOURCE2_OIS2_FSYNC_INT1_EN 0x10
1172 #define BIT_INT_SOURCE2_OIS2_DRDY_INT1_EN 0x08
1173 #define BIT_INT_SOURCE2_OIS1_AGC_RDY_INT1_EN 0x04
1174 #define BIT_INT_SOURCE2_OIS1_FSYNC_INT1_EN 0x02
1175 #define BIT_INT_SOURCE2_OIS1_DRDY_INT1_EN 0x01
1176
1177 /*
1178 * MPUREG_INT_SOURCE3
1179 * Register Name: INT_SOURCE3
1180 */
1181 #define BIT_INT_SOURCE3_UI_FSYNC_INT2_EN 0x40
1182 #define BIT_INT_SOURCE3_PLL_RDY_INT2_EN 0x20
1183 #define BIT_INT_SOURCE3_RESET_DONE_INT2_EN 0x10
1184 #define BIT_INT_SOURCE3_UI_DRDY_INT2_EN 0x08
1185 #define BIT_INT_SOURCE3_FIFO_THS_INT2_EN 0x04
1186 #define BIT_INT_SOURCE3_FIFO_FULL_INT2_EN 0x02
1187 #define BIT_INT_SOURCE3_UI_AGC_RDY_INT2_EN 0x01
1188
1189 /*
1190 * MPUREG_INT_SOURCE4
1191 * Register Name: INT_SOURCE4
1192 */
1193 #define BIT_INT_SOURCE4_SMD_INT2_EN 0x08
1194 #define BIT_INT_SOURCE4_WOM_Z_INT2_EN 0x04
1195 #define BIT_INT_SOURCE4_WOM_Y_INT2_EN 0x02
1196 #define BIT_INT_SOURCE4_WOM_X_INT2_EN 0x01
1197
1198 /*
1199 * MPUREG_INT_SOURCE5
1200 * Register Name: INT_SOURCE5
1201 */
1202 #define BIT_INT_SOURCE5_OIS2_AGC_RDY_INT2_EN 0x20
1203 #define BIT_INT_SOURCE5_OIS2_FSYNC_INT2_EN 0x10
1204 #define BIT_INT_SOURCE5_OIS2_DRDY_INT2_EN 0x08
1205 #define BIT_INT_SOURCE5_OIS1_AGC_RDY_INT2_EN 0x04
1206 #define BIT_INT_SOURCE5_OIS1_FSYNC_INT2_EN 0x02
1207 #define BIT_INT_SOURCE5_OIS1_DRDY_INT2_EN 0x01
1208
1209 /*
1210 * MPUREG_SELF_TEST_CONFIG
1211 * Register Name: SELF_TEST_CONFIG
1212 */
1213 #define BIT_ST_REGULATOR_EN 0x40
1214 #define BIT_ACCEL_Z_ST_EN 0x20
1215 #define BIT_ACCEL_Y_ST_EN 0x10
1216 #define BIT_ACCEL_X_ST_EN 0x08
1217 #define BIT_GYRO_Z_ST_EN 0x04
1218 #define BIT_GYRO_Y_ST_EN 0x02
1219 #define BIT_GYRO_X_ST_EN 0x01
1220
1221
1222 /*
1223 * MPUREG_SCAN0
1224 * Register Name: SCAN0
1225 */
1226 #define BIT_DMP_MEM_ACCESS_EN 0x08
1227 #define BIT_MEM_OTP_ACCESS_EN 0x04
1228 #define BIT_FIFO_MEM_RD_SYS 0x02
1229 #define BIT_FIFO_MEM_WR_SER 0x01
1230
1231 /* ----------------------------------------------------------------------------
1232 * Register bank 1
1233 * ---------------------------------------------------------------------------- */
1234
1235 #define BIT_SENSOR_CONFIG2_OIS_MODE_POS 4
1236 #define BIT_SENSOR_CONFIG2_OIS_MODE_MASK (0x03 << BIT_SENSOR_CONFIG2_OIS_MODE_POS)
1237
1238 typedef enum
1239 {
1240 IXM42XXX_SENSOR_CONFIG2_OIS_MODE_32KHZ = (0x2 << BIT_SENSOR_CONFIG2_OIS_MODE_POS),
1241 IXM42XXX_SENSOR_CONFIG2_OIS_MODE_8KHZ = (0x1 << BIT_SENSOR_CONFIG2_OIS_MODE_POS),
1242 IXM42XXX_SENSOR_CONFIG2_OIS_MODE_DIS = (0x0 << BIT_SENSOR_CONFIG2_OIS_MODE_POS)
1243 } IXM42XXX_SENSOR_CONFIG2_OIS_MODE_t;
1244
1245
1246 /*
1247 * MPUREG_GYRO_CONFIG_STATIC2_B1
1248 * Register Name: GYRO_CONFIG_STATIC2
1249 */
1250
1251 /* GYRO_AAF_DIS */
1252 #define BIT_GYRO_AAF_DIS_POS 1
1253 #define BIT_GYRO_AAF_DIS_MASK (0x01 << BIT_GYRO_AAF_DIS_POS)
1254
1255 typedef enum
1256 {
1257 IXM42XXX_GYRO_AAF_EN = (0x0 << BIT_GYRO_AAF_DIS_POS),
1258 IXM42XXX_GYRO_AAF_DIS = (0x1 << BIT_GYRO_AAF_DIS_POS),
1259 } IXM42XXX_GYRO_AAF_DIS_t;
1260
1261 /* GYRO_NF_DIS */
1262 #define BIT_GYRO_NF_DIS_POS 0
1263 #define BIT_GYRO_NF_DIS_MASK (0x01 << BIT_GYRO_NF_DIS_POS)
1264 typedef enum
1265 {
1266 IXM42XXX_GYRO_NF_EN = (0x0 << BIT_GYRO_NF_DIS_POS),
1267 IXM42XXX_GYRO_NF_DIS = (0x1 << BIT_GYRO_NF_DIS_POS),
1268 } IXM42XXX_GYRO_NF_DIS_t;
1269
1270 /*
1271 * MPUREG_GYRO_CONFIG_STATIC3_B1
1272 * Register Name: GYRO_CONFIG_STATIC3
1273 */
1274
1275 /* GYRO_AAF_DELT */
1276 #define BIT_GYRO_AAF_DELT_POS 0
1277 #define BIT_GYRO_AAF_DELT_MASK (0x3F << BIT_GYRO_AAF_DELT_POS)
1278
1279 /*
1280 * MPUREG_GYRO_CONFIG_STATIC4_B1
1281 * Register Name: GYRO_CONFIG_STATIC4
1282 */
1283
1284 /* GYRO_AAF_DELTSQR */
1285 #define BIT_GYRO_AAF_DELTSQR_POS_LO 0
1286 #define BIT_GYRO_AAF_DELTSQR_MASK_LO (0xFF << BIT_GYRO_AAF_DELTSQR_POS_LO)
1287
1288 /*
1289 * MPUREG_GYRO_CONFIG_STATIC5_B1
1290 * Register Name: GYRO_CONFIG_STATIC5
1291 */
1292
1293 #define BIT_GYRO_AAF_DELTSQR_POS_HI 0
1294 #define BIT_GYRO_AAF_DELTSQR_MASK_HI (0x0F << BIT_GYRO_AAF_DELTSQR_POS_HI)
1295
1296 /* GYRO_AAF_BITSHIFT */
1297 #define BIT_GYRO_AAF_BITSHIFT_POS 4
1298 #define BIT_GYRO_AAF_BITSHIFT_MASK (0x0F << BIT_GYRO_AAF_BITSHIFT_POS)
1299
1300 /*
1301 * MPUREG_INTF_CONFIG4_B1
1302 * Register Name: INTF_CONFIG4
1303 */
1304
1305 /* SPI_AP_4WIRE */
1306 #define BIT_INTF_CONFIG4_AP_SPI_POS 1
1307 #define BIT_INTF_CONFIG4_AP_SPI_MASK (0x1 << BIT_INTF_CONFIG4_AP_SPI_POS)
1308
1309 typedef enum
1310 {
1311 IXM42XXX_INTF_CONFIG4_AP_SPI4W = (0x1 << BIT_INTF_CONFIG4_AP_SPI_POS),
1312 IXM42XXX_INTF_CONFIG4_AP_SPI3W = (0x0 << BIT_INTF_CONFIG4_AP_SPI_POS),
1313 } IXM42XXX_INTF_CONFIG4_AP_SPI_t;
1314
1315 /*
1316 * MPUREG_INTF_CONFIG5_B1
1317 * Register Name: INTF_CONFIG5
1318 */
1319
1320 /* GPIO_PAD_SEL */
1321 #define BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS 1
1322 #define BIT_INTF_CONFIG5_GPIO_PAD_SEL_MASK (0x3 << BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS)
1323
1324 /*
1325 * MPUREG_INTF_CONFIG6_B1
1326 * Register Name: INTF_CONFIG6
1327 */
1328
1329 /* I3C_DDR_EN */
1330 #define BIT_INTF_CONFIG6_I3C_DDR_EN_POS 1
1331 #define BIT_INTF_CONFIG6_I3C_DDR_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_DDR_EN_POS)
1332
1333 /* I3C_SDR_EN */
1334 #define BIT_INTF_CONFIG6_I3C_SDR_EN_POS 0
1335 #define BIT_INTF_CONFIG6_I3C_SDR_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_SDR_EN_POS)
1336
1337 /*
1338 * MPUREG_INTF_CONFIG6_B1
1339 * Register Name: INTF_CONFIG6
1340 */
1341
1342 /* I3C_IBI_BYTE_EN */
1343 #define BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS 3
1344 #define BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS)
1345
1346 /* I3C_IBI_EN */
1347 #define BIT_INTF_CONFIG6_I3C_IBI_EN_POS 2
1348 #define BIT_INTF_CONFIG6_I3C_IBI_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_IBI_EN_POS)
1349
1350 /* ----------------------------------------------------------------------------
1351 * Register bank 2
1352 * ---------------------------------------------------------------------------- */
1353
1354 /*
1355 * MPUREG_ACCEL_CONFIG_STATIC2_B2
1356 * Register Name: ACCEL_CONFIG_STATIC2
1357 */
1358
1359 /* ACCEL_AAF_DIS */
1360 #define BIT_ACCEL_AAF_DIS_POS 0
1361 #define BIT_ACCEL_AAF_DIS_MASK (0x01 << BIT_ACCEL_AAF_DIS_POS)
1362
1363 typedef enum
1364 {
1365 IXM42XXX_ACCEL_AAF_EN = (0x0 << BIT_ACCEL_AAF_DIS_POS),
1366 IXM42XXX_ACCEL_AAF_DIS = (0x1 << BIT_ACCEL_AAF_DIS_POS),
1367 } IXM42XXX_ACCEL_AAF_DIS_t;
1368
1369 /* ACCEL_AAF_DELT */
1370 #define BIT_ACCEL_AAF_DELT_POS 1
1371 #define BIT_ACCEL_AAF_DELT_MASK (0x3F << BIT_ACCEL_AAF_DELT_POS)
1372
1373 /*
1374 * MPUREG_ACCEL_CONFIG_STATIC3_B2
1375 * Register Name: ACCEL_CONFIG_STATIC3
1376 */
1377
1378 /* ACCEL_AAF_DELTSQR */
1379 #define BIT_ACCEL_AAF_DELTSQR_POS_LO 0
1380 #define BIT_ACCEL_AAF_DELTSQR_MASK_LO (0xFF << BIT_ACCEL_AAF_DELTSQR_POS_LO)
1381
1382 /*
1383 * MPUREG_ACCEL_CONFIG_STATIC4_B2
1384 * Register Name: ACCEL_CONFIG_STATIC4
1385 */
1386
1387 /* ACCEL_AAF_DELTSQR */
1388 #define BIT_ACCEL_AAF_DELTSQR_POS_HI 0
1389 #define BIT_ACCEL_AAF_DELTSQR_MASK_HI (0x0F << BIT_ACCEL_AAF_DELTSQR_POS_HI)
1390
1391 /* ACCEL_AAF_BITSHIFT */
1392 #define BIT_ACCEL_AAF_BITSHIFT_POS 4
1393 #define BIT_ACCEL_AAF_BITSHIFT_MASK (0x0F << BIT_ACCEL_AAF_BITSHIFT_POS)
1394
1395 /*
1396 * MPUREG_OIS1_CONFIG1_B2
1397 * Register Name: OIS1_CONFIG1
1398 */
1399
1400 /* OIS1_ACCEL_LP_CLK_SEL */
1401 #define BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS 5
1402 #define BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_MASK (0x1 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS)
1403
1404 typedef enum
1405 {
1406 IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC = (0x0 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS),
1407 IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC = (0x1 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS),
1408 } IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_t;
1409
1410 /* OIS1_DEC */
1411 #define BIT_OIS1_CONFIG1_DEC_POS 2
1412 #define BIT_OIS1_CONFIG1_DEC_MASK (0x7 << BIT_OIS1_CONFIG1_DEC_POS)
1413
1416 typedef enum
1417 {
1418 IXM42XXX_OIS1_CONFIG1_DEC_1 = (0x0 << BIT_OIS1_CONFIG1_DEC_POS),
1419 IXM42XXX_OIS1_CONFIG1_DEC_2 = (0x1 << BIT_OIS1_CONFIG1_DEC_POS),
1420 IXM42XXX_OIS1_CONFIG1_DEC_4 = (0x2 << BIT_OIS1_CONFIG1_DEC_POS),
1421 IXM42XXX_OIS1_CONFIG1_DEC_8 = (0x3 << BIT_OIS1_CONFIG1_DEC_POS),
1422 IXM42XXX_OIS1_CONFIG1_DEC_16 = (0x4 << BIT_OIS1_CONFIG1_DEC_POS),
1423 IXM42XXX_OIS1_CONFIG1_DEC_32 = (0x5 << BIT_OIS1_CONFIG1_DEC_POS),
1424 } IXM42XXX_OIS1_CONFIG1_DEC_t;
1425
1426 /* GYRO_OIS1_EN */
1427 #define BIT_OIS1_CONFIG1_GYRO_EN_POS 1
1428 #define BIT_OIS1_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS1_CONFIG1_GYRO_EN_POS)
1429
1430 typedef enum
1431 {
1432 IXM42XXX_OIS1_CONFIG1_GYRO_EN = (0x1 << BIT_OIS1_CONFIG1_GYRO_EN_POS),
1433 IXM42XXX_OIS1_CONFIG1_GYRO_DIS = (0x0 << BIT_OIS1_CONFIG1_GYRO_EN_POS),
1434 } IXM42XXX_OIS1_CONFIG1_GYRO_EN_t;
1435
1436 /* ACCEL_OIS1_EN */
1437 #define BIT_OIS1_CONFIG1_ACCEL_EN_POS 0
1438 #define BIT_OIS1_CONFIG1_ACCEL_EN_MASK (0x1 << BIT_OIS1_CONFIG1_ACCEL_EN_POS)
1439
1440 typedef enum
1441 {
1442 IXM42XXX_OIS1_CONFIG1_ACCEL_EN = (0x1 << BIT_OIS1_CONFIG1_ACCEL_EN_POS),
1443 IXM42XXX_OIS1_CONFIG1_ACCEL_DIS = (0x0 << BIT_OIS1_CONFIG1_ACCEL_EN_POS),
1444 } IXM42XXX_OIS1_CONFIG1_ACCEL_EN_t;
1445
1446 /*
1447 * MPUREG_OIS1_CONFIG2_B2
1448 * Register Name: OIS1_CONFIG2
1449 */
1450
1451 /* GYRO_OIS1_FS_SEL */
1452 #define BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS 3
1453 #define BIT_OIS1_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS)
1454
1457 typedef enum
1458 {
1459 IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_16dps = (0x7 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1460 IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_31dps = (0x6 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1461 IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_62dps = (0x5 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1462 IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_125dps = (0x4 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1463 IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_250dps = (0x3 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1464 IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_500dps = (0x2 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1465 IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_1000dps = (0x1 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1466 IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_2000dps = (0x0 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1467 } IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_t;
1468
1469 /* ACCEL_OIS1_FS_SEL */
1470 #define BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS 0
1471 #define BIT_OIS1_CONFIG2_ACCEL_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS)
1472
1475 typedef enum
1476 {
1477 IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_RESERVED = (0x4 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1478 IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_2g = (0x3 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1479 IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_4g = (0x2 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1480 IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_8g = (0x1 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1481 IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_16g = (0x0 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1482 } IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_t;
1483
1484 /*
1485 * MPUREG_INT_STATUS_OIS1_B2
1486 * Register Name: INT_STATUS_OIS1
1487 */
1488 #define BIT_INT_STATUS_OIS1_FSYNC 0x04
1489 #define BIT_INT_STATUS_OIS1_DRDY 0x02
1490 #define BIT_INT_STATUS_OIS1_AGC_RDY 0x01
1491
1492 /*
1493 * MPUREG_OIS2_CONFIG1_B2
1494 * Register Name: OIS2_CONFIG1
1495 */
1496
1497 /* OIS2_ACCEL_LP_CLK_SEL */
1498 #define BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS 5
1499 #define BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_MASK (0x1 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS)
1500
1501 typedef enum
1502 {
1503 IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC = (0x0 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS),
1504 IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC = (0x1 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS),
1505 } IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_t;
1506
1507 /* OIS2_DEC */
1508 #define BIT_OIS2_CONFIG1_DEC_POS 2
1509 #define BIT_OIS2_CONFIG1_DEC_MASK (0x7 << BIT_OIS2_CONFIG1_DEC_POS)
1510
1513 typedef enum
1514 {
1515 IXM42XXX_OIS2_CONFIG1_DEC_1 = (0x0 << BIT_OIS2_CONFIG1_DEC_POS),
1516 IXM42XXX_OIS2_CONFIG1_DEC_2 = (0x1 << BIT_OIS2_CONFIG1_DEC_POS),
1517 IXM42XXX_OIS2_CONFIG1_DEC_4 = (0x2 << BIT_OIS2_CONFIG1_DEC_POS),
1518 IXM42XXX_OIS2_CONFIG1_DEC_8 = (0x3 << BIT_OIS2_CONFIG1_DEC_POS),
1519 IXM42XXX_OIS2_CONFIG1_DEC_16 = (0x4 << BIT_OIS2_CONFIG1_DEC_POS),
1520 IXM42XXX_OIS2_CONFIG1_DEC_32 = (0x5 << BIT_OIS2_CONFIG1_DEC_POS),
1521 } IXM42XXX_OIS2_CONFIG1_DEC_t;
1522
1523 /* GYRO_OIS2_EN */
1524 #define BIT_OIS2_CONFIG1_GYRO_EN_POS 1
1525 #define BIT_OIS2_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS2_CONFIG1_GYRO_EN_POS)
1526
1527 typedef enum
1528 {
1529 IXM42XXX_OIS2_CONFIG1_GYRO_EN = (0x1 << BIT_OIS2_CONFIG1_GYRO_EN_POS),
1530 IXM42XXX_OIS2_CONFIG1_GYRO_DIS = (0x0 << BIT_OIS2_CONFIG1_GYRO_EN_POS),
1531 } IXM42XXX_OIS2_CONFIG1_GYRO_EN_t;
1532
1533 /* ACCEL_OIS2_EN */
1534 #define BIT_OIS2_CONFIG1_ACCEL_EN_POS 0
1535 #define BIT_OIS2_CONFIG1_ACCEL_EN_MASK (0x1 << BIT_OIS2_CONFIG1_ACCEL_EN_POS)
1536
1537 typedef enum
1538 {
1539 IXM42XXX_OIS2_CONFIG1_ACCEL_EN = (0x1 << BIT_OIS2_CONFIG1_ACCEL_EN_POS),
1540 IXM42XXX_OIS2_CONFIG1_ACCEL_DIS = (0x0 << BIT_OIS2_CONFIG1_ACCEL_EN_POS),
1541 } IXM42XXX_OIS2_CONFIG1_ACCEL_EN_t;
1542
1543 /*
1544 * MPUREG_OIS2_CONFIG2_B2
1545 * Register Name: OIS2_CONFIG2
1546 */
1547
1548 /* GYRO_OIS2_FS_SEL */
1549 #define BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS 3
1550 #define BIT_OIS2_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS)
1551
1554 typedef enum
1555 {
1556 IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_16dps = (0x7 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1557 IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_31dps = (0x6 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1558 IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_62dps = (0x5 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1559 IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_125dps = (0x4 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1560 IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_250dps = (0x3 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1561 IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_500dps = (0x2 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1562 IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_1000dps = (0x1 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1563 IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_2000dps = (0x0 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1564 } IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_t;
1565
1566 /* ACCEL_OIS2_FS_SEL */
1567 #define BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS 0
1568 #define BIT_OIS2_CONFIG2_ACCEL_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS)
1569
1572 typedef enum
1573 {
1574 IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_RESERVED = (0x4 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1575 IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_2g = (0x3 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1576 IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_4g = (0x2 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1577 IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_8g = (0x1 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1578 IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_16g = (0x0 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1579 } IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_t;
1580
1581
1582 /*
1583 * MPUREG_INT_STATUS_OIS2_B2
1584 * Register Name: INT_STATUS_OIS2
1585 */
1586 #define BIT_INT_STATUS_OIS2_FSYNC 0x04
1587 #define BIT_INT_STATUS_OIS2_DRDY 0x02
1588 #define BIT_INT_STATUS_OIS2_AGC_RDY 0x01
1589
1590
1591 /* ----------------------------------------------------------------------------
1592 * Register bank 4
1593 * ---------------------------------------------------------------------------- */
1594
1595
1596 /*
1597 * MPUREG_APEX_CONFIG1_B4
1598 * Register Name: APEX_CONFIG1
1599 */
1600
1601 /* DMP_POWER_SAVE_TIME_SEL */
1602
1603 #define BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_POS 0
1604 #define BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_MASK 0x0F
1605
1606 typedef enum
1607 {
1608 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_0S = 0x0,
1609 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_4S = 0x1,
1610 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_8S = 0x2,
1611 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_12S = 0x3,
1612 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_16S = 0x4,
1613 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_20S = 0x5,
1614 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_24S = 0x6,
1615 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_28S = 0x7,
1616 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_32S = 0x8,
1617 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_36S = 0x9,
1618 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_40S = 0xA,
1619 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_44S = 0xB,
1620 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_48S = 0xC,
1621 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_52S = 0xD,
1622 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_56S = 0xE,
1623 IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_60S = 0xF
1624 } IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t;
1625
1626 /* LOW_ENERGY_AMP_TH_SEL */
1627
1628 #define BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS 4
1629 #define BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_MASK (0x0F << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS)
1630
1631 typedef enum
1632 {
1633 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1006632MG = (0 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1634 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1174405MG = (1 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1635 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1342177MG = (2 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1636 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1509949MG = (3 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1637 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1677721MG = (4 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1638 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1845493MG = (5 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1639 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2013265MG = (6 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1640 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2181038MG = (7 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1641 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2348810MG = (8 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1642 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2516582MG = (9 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1643 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2684354MG = (10 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1644 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2852126MG = (11 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1645 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3019898MG = (12 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1646 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3187671MG = (13 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1647 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3355443MG = (14 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1648 IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3523215MG = (15 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS)
1649 } IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t;
1650
1651 /*
1652 * MPUREG_APEX_CONFIG2_B4
1653 * Register Name: APEX_CONFIG2
1654 */
1655
1656 /* PEDO_AMP_TH_SEL */
1657
1658 #define BIT_APEX_CONFIG2_PEDO_AMP_TH_POS 4
1659 #define BIT_APEX_CONFIG2_PEDO_AMP_TH_MASK (0x0F<<BIT_APEX_CONFIG2_PEDO_AMP_TH_POS)
1660
1661 typedef enum
1662 {
1663 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1006632_MG = (0 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1664 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1140850_MG = (1 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1665 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1275068_MG = (2 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1666 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1409286_MG = (3 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1667 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1543503_MG = (4 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1668 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1677721_MG = (5 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1669 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1811939_MG = (6 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1670 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1946157_MG = (7 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1671 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2080374_MG = (8 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1672 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2214592_MG = (9 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1673 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2348810_MG = (10 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1674 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2483027_MG = (11 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1675 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2617245_MG = (12 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1676 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2751463_MG = (13 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1677 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2885681_MG = (14 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1678 IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_3019898_MG = (15 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS)
1679 } IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_t;
1680
1681 /* PEDO_STEP_CNT_TH_SEL */
1682
1683 #define BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_POS 0
1684 #define BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_MASK 0x0F
1685
1686 /*
1687 * MPUREG_APEX_CONFIG3_B4
1688 * Register Name: APEX_CONFIG3
1689 */
1690
1691 /* PEDO_STEP_DET_TH_SEL */
1692
1693 #define BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS 5
1694 #define BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_MASK (0x07<<BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS)
1695
1696 /* PEDO_SB_TIMER_TH_SEL */
1697
1698 #define BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS 2
1699 #define BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_MASK (0x07<<BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS)
1700
1701 typedef enum
1702 {
1703 IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_50_SAMPLES = (0 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1704 IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_75_SAMPLES = (1 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1705 IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_100_SAMPLES = (2 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1706 IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_125_SAMPLES = (3 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1707 IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_150_SAMPLES = (4 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1708 IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_175_SAMPLES = (5 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1709 IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_200_SAMPLES = (6 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1710 IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_225_SAMPLES = (7 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS)
1711 } IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t;
1712
1713 /* PEDO_HI_ENRGY_TH_SEL */
1714
1715 #define BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_POS 0
1716 #define BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_MASK 0x03
1717
1718 typedef enum
1719 {
1720 IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_90 = 0x0,
1721 IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_107 = 0x1,
1722 IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_136 = 0x2,
1723 IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_159 = 0x3
1724 } IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t;
1725
1726 /*
1727 * MPUREG_APEX_CONFIG4_B4
1728 * Register Name: APEX_CONFIG4
1729 */
1730
1731 /* TILT_WAIT_TIME_SEL */
1732
1733 #define BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS 6
1734 #define BIT_APEX_CONFIG4_TILT_WAIT_TIME_MASK (0x03<<BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS)
1735
1736 typedef enum
1737 {
1738 IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_0 = (0 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS),
1739 IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_2S = (1 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS),
1740 IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_4S = (2 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS),
1741 IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_6S = (3 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS)
1742 } IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_t;
1743
1744 /* R2W_SLEEP_TIME_OUT */
1745
1746 #define BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS 3
1747 #define BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_MASK (0x07<<BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS)
1748
1749 typedef enum
1750 {
1751 IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_1_28S = (0 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1752 IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_2_56S = (1 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1753 IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_3_84S = (2 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1754 IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_5_12S = (3 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1755 IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_6_4S = (4 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1756 IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_7_68S = (5 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1757 IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_8_96S = (6 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1758 IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_10_24S = (7 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS)
1759 } IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t;
1760
1761 /*
1762 * MPUREG_APEX_CONFIG5_B4
1763 * Register Name: APEX_CONFIG5
1764 */
1765
1766 /* R2W_MOUNTING_MATRIX */
1767
1768 #define BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS 0
1769 #define BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_MASK (0x07<<BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS)
1770
1771 typedef enum
1772 {
1773 IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_0 = (0 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1774 IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_1 = (1 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1775 IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_2 = (2 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1776 IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_3 = (3 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1777 IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_4 = (4 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1778 IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_5 = (5 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1779 IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_6 = (6 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1780 IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_7 = (7 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS)
1781 } IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t;
1782
1783 /*
1784 * MPUREG_APEX_CONFIG6_B4
1785 * Register Name: APEX_CONFIG6
1786 */
1787
1788 /* R2W_SLEEP_GEST_DELAY */
1789
1790 #define BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS 0
1791 #define BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_MASK (0x07<<BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS)
1792
1793 typedef enum
1794 {
1795 IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_32S = (0 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1796 IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_64S = (1 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1797 IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_96S = (2 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1798 IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_28S = (3 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1799 IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_6S = (4 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1800 IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_92S = (5 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1801 IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_24S = (6 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1802 IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_56S = (7 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS)
1803 } IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t;
1804
1805 /*
1806 * MPUREG_APEX_CONFIG7_B4
1807 * Register Name: APEX_CONFIG7
1808 */
1809
1810 /* TAP_MIN_JERK_THR */
1811 #define BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS 2
1812 #define BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_MASK (0x3F << BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS)
1813
1814 #define IXM42XXX_APEX_CONFIG7_TAP_MIN_JERK_THR_281MG_DEFAULT 0x11
1815
1816 /* TAP_MAX_PEAK_TOL */
1817 #define BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_POS 0
1818 #define BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_MASK 0x3
1819
1820 typedef enum
1821 {
1822 IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_12 = 0x0,
1823 IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_25 = 0x1,
1824 IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_37 = 0x2,
1825 IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_50 = 0x3
1826 } IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t;
1827
1828 /*
1829 * MPUREG_APEX_CONFIG8_B4
1830 * Register Name: APEX_CONFIG8
1831 */
1832
1833 /* TAP_TMAX */
1834 #define BIT_APEX_CONFIG8_TAP_TMAX_POS 5
1835 #define BIT_APEX_CONFIG8_TAP_TMAX_MASK (0x03 << BIT_APEX_CONFIG8_TAP_TMAX_POS)
1836
1837 typedef enum
1838 {
1839 IXM42XXX_APEX_CONFIG8_TAP_TMAX_250MS = (0 << BIT_APEX_CONFIG8_TAP_TMAX_POS),
1840 IXM42XXX_APEX_CONFIG8_TAP_TMAX_375MS = (1 << BIT_APEX_CONFIG8_TAP_TMAX_POS),
1841 IXM42XXX_APEX_CONFIG8_TAP_TMAX_500MS = (2 << BIT_APEX_CONFIG8_TAP_TMAX_POS),
1842 IXM42XXX_APEX_CONFIG8_TAP_TMAX_625MS = (3 << BIT_APEX_CONFIG8_TAP_TMAX_POS)
1843 } IXM42XXX_APEX_CONFIG8_TAP_TMAX_t;
1844
1845 /* TAP_TAVG */
1846 #define BIT_APEX_CONFIG8_TAP_TAVG_POS 3
1847 #define BIT_APEX_CONFIG8_TAP_TAVG_MASK (0x03 << BIT_APEX_CONFIG8_TAP_TAVG_POS)
1848
1849 typedef enum
1850 {
1851 IXM42XXX_APEX_CONFIG8_TAP_TAVG_1SAMPLE = (0 << BIT_APEX_CONFIG8_TAP_TAVG_POS),
1852 IXM42XXX_APEX_CONFIG8_TAP_TAVG_2SAMPLE = (1 << BIT_APEX_CONFIG8_TAP_TAVG_POS),
1853 IXM42XXX_APEX_CONFIG8_TAP_TAVG_4SAMPLE = (2 << BIT_APEX_CONFIG8_TAP_TAVG_POS),
1854 IXM42XXX_APEX_CONFIG8_TAP_TAVG_8SAMPLE = (3 << BIT_APEX_CONFIG8_TAP_TAVG_POS)
1855 } IXM42XXX_APEX_CONFIG8_TAP_TAVG_t;
1856
1857 /* TAP_TMIN */
1858 #define BIT_APEX_CONFIG8_TAP_TMIN_POS 0
1859 #define BIT_APEX_CONFIG8_TAP_TMIN_MASK 0x07
1860
1861 typedef enum
1862 {
1863 IXM42XXX_APEX_CONFIG8_TAP_TMIN_125MS = 0x0,
1864 IXM42XXX_APEX_CONFIG8_TAP_TMIN_140MS = 0x1,
1865 IXM42XXX_APEX_CONFIG8_TAP_TMIN_156MS = 0x2,
1866 IXM42XXX_APEX_CONFIG8_TAP_TMIN_171MS = 0x3,
1867 IXM42XXX_APEX_CONFIG8_TAP_TMIN_187MS = 0x4,
1868 IXM42XXX_APEX_CONFIG8_TAP_TMIN_203MS = 0x5,
1869 IXM42XXX_APEX_CONFIG8_TAP_TMIN_218MS = 0x6,
1870 IXM42XXX_APEX_CONFIG8_TAP_TMIN_234MS = 0x7
1871 } IXM42XXX_APEX_CONFIG8_TAP_TMIN_t;
1872
1873 /*
1874 * MPUREG_APEX_CONFIG9_B4
1875 * Register Name: APEX_CONFIG9
1876 */
1877 #define BIT_APEX_CONFIG9_SENSITIVITY_MODE_POS 0
1878 #define BIT_APEX_CONFIG9_SENSITIVITY_MODE_MASK 0x01
1879 typedef enum
1880 {
1881 IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_NORMAL = 0x00,
1882 IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_RESERVED = 0x01
1883 } IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_t;
1884
1885 /*
1886 * MPUREG_INT_SOURCE6_B4
1887 * Register Name: INT_SOURCE6
1888 */
1889 #define BIT_INT_STEP_DET_INT_EN_POS 5
1890 #define BIT_INT_STEP_CNT_OVFL_INT_EN_POS 4
1891 #define BIT_INT_TILT_DET_INT_EN_POS 3
1892 #define BIT_INT_WAKE_DET_INT_EN_POS 2
1893 #define BIT_INT_SLEEP_DET_INT_EN_POS 1
1894 #define BIT_INT_TAP_DET_INT_EN_POS 0
1895
1896 #define BIT_INT_SOURCE6_STEP_DET_INT1_EN 0x20
1897 #define BIT_INT_SOURCE6_STEP_CNT_OVFL_INT1_EN 0x10
1898 #define BIT_INT_SOURCE6_TILT_DET_INT1_EN 0x8
1899 #define BIT_INT_SOURCE6_WAKE_DET_INT1_EN 0x4
1900 #define BIT_INT_SOURCE6_SLEEP_DET_INT1_EN 0x2
1901 #define BIT_INT_SOURCE6_TAP_DET_INT1_EN 0x1
1902
1903 /*
1904 * MPUREG_INT_SOURCE7_B4
1905 * Register Name: INT_SOURCE7
1906 */
1907 #define BIT_INT_SOURCE7_STEP_DET_INT2_EN 0x20
1908 #define BIT_INT_SOURCE7_STEP_CNT_OVFL_INT2_EN 0x10
1909 #define BIT_INT_SOURCE7_TILT_DET_INT2_EN 0x8
1910 #define BIT_INT_SOURCE7_WAKE_DET_INT2_EN 0x4
1911 #define BIT_INT_SOURCE7_SLEEP_DET_INT2_EN 0x2
1912 #define BIT_INT_SOURCE7_TAP_DET_INT2_EN 0x1
1913
1914 /*
1915 * MPUREG_INT_SOURCE8_B4
1916 * Register Name: INT_SOURCE8
1917 */
1918 #define BIT_INT_OIS1_DRDY_IBI_EN_POS 6
1919 #define BIT_INT_UI_FSYNC_IBI_EN_POS 5
1920 #define BIT_INT_PLL_RDY_IBI_EN_POS 4
1921 #define BIT_INT_UI_DRDY_IBI_EN_POS 3
1922 #define BIT_INT_FIFO_THS_IBI_EN_POS 2
1923 #define BIT_INT_FIFO_FULL_IBI_EN_POS 1
1924 #define BIT_INT_UI_AGC_RDY_IBI_EN_POS 0
1925
1926 #define BIT_INT_SOURCE8_OIS1_DRDY_IBI_EN 0x40
1927 #define BIT_INT_SOURCE8_UI_FSYNC_IBI_EN 0x20
1928 #define BIT_INT_SOURCE8_PLL_RDY_IBI_EN 0x10
1929 #define BIT_INT_SOURCE8_UI_DRDY_IBI_EN 0x08
1930 #define BIT_INT_SOURCE8_FIFO_THS_IBI_EN 0x04
1931 #define BIT_INT_SOURCE8_FIFO_FULL_IBI_EN 0x02
1932 #define BIT_INT_SOURCE8_UI_AGC_RDY_IBI_EN 0x01
1933
1934 /*
1935 * MPUREG_INT_SOURCE9_B4
1936 * Register Name: INT_SOURCE9
1937 */
1938 #define BIT_INT_SMD_IBI_EN_POS 4
1939 #define BIT_INT_WOM_Z_IBI_EN_POS 3
1940 #define BIT_INT_WOM_Y_IBI_EN_POS 2
1941 #define BIT_INT_WOM_X_IBI_EN_POS 1
1942
1943 #define BIT_INT_SOURCE9_SMD_IBI_EN 0x10
1944 #define BIT_INT_SOURCE9_WOM_Z_IBI_EN 0x08
1945 #define BIT_INT_SOURCE9_WOM_Y_IBI_EN 0x04
1946 #define BIT_INT_SOURCE9_WOM_X_IBI_EN 0x02
1947
1948 /*
1949 * MPUREG_INT_SOURCE10_B4
1950 * Register Name: INT_SOURCE10
1951 */
1952 #define BIT_INT_STEP_DET_IBI_EN_POS 5
1953 #define BIT_INT_STEP_CNT_OVFL_IBI_EN_POS 4
1954 #define BIT_INT_TILT_DET_IBI_EN_POS 3
1955 #define BIT_INT_WAKE_DET_IBI_EN_POS 2
1956 #define BIT_INT_SLEEP_DET_IBI_EN_POS 1
1957 #define BIT_INT_TAP_DET_IBI_EN_POS 0
1958
1959 #define BIT_INT_SOURCE10_STEP_DET_IBI_EN 0x20
1960 #define BIT_INT_SOURCE10_STEP_CNT_OVFL_IBI_EN 0x10
1961 #define BIT_INT_SOURCE10_TILT_DET_IBI_EN 0x08
1962 #define BIT_INT_SOURCE10_WAKE_DET_IBI_EN 0x04
1963 #define BIT_INT_SOURCE10_SLEEP_DET_IBI_EN 0x02
1964 #define BIT_INT_SOURCE10_TAP_DET_IBI_EN 0x01
1965
1966 /*
1967 * MPUREG_OFFSET_USER_0_B4
1968 * Register Name: OFFSET_USER0
1969 */
1970
1971 /* GYRO_X_OFFUSER */
1972 #define BIT_GYRO_X_OFFUSER_POS_LO 0
1973 #define BIT_GYRO_X_OFFUSER_MASK_LO (0xFF << BIT_GYRO_X_OFFUSER_POS_LO)
1974
1975 /*
1976 * MPUREG_OFFSET_USER_1_B4
1977 * Register Name: OFFSET_USER1
1978 */
1979
1980 #define BIT_GYRO_X_OFFUSER_POS_HI 0
1981 #define BIT_GYRO_X_OFFUSER_MASK_HI (0x0F << BIT_GYRO_X_OFFUSER_POS_HI)
1982
1983 /* GYRO_Y_OFFUSER */
1984 #define BIT_GYRO_Y_OFFUSER_POS_HI 4
1985 #define BIT_GYRO_Y_OFFUSER_MASK_HI (0x0F << BIT_GYRO_Y_OFFUSER_POS_HI)
1986
1987 /*
1988 * MPUREG_OFFSET_USER_2_B4
1989 * Register Name: OFFSET_USER2
1990 */
1991
1992 #define BIT_GYRO_Y_OFFUSER_POS_LO 0
1993 #define BIT_GYRO_Y_OFFUSER_MASK_LO (0xFF << BIT_GYRO_Y_OFFUSER_POS_LO)
1994
1995 /*
1996 * MPUREG_OFFSET_USER_3_B4
1997 * Register Name: OFFSET_USER3
1998 */
1999
2000 /* GYRO_Z_OFFUSER */
2001 #define BIT_GYRO_Z_OFFUSER_POS_LO 0
2002 #define BIT_GYRO_Z_OFFUSER_MASK_LO (0xFF << BIT_GYRO_Z_OFFUSER_POS_LO)
2003
2004 /*
2005 * MPUREG_OFFSET_USER_4_B4
2006 * Register Name: OFFSET_USER4
2007 */
2008
2009 #define BIT_GYRO_Z_OFFUSER_POS_HI 0
2010 #define BIT_GYRO_Z_OFFUSER_MASK_HI (0x0F << BIT_GYRO_Z_OFFUSER_POS_HI)
2011
2012 /* ACCEL_X_OFFUSER */
2013 #define BIT_ACCEL_X_OFFUSER_POS_HI 4
2014 #define BIT_ACCEL_X_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_X_OFFUSER_POS_HI)
2015
2016 /*
2017 * MPUREG_OFFSET_USER_5_B4
2018 * Register Name: OFFSET_USER5
2019 */
2020
2021 #define BIT_ACCEL_X_OFFUSER_POS_LO 0
2022 #define BIT_ACCEL_X_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_X_OFFUSER_POS_LO)
2023
2024 /*
2025 * MPUREG_OFFSET_USER_6_B4
2026 * Register Name: OFFSET_USER_6
2027 */
2028
2029 /* ACCEL_Y_OFFUSER */
2030 #define BIT_ACCEL_Y_OFFUSER_POS_LO 0
2031 #define BIT_ACCEL_Y_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_Y_OFFUSER_POS_LO)
2032
2033
2034 /*
2035 * MPUREG_OFFSET_USER_7_B4
2036 * Register Name: OFFSET_USER_7
2037 */
2038
2039 #define BIT_ACCEL_Y_OFFUSER_POS_HI 0
2040 #define BIT_ACCEL_Y_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_Y_OFFUSER_POS_HI)
2041
2042 /* ACCEL_Z_OFFUSER */
2043 #define BIT_ACCEL_Z_OFFUSER_POS_HI 4
2044 #define BIT_ACCEL_Z_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_Z_OFFUSER_POS_HI)
2045
2046 /*
2047 * MPUREG_OFFSET_USER_8_B4
2048 * Register Name: OFFSET_USER_8
2049 */
2050
2051 /* ACCEL_Z_OFFUSER_L */
2052 #define BIT_ACCEL_Z_OFFUSER_POS_LO 0
2053 #define BIT_ACCEL_Z_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_Z_OFFUSER_POS_LO)
2054
2055 #ifdef __cplusplus
2056 }
2057 #endif
2058
2059 #endif /* #ifndef _INV_IXM42XXX_DEFS_H_ */
BIT_FIFO_CONFIG1_HIRES_POS
#define BIT_FIFO_CONFIG1_HIRES_POS
Definition: Ixm42xxxDefs.h:1047
IXM42XXX_APEX_CONFIG0_DMP_ODR_RESERVED
@ IXM42XXX_APEX_CONFIG0_DMP_ODR_RESERVED
Definition: Ixm42xxxDefs.h:989
IXM42XXX_INT_CONFIG_INT1_POLARITY_LOW
@ IXM42XXX_INT_CONFIG_INT1_POLARITY_LOW
Definition: Ixm42xxxDefs.h:368
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t
Definition: Ixm42xxxDefs.h:848
IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_OD
@ IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_OD
Definition: Ixm42xxxDefs.h:358
IXM42XXX_FIFO_CONFIG1_GYRO_t
IXM42XXX_FIFO_CONFIG1_GYRO_t
Definition: Ixm42xxxDefs.h:1081
IXM42XXX_APEX_CONFIG8_TAP_TMIN_t
IXM42XXX_APEX_CONFIG8_TAP_TMIN_t
Definition: Ixm42xxxDefs.h:1862
IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_1_2
@ IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_1_2
Definition: Ixm42xxxDefs.h:606
IXM42XXX_PWR_MGMT_0_ACCEL_MODE_LN
@ IXM42XXX_PWR_MGMT_0_ACCEL_MODE_LN
Definition: Ixm42xxxDefs.h:677
IXM42XXX_GYRO_CONFIG0_FS_SEL_16dps
@ IXM42XXX_GYRO_CONFIG0_FS_SEL_16dps
Definition: Ixm42xxxDefs.h:705
BIT_SENSOR_CONFIG2_OIS_MODE_POS
#define BIT_SENSOR_CONFIG2_OIS_MODE_POS
Definition: Ixm42xxxDefs.h:1235
IXM42XXX_GYRO_CONFIG0_FS_SEL_62dps
@ IXM42XXX_GYRO_CONFIG0_FS_SEL_62dps
Definition: Ixm42xxxDefs.h:707
IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_t
IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_t
Definition: Ixm42xxxDefs.h:416
BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS
#define BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS
Definition: Ixm42xxxDefs.h:332
BIT_PWR_MGMT_0_IDLE_POS
#define BIT_PWR_MGMT_0_IDLE_POS
Definition: Ixm42xxxDefs.h:651
IXM42XXX_DEVICE_CONFIG_SPI_MODE_t
IXM42XXX_DEVICE_CONFIG_SPI_MODE_t
Definition: Ixm42xxxDefs.h:296
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_100_SAMPLES
@ IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_100_SAMPLES
Definition: Ixm42xxxDefs.h:1705
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_31dps
@ IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_31dps
Definition: Ixm42xxxDefs.h:1460
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_31dps
@ IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_31dps
Definition: Ixm42xxxDefs.h:1557
IXM42XXX_TMST_CONFIG_RESOL_16us
@ IXM42XXX_TMST_CONFIG_RESOL_16us
Definition: Ixm42xxxDefs.h:900
IXM42XXX_GYRO_CONFIG0_ODR_1_KHZ
@ IXM42XXX_GYRO_CONFIG0_ODR_1_KHZ
Definition: Ixm42xxxDefs.h:730
BIT_FIFO_CONFIG1_TMST_FSYNC_POS
#define BIT_FIFO_CONFIG1_TMST_FSYNC_POS
Definition: Ixm42xxxDefs.h:1057
BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS
#define BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS
Definition: Ixm42xxxDefs.h:885
BIT_OIS2_CONFIG1_DEC_POS
#define BIT_OIS2_CONFIG1_DEC_POS
Definition: Ixm42xxxDefs.h:1508
IXM42XXX_APEX_CONFIG8_TAP_TMAX_500MS
@ IXM42XXX_APEX_CONFIG8_TAP_TMAX_500MS
Definition: Ixm42xxxDefs.h:1841
fifo_header_t::msg_bit
unsigned char msg_bit
Definition: Ixm42xxxDefs.h:253
IXM42XXX_OIS2_CONFIG1_GYRO_DIS
@ IXM42XXX_OIS2_CONFIG1_GYRO_DIS
Definition: Ixm42xxxDefs.h:1530
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_0
@ IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_0
Definition: Ixm42xxxDefs.h:1773
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_96S
@ IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_96S
Definition: Ixm42xxxDefs.h:1797
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t
Definition: Ixm42xxxDefs.h:1794
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_4
@ IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_4
Definition: Ixm42xxxDefs.h:1777
IXM42XXX_PWR_MGMT_0_GYRO_MODE_STANDBY
@ IXM42XXX_PWR_MGMT_0_GYRO_MODE_STANDBY
Definition: Ixm42xxxDefs.h:667
IXM42XXX_APEX_CONFIG0_TAP_ENABLE_DIS
@ IXM42XXX_APEX_CONFIG0_TAP_ENABLE_DIS
Definition: Ixm42xxxDefs.h:946
IXM42XXX_PWR_MGMT_0_TEMP_EN
@ IXM42XXX_PWR_MGMT_0_TEMP_EN
Definition: Ixm42xxxDefs.h:647
IXM42XXX_SMD_CONFIG_WOM_INT_MODE_ANDED
@ IXM42XXX_SMD_CONFIG_WOM_INT_MODE_ANDED
Definition: Ixm42xxxDefs.h:1003
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_20S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_20S
Definition: Ixm42xxxDefs.h:1613
IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_OTHER
@ IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_OTHER
Definition: Ixm42xxxDefs.h:417
IXM42XXX_APEX_CONFIG0_DMP_ODR_25Hz
@ IXM42XXX_APEX_CONFIG0_DMP_ODR_25Hz
Definition: Ixm42xxxDefs.h:987
IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_3RD_ORDER
@ IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_3RD_ORDER
Definition: Ixm42xxxDefs.h:808
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1946157_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1946157_MG
Definition: Ixm42xxxDefs.h:1670
IXM42XXX_TMST_CONFIG_TMST_TO_REGS_EN_t
IXM42XXX_TMST_CONFIG_TMST_TO_REGS_EN_t
Definition: Ixm42xxxDefs.h:889
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_5
@ IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_5
Definition: Ixm42xxxDefs.h:1778
BIT_INTF_CONFIG4_AP_SPI_POS
#define BIT_INTF_CONFIG4_AP_SPI_POS
Definition: Ixm42xxxDefs.h:1306
IXM42XXX_TMST_CONFIG_TMST_EN_t
IXM42XXX_TMST_CONFIG_TMST_EN_t
Definition: Ixm42xxxDefs.h:919
IXM42XXX_INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN
@ IXM42XXX_INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN
Definition: Ixm42xxxDefs.h:576
fifo_header_t::gyro_odr_different
unsigned char gyro_odr_different
Definition: Ixm42xxxDefs.h:246
IXM42XXX_APEX_CONFIG8_TAP_TAVG_2SAMPLE
@ IXM42XXX_APEX_CONFIG8_TAP_TAVG_2SAMPLE
Definition: Ixm42xxxDefs.h:1852
IXM42XXX_GYRO_NF_EN
@ IXM42XXX_GYRO_NF_EN
Definition: Ixm42xxxDefs.h:1266
IXM42XXX_FSYNC_CONFIG_UI_SEL_TEMP
@ IXM42XXX_FSYNC_CONFIG_UI_SEL_TEMP
Definition: Ixm42xxxDefs.h:1108
IXM42XXX_OIS2_CONFIG1_DEC_2
@ IXM42XXX_OIS2_CONFIG1_DEC_2
Definition: Ixm42xxxDefs.h:1516
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_2
@ IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_2
Definition: Ixm42xxxDefs.h:1775
BIT_APEX_CONFIG0_PEDO_EN_POS
#define BIT_APEX_CONFIG0_PEDO_EN_POS
Definition: Ixm42xxxDefs.h:950
IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_t
IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_t
OIS2 accelerometer FSR selection.
Definition: Ixm42xxxDefs.h:1573
IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_12
@ IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_12
Definition: Ixm42xxxDefs.h:1822
IXM42XXX_SENSOR_CONFIG2_OIS_MODE_8KHZ
@ IXM42XXX_SENSOR_CONFIG2_OIS_MODE_8KHZ
Definition: Ixm42xxxDefs.h:1241
IXM42XXX_TMST_CONFIG_TMST_FSYNC_DIS
@ IXM42XXX_TMST_CONFIG_TMST_FSYNC_DIS
Definition: Ixm42xxxDefs.h:911
IXM42XXX_TMST_CONFIG_TMST_DIS
@ IXM42XXX_TMST_CONFIG_TMST_DIS
Definition: Ixm42xxxDefs.h:921
IXM42XXX_OIS2_CONFIG1_DEC_4
@ IXM42XXX_OIS2_CONFIG1_DEC_4
Definition: Ixm42xxxDefs.h:1517
IXM42XXX_PWR_MGMT_0_IDLE_DIS
@ IXM42XXX_PWR_MGMT_0_IDLE_DIS
Definition: Ixm42xxxDefs.h:656
IXM42XXX_FIFO_CONFIG1_ACCEL_t
IXM42XXX_FIFO_CONFIG1_ACCEL_t
Definition: Ixm42xxxDefs.h:1091
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1174405MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1174405MG
Definition: Ixm42xxxDefs.h:1634
IXM42XXX_GYRO_AAF_DIS
@ IXM42XXX_GYRO_AAF_DIS
Definition: Ixm42xxxDefs.h:1258
IXM42XXX_DEVICE_CONFIG_SPI_MODE_1_2
@ IXM42XXX_DEVICE_CONFIG_SPI_MODE_1_2
Definition: Ixm42xxxDefs.h:297
IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC
@ IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC
Definition: Ixm42xxxDefs.h:1407
BIT_APEX_DATA4_TAP_AXIS_POS
#define BIT_APEX_DATA4_TAP_AXIS_POS
Definition: Ixm42xxxDefs.h:453
IXM42XXX_FIFO_CONFIG1_TEMP_t
IXM42XXX_FIFO_CONFIG1_TEMP_t
Definition: Ixm42xxxDefs.h:1071
IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_2ND_ORDER
@ IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_2ND_ORDER
Definition: Ixm42xxxDefs.h:807
BIT_OIS1_CONFIG1_ACCEL_EN_POS
#define BIT_OIS1_CONFIG1_ACCEL_EN_POS
Definition: Ixm42xxxDefs.h:1437
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_62dps
@ IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_62dps
Definition: Ixm42xxxDefs.h:1558
IXM42XXX_SENSOR_CONFIG2_OIS_MODE_DIS
@ IXM42XXX_SENSOR_CONFIG2_OIS_MODE_DIS
Definition: Ixm42xxxDefs.h:1242
IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_t
IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_t
Definition: Ixm42xxxDefs.h:869
IXM42XXX_GYRO_CONFIG0_ODR_200_HZ
@ IXM42XXX_GYRO_CONFIG0_ODR_200_HZ
Definition: Ixm42xxxDefs.h:729
IXM42XXX_ACCEL_CONFIG0_FS_SEL_16g
@ IXM42XXX_ACCEL_CONFIG0_FS_SEL_16g
Definition: Ixm42xxxDefs.h:762
IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_50
@ IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_50
Definition: Ixm42xxxDefs.h:1825
IXM42XXX_GYRO_CONFIG0_FS_SEL_500dps
@ IXM42XXX_GYRO_CONFIG0_FS_SEL_500dps
Definition: Ixm42xxxDefs.h:710
BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS
#define BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS
Definition: Ixm42xxxDefs.h:516
BIT_FIFO_CONFIG_MODE_POS
#define BIT_FIFO_CONFIG_MODE_POS
Definition: Ixm42xxxDefs.h:377
BIT_TMST_CONFIG_RESOL_POS
#define BIT_TMST_CONFIG_RESOL_POS
Definition: Ixm42xxxDefs.h:895
IXM42XXX_OIS2_CONFIG1_DEC_8
@ IXM42XXX_OIS2_CONFIG1_DEC_8
Definition: Ixm42xxxDefs.h:1518
IXM42XXX_INT_CONFIG1_ASY_RST_ENABLED
@ IXM42XXX_INT_CONFIG1_ASY_RST_ENABLED
Definition: Ixm42xxxDefs.h:1129
IXM42XXX_ACCEL_AAF_DIS
@ IXM42XXX_ACCEL_AAF_DIS
Definition: Ixm42xxxDefs.h:1366
IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_t
IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_t
Definition: Ixm42xxxDefs.h:620
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2214592_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2214592_MG
Definition: Ixm42xxxDefs.h:1672
BIT_SIGNAL_PATH_RESET_DMP_INIT_POS
#define BIT_SIGNAL_PATH_RESET_DMP_INIT_POS
Definition: Ixm42xxxDefs.h:506
BIT_INT_CONFIG_INT2_POLARITY_POS
#define BIT_INT_CONFIG_INT2_POLARITY_POS
Definition: Ixm42xxxDefs.h:342
fifo_header_t::twentybits_bit
unsigned char twentybits_bit
Definition: Ixm42xxxDefs.h:250
IXM42XXX_SMD_CONFIG_WOM_INT_MODE_t
IXM42XXX_SMD_CONFIG_WOM_INT_MODE_t
Definition: Ixm42xxxDefs.h:1002
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_500dps
@ IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_500dps
Definition: Ixm42xxxDefs.h:1561
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_250dps
@ IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_250dps
Definition: Ixm42xxxDefs.h:1560
IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_3RD_ORDER
@ IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_3RD_ORDER
Definition: Ixm42xxxDefs.h:872
IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_1_2
@ IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_1_2
Definition: Ixm42xxxDefs.h:596
IXM42XXX_APEX_CONFIG0_PEDO_EN_t
IXM42XXX_APEX_CONFIG0_PEDO_EN_t
Definition: Ixm42xxxDefs.h:954
IXM42XXX_ACCEL_CONFIG0_ODR_12_5_HZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_12_5_HZ
Definition: Ixm42xxxDefs.h:778
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_56S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_56S
Definition: Ixm42xxxDefs.h:1622
IXM42XXX_GYRO_CONFIG0_FS_SEL_1000dps
@ IXM42XXX_GYRO_CONFIG0_FS_SEL_1000dps
Definition: Ixm42xxxDefs.h:711
IXM42XXX_APEX_CONFIG0_TAP_ENABLE_EN
@ IXM42XXX_APEX_CONFIG0_TAP_ENABLE_EN
Definition: Ixm42xxxDefs.h:945
IXM42XXX_FSYNC_CONFIG_UI_SEL_t
IXM42XXX_FSYNC_CONFIG_UI_SEL_t
Definition: Ixm42xxxDefs.h:1106
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_24S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_24S
Definition: Ixm42xxxDefs.h:1614
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_1000dps
@ IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_1000dps
Definition: Ixm42xxxDefs.h:1465
IXM42XXX_OIS2_CONFIG1_DEC_t
IXM42XXX_OIS2_CONFIG1_DEC_t
OIS2 rate selection (base clock fixed by OTP divided by decimator value)
Definition: Ixm42xxxDefs.h:1514
IXM42XXX_SMD_CONFIG_SMD_MODE_WOM
@ IXM42XXX_SMD_CONFIG_SMD_MODE_WOM
Definition: Ixm42xxxDefs.h:1025
IXM42XXX_APEX_DATA3_DMP_IDLE_OFF_t
IXM42XXX_APEX_DATA3_DMP_IDLE_OFF_t
Definition: Ixm42xxxDefs.h:427
BIT_APEX_DATA3_DMP_IDLE_POS
#define BIT_APEX_DATA3_DMP_IDLE_POS
Definition: Ixm42xxxDefs.h:423
IXM42XXX_FIFO_CONFIG1_HIRES_DIS
@ IXM42XXX_FIFO_CONFIG1_HIRES_DIS
Definition: Ixm42xxxDefs.h:1053
BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS
#define BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS
Definition: Ixm42xxxDefs.h:1549
IXM42XXX_FIFO_CONFIG1_HIRES_t
IXM42XXX_FIFO_CONFIG1_HIRES_t
Definition: Ixm42xxxDefs.h:1051
IXM42XXX_GYRO_CONFIG0_ODR_16_KHZ
@ IXM42XXX_GYRO_CONFIG0_ODR_16_KHZ
Definition: Ixm42xxxDefs.h:734
IXM42XXX_TMST_CONFIG_TMST_TO_REGS_EN
@ IXM42XXX_TMST_CONFIG_TMST_TO_REGS_EN
Definition: Ixm42xxxDefs.h:890
BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS
#define BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS
Definition: Ixm42xxxDefs.h:526
IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_RESERVED
@ IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_RESERVED
Definition: Ixm42xxxDefs.h:1882
IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_Y
@ IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_Y
Definition: Ixm42xxxDefs.h:1110
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2348810_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2348810_MG
Definition: Ixm42xxxDefs.h:1673
BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS
#define BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS
Definition: Ixm42xxxDefs.h:930
BIT_DEVICE_CONFIG_SPI_MODE_POS
#define BIT_DEVICE_CONFIG_SPI_MODE_POS
Definition: Ixm42xxxDefs.h:290
BIT_APEX_CONFIG0_DMP_ODR_POS
#define BIT_APEX_CONFIG0_DMP_ODR_POS
Definition: Ixm42xxxDefs.h:980
BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS
#define BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS
Definition: Ixm42xxxDefs.h:801
IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_1ST_ORDER
@ IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_1ST_ORDER
Definition: Ixm42xxxDefs.h:870
IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_136
@ IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_136
Definition: Ixm42xxxDefs.h:1722
IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_4g
@ IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_4g
Definition: Ixm42xxxDefs.h:1576
IXM42XXX_FIFO_CONFIG1_WM_GT_t
IXM42XXX_FIFO_CONFIG1_WM_GT_t
Definition: Ixm42xxxDefs.h:1041
IXM42XXX_INTF_CONFIG4_AP_SPI4W
@ IXM42XXX_INTF_CONFIG4_AP_SPI4W
Definition: Ixm42xxxDefs.h:1311
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t
Definition: Ixm42xxxDefs.h:826
IXM42XXX_APEX_DATA4_TAP_AXIS_Z
@ IXM42XXX_APEX_DATA4_TAP_AXIS_Z
Definition: Ixm42xxxDefs.h:457
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_16S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_16S
Definition: Ixm42xxxDefs.h:1612
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1409286_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1409286_MG
Definition: Ixm42xxxDefs.h:1666
IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_2S
@ IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_2S
Definition: Ixm42xxxDefs.h:1739
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2751463_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2751463_MG
Definition: Ixm42xxxDefs.h:1676
IXM42XXX_GYRO_CONFIG0_ODR_4_KHZ
@ IXM42XXX_GYRO_CONFIG0_ODR_4_KHZ
Definition: Ixm42xxxDefs.h:732
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_200_SAMPLES
@ IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_200_SAMPLES
Definition: Ixm42xxxDefs.h:1709
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_64S
@ IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_64S
Definition: Ixm42xxxDefs.h:1796
BIT_ACCEL_CONFIG0_FS_SEL_POS
#define BIT_ACCEL_CONFIG0_FS_SEL_POS
Definition: Ixm42xxxDefs.h:744
IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_PP
@ IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_PP
Definition: Ixm42xxxDefs.h:357
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1509949MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1509949MG
Definition: Ixm42xxxDefs.h:1636
IXM42XXX_ACCEL_CONFIG0_ODR_1_5625_HZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_1_5625_HZ
Definition: Ixm42xxxDefs.h:775
IXM42XXX_APEX_CONFIG8_TAP_TAVG_8SAMPLE
@ IXM42XXX_APEX_CONFIG8_TAP_TAVG_8SAMPLE
Definition: Ixm42xxxDefs.h:1854
IXM42XXX_GYRO_CONFIG0_FS_SEL_t
IXM42XXX_GYRO_CONFIG0_FS_SEL_t
Gyroscope FSR selection.
Definition: Ixm42xxxDefs.h:694
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t
Definition: Ixm42xxxDefs.h:1632
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_16dps
@ IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_16dps
Definition: Ixm42xxxDefs.h:1459
IXM42XXX_OIS1_CONFIG1_DEC_1
@ IXM42XXX_OIS1_CONFIG1_DEC_1
Definition: Ixm42xxxDefs.h:1418
IXM42XXX_PWR_MGMT_0_IDLE_EN
@ IXM42XXX_PWR_MGMT_0_IDLE_EN
Definition: Ixm42xxxDefs.h:657
IXM42XXX_ACCEL_CONFIG0_ODR_4_KHZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_4_KHZ
Definition: Ixm42xxxDefs.h:785
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_t
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_t
Definition: Ixm42xxxDefs.h:1662
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_16
@ IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_16
Definition: Ixm42xxxDefs.h:829
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_16dps
@ IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_16dps
Definition: Ixm42xxxDefs.h:1556
IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_t
IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_t
Definition: Ixm42xxxDefs.h:1502
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_2000dps
@ IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_2000dps
Definition: Ixm42xxxDefs.h:1466
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_125_SAMPLES
@ IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_125_SAMPLES
Definition: Ixm42xxxDefs.h:1706
IXM42XXX_APEX_CONFIG8_TAP_TMIN_218MS
@ IXM42XXX_APEX_CONFIG8_TAP_TMIN_218MS
Definition: Ixm42xxxDefs.h:1869
IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_16g
@ IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_16g
Definition: Ixm42xxxDefs.h:1578
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_5
@ IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_5
Definition: Ixm42xxxDefs.h:832
IXM42XXX_INT_CONFIG_INT2_POLARITY_t
IXM42XXX_INT_CONFIG_INT2_POLARITY_t
Definition: Ixm42xxxDefs.h:346
IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_t
IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_t
Definition: Ixm42xxxDefs.h:336
IXM42XXX_DEVICE_CONFIG_SPI_MODE_0_3
@ IXM42XXX_DEVICE_CONFIG_SPI_MODE_0_3
Definition: Ixm42xxxDefs.h:298
IXM42XXX_OIS1_CONFIG1_GYRO_EN_t
IXM42XXX_OIS1_CONFIG1_GYRO_EN_t
Definition: Ixm42xxxDefs.h:1431
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1845493MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1845493MG
Definition: Ixm42xxxDefs.h:1638
IXM42XXX_CHIP_CONFIG_RESET_NONE
@ IXM42XXX_CHIP_CONFIG_RESET_NONE
Definition: Ixm42xxxDefs.h:323
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_1
@ IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_1
Definition: Ixm42xxxDefs.h:1774
IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_t
IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_t
Definition: Ixm42xxxDefs.h:1880
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1811939_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1811939_MG
Definition: Ixm42xxxDefs.h:1669
IXM42XXX_SMD_CONFIG_SMD_MODE_LONG
@ IXM42XXX_SMD_CONFIG_SMD_MODE_LONG
Definition: Ixm42xxxDefs.h:1023
IXM42XXX_GYRO_CONFIG0_ODR_25_HZ
@ IXM42XXX_GYRO_CONFIG0_ODR_25_HZ
Definition: Ixm42xxxDefs.h:726
BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS
#define BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS
Definition: Ixm42xxxDefs.h:865
IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_DIS
@ IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_DIS
Definition: Ixm42xxxDefs.h:936
BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS
#define BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS
Definition: Ixm42xxxDefs.h:1452
IXM42XXX_OIS1_CONFIG1_ACCEL_EN
@ IXM42XXX_OIS1_CONFIG1_ACCEL_EN
Definition: Ixm42xxxDefs.h:1442
IXM42XXX_APEX_CONFIG8_TAP_TMIN_234MS
@ IXM42XXX_APEX_CONFIG8_TAP_TMIN_234MS
Definition: Ixm42xxxDefs.h:1870
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_5_12S
@ IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_5_12S
Definition: Ixm42xxxDefs.h:1754
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_2
@ IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_2
Definition: Ixm42xxxDefs.h:856
IXM42XXX_ACCEL_CONFIG0_ODR_8_KHZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_8_KHZ
Definition: Ixm42xxxDefs.h:786
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_8
@ IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_8
Definition: Ixm42xxxDefs.h:831
IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_1ST_ORDER
@ IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_1ST_ORDER
Definition: Ixm42xxxDefs.h:806
BIT_APEX_CONFIG0_R2W_EN_POS
#define BIT_APEX_CONFIG0_R2W_EN_POS
Definition: Ixm42xxxDefs.h:960
IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_PP
@ IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_PP
Definition: Ixm42xxxDefs.h:337
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_3019898_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_3019898_MG
Definition: Ixm42xxxDefs.h:1678
BIT_SPI_MODE_OIS2_POS
#define BIT_SPI_MODE_OIS2_POS
Definition: Ixm42xxxDefs.h:591
IXM42XXX_APEX_CONFIG8_TAP_TMAX_250MS
@ IXM42XXX_APEX_CONFIG8_TAP_TMAX_250MS
Definition: Ixm42xxxDefs.h:1839
IXM42XXX_GYRO_CONFIG0_ODR_32_KHZ
@ IXM42XXX_GYRO_CONFIG0_ODR_32_KHZ
Definition: Ixm42xxxDefs.h:735
IXM42XXX_OIS1_CONFIG1_ACCEL_EN_t
IXM42XXX_OIS1_CONFIG1_ACCEL_EN_t
Definition: Ixm42xxxDefs.h:1441
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_175_SAMPLES
@ IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_175_SAMPLES
Definition: Ixm42xxxDefs.h:1708
IXM42XXX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t
IXM42XXX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t
Definition: Ixm42xxxDefs.h:575
fifo_header_t::accel_odr_different
unsigned char accel_odr_different
Definition: Ixm42xxxDefs.h:247
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2885681_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2885681_MG
Definition: Ixm42xxxDefs.h:1677
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1342177MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1342177MG
Definition: Ixm42xxxDefs.h:1635
IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_Z
@ IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_Z
Definition: Ixm42xxxDefs.h:1111
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1006632MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1006632MG
Definition: Ixm42xxxDefs.h:1633
IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_t
IXM42XXX_GYRO_CONFIG_GYRO_UI_FILT_ORD_t
Definition: Ixm42xxxDefs.h:805
IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_t
IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_t
Definition: Ixm42xxxDefs.h:1405
IXM42XXX_OIS1_CONFIG1_GYRO_EN
@ IXM42XXX_OIS1_CONFIG1_GYRO_EN
Definition: Ixm42xxxDefs.h:1432
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_4S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_4S
Definition: Ixm42xxxDefs.h:1609
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_4
@ IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_4
Definition: Ixm42xxxDefs.h:855
IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_BYTE
@ IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_BYTE
Definition: Ixm42xxxDefs.h:567
BIT_FIFO_CONFIG1_GYRO_POS
#define BIT_FIFO_CONFIG1_GYRO_POS
Definition: Ixm42xxxDefs.h:1077
IXM42XXX_INTF_CONFIG0_DATA_LITTLE_ENDIAN
@ IXM42XXX_INTF_CONFIG0_DATA_LITTLE_ENDIAN
Definition: Ixm42xxxDefs.h:587
IXM42XXX_APEX_DATA4_TAP_NUM_DOUBLE
@ IXM42XXX_APEX_DATA4_TAP_NUM_DOUBLE
Definition: Ixm42xxxDefs.h:448
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_3
@ IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_3
Definition: Ixm42xxxDefs.h:1776
fifo_header_t::Byte
unsigned char Byte
Definition: Ixm42xxxDefs.h:243
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_6_4S
@ IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_6_4S
Definition: Ixm42xxxDefs.h:1755
IXM42XXX_APEX_CONFIG8_TAP_TAVG_t
IXM42XXX_APEX_CONFIG8_TAP_TAVG_t
Definition: Ixm42xxxDefs.h:1850
IXM42XXX_ACCEL_CONFIG0_ODR_1_KHZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_1_KHZ
Definition: Ixm42xxxDefs.h:783
BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS
#define BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS
Definition: Ixm42xxxDefs.h:1498
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_1000dps
@ IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_1000dps
Definition: Ixm42xxxDefs.h:1562
IXM42XXX_APEX_CONFIG0_PEDO_EN_EN
@ IXM42XXX_APEX_CONFIG0_PEDO_EN_EN
Definition: Ixm42xxxDefs.h:955
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_10
@ IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_10
Definition: Ixm42xxxDefs.h:830
BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS
#define BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS
Definition: Ixm42xxxDefs.h:1628
IXM42XXX_APEX_DATA3_DMP_IDLE_OFF
@ IXM42XXX_APEX_DATA3_DMP_IDLE_OFF
Definition: Ixm42xxxDefs.h:429
IXM42XXX_PWR_MGMT_0_GYRO_MODE_LN
@ IXM42XXX_PWR_MGMT_0_GYRO_MODE_LN
Definition: Ixm42xxxDefs.h:666
IXM42XXX_APEX_CONFIG0_DMP_ODR_t
IXM42XXX_APEX_CONFIG0_DMP_ODR_t
DMP ODR selection.
Definition: Ixm42xxxDefs.h:986
IXM42XXX_APEX_CONFIG8_TAP_TAVG_1SAMPLE
@ IXM42XXX_APEX_CONFIG8_TAP_TAVG_1SAMPLE
Definition: Ixm42xxxDefs.h:1851
IXM42XXX_ACCEL_CONFIG0_ODR_50_HZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_50_HZ
Definition: Ixm42xxxDefs.h:780
IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_EN
@ IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_EN
Definition: Ixm42xxxDefs.h:1062
BIT_GYRO_AAF_DIS_POS
#define BIT_GYRO_AAF_DIS_POS
Definition: Ixm42xxxDefs.h:1252
IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_t
IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_t
Definition: Ixm42xxxDefs.h:595
fifo_header_t
Definition: Ixm42xxxDefs.h:242
BIT_FIFO_CONFIG1_WM_GT_TH_POS
#define BIT_FIFO_CONFIG1_WM_GT_TH_POS
Definition: Ixm42xxxDefs.h:1037
IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t
IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t
Definition: Ixm42xxxDefs.h:1821
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_10_24S
@ IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_10_24S
Definition: Ixm42xxxDefs.h:1758
IXM42XXX_GYRO_CONFIG0_ODR_50_HZ
@ IXM42XXX_GYRO_CONFIG0_ODR_50_HZ
Definition: Ixm42xxxDefs.h:727
IXM42XXX_INTF_CONFIG0_DATA_ENDIAN_t
IXM42XXX_INTF_CONFIG0_DATA_ENDIAN_t
Definition: Ixm42xxxDefs.h:585
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1140850_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1140850_MG
Definition: Ixm42xxxDefs.h:1664
IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_8g
@ IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_8g
Definition: Ixm42xxxDefs.h:1480
IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC
@ IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC
Definition: Ixm42xxxDefs.h:1503
BIT_SPI_MODE_OIS1_POS
#define BIT_SPI_MODE_OIS1_POS
Definition: Ixm42xxxDefs.h:601
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_40S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_40S
Definition: Ixm42xxxDefs.h:1618
IXM42XXX_APEX_DATA4_TAP_AXIS_t
IXM42XXX_APEX_DATA4_TAP_AXIS_t
Definition: Ixm42xxxDefs.h:456
IXM42XXX_GYRO_CONFIG0_FS_SEL_125dps
@ IXM42XXX_GYRO_CONFIG0_FS_SEL_125dps
Definition: Ixm42xxxDefs.h:708
IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_t
IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_t
Definition: Ixm42xxxDefs.h:530
BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS
#define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS
Definition: Ixm42xxxDefs.h:536
IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_X
@ IXM42XXX_FSYNC_CONFIG_UI_SEL_GYRO_X
Definition: Ixm42xxxDefs.h:1109
IXM42XXX_ACCEL_CONFIG0_ODR_25_HZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_25_HZ
Definition: Ixm42xxxDefs.h:779
IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_2g
@ IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_2g
Definition: Ixm42xxxDefs.h:1575
BIT_OIS1_CONFIG1_GYRO_EN_POS
#define BIT_OIS1_CONFIG1_GYRO_EN_POS
Definition: Ixm42xxxDefs.h:1427
IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_90
@ IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_90
Definition: Ixm42xxxDefs.h:1720
IXM42XXX_CHIP_CONFIG_RESET_t
IXM42XXX_CHIP_CONFIG_RESET_t
Definition: Ixm42xxxDefs.h:321
IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_DIS
@ IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_DIS
Definition: Ixm42xxxDefs.h:522
IXM42XXX_APEX_CONFIG0_R2W_EN_t
IXM42XXX_APEX_CONFIG0_R2W_EN_t
Definition: Ixm42xxxDefs.h:964
BIT_DATA_ENDIAN_POS
#define BIT_DATA_ENDIAN_POS
Definition: Ixm42xxxDefs.h:581
IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_25
@ IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_25
Definition: Ixm42xxxDefs.h:1823
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_52S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_52S
Definition: Ixm42xxxDefs.h:1621
BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS
#define BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS
Definition: Ixm42xxxDefs.h:1768
IXM42XXX_APEX_DATA4_TAP_AXIS_Y
@ IXM42XXX_APEX_DATA4_TAP_AXIS_Y
Definition: Ixm42xxxDefs.h:458
IXM42XXX_APEX_DATA4_TAP_DIR_NEGATIVE
@ IXM42XXX_APEX_DATA4_TAP_DIR_NEGATIVE
Definition: Ixm42xxxDefs.h:468
IXM42XXX_APEX_DATA4_TAP_DIR_POSITIVE
@ IXM42XXX_APEX_DATA4_TAP_DIR_POSITIVE
Definition: Ixm42xxxDefs.h:467
fifo_header_t::timestamp_bit
unsigned char timestamp_bit
Definition: Ixm42xxxDefs.h:249
BIT_OIS2_CONFIG1_GYRO_EN_POS
#define BIT_OIS2_CONFIG1_GYRO_EN_POS
Definition: Ixm42xxxDefs.h:1524
IXM42XXX_INT_CONFIG_INT1_POLARITY_HIGH
@ IXM42XXX_INT_CONFIG_INT1_POLARITY_HIGH
Definition: Ixm42xxxDefs.h:367
IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t
IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t
Definition: Ixm42xxxDefs.h:555
IXM42XXX_GYRO_NF_DIS_t
IXM42XXX_GYRO_NF_DIS_t
Definition: Ixm42xxxDefs.h:1265
IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_159
@ IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_159
Definition: Ixm42xxxDefs.h:1723
BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS
#define BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS
Definition: Ixm42xxxDefs.h:1733
IXM42XXX_GYRO_CONFIG0_FS_SEL_250dps
@ IXM42XXX_GYRO_CONFIG0_FS_SEL_250dps
Definition: Ixm42xxxDefs.h:709
IXM42XXX_CHIP_CONFIG_SPI_MODE_1_2
@ IXM42XXX_CHIP_CONFIG_SPI_MODE_1_2
Definition: Ixm42xxxDefs.h:303
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_8_96S
@ IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_8_96S
Definition: Ixm42xxxDefs.h:1757
IXM42XXX_OIS2_CONFIG1_GYRO_EN
@ IXM42XXX_OIS2_CONFIG1_GYRO_EN
Definition: Ixm42xxxDefs.h:1529
BIT_PWR_MGMT_0_TEMP_POS
#define BIT_PWR_MGMT_0_TEMP_POS
Definition: Ixm42xxxDefs.h:641
IXM42XXX_PWR_MGMT_0_GYRO_MODE_t
IXM42XXX_PWR_MGMT_0_GYRO_MODE_t
Definition: Ixm42xxxDefs.h:665
IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_4S
@ IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_4S
Definition: Ixm42xxxDefs.h:1740
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_125dps
@ IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_125dps
Definition: Ixm42xxxDefs.h:1462
IXM42XXX_OIS1_CONFIG1_GYRO_DIS
@ IXM42XXX_OIS1_CONFIG1_GYRO_DIS
Definition: Ixm42xxxDefs.h:1433
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2013265MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2013265MG
Definition: Ixm42xxxDefs.h:1639
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t
Definition: Ixm42xxxDefs.h:1702
IXM42XXX_OIS1_CONFIG1_DEC_t
IXM42XXX_OIS1_CONFIG1_DEC_t
OIS1 rate selection (base clock fixed by OTP divided by decimator value)
Definition: Ixm42xxxDefs.h:1417
IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_107
@ IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_107
Definition: Ixm42xxxDefs.h:1721
IXM42XXX_OIS2_CONFIG1_DEC_16
@ IXM42XXX_OIS2_CONFIG1_DEC_16
Definition: Ixm42xxxDefs.h:1519
IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC
@ IXM42XXX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC
Definition: Ixm42xxxDefs.h:1406
IXM42XXX_PWR_MGMT_0_TEMP_DIS
@ IXM42XXX_PWR_MGMT_0_TEMP_DIS
Definition: Ixm42xxxDefs.h:646
IXM42XXX_APEX_CONFIG8_TAP_TAVG_4SAMPLE
@ IXM42XXX_APEX_CONFIG8_TAP_TAVG_4SAMPLE
Definition: Ixm42xxxDefs.h:1853
IXM42XXX_TMST_CONFIG_RESOL_1us
@ IXM42XXX_TMST_CONFIG_RESOL_1us
Definition: Ixm42xxxDefs.h:901
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2080374_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2080374_MG
Definition: Ixm42xxxDefs.h:1671
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_7_68S
@ IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_7_68S
Definition: Ixm42xxxDefs.h:1756
IXM42XXX_INTF_CONFIG1_RTC_MODE_EN
@ IXM42XXX_INTF_CONFIG1_RTC_MODE_EN
Definition: Ixm42xxxDefs.h:632
IXM42XXX_SMD_CONFIG_WOM_MODE_CMP_PREV
@ IXM42XXX_SMD_CONFIG_WOM_MODE_CMP_PREV
Definition: Ixm42xxxDefs.h:1013
IXM42XXX_OIS1_CONFIG1_DEC_8
@ IXM42XXX_OIS1_CONFIG1_DEC_8
Definition: Ixm42xxxDefs.h:1421
IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_6S
@ IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_6S
Definition: Ixm42xxxDefs.h:1741
IXM42XXX_OIS2_CONFIG1_ACCEL_EN
@ IXM42XXX_OIS2_CONFIG1_ACCEL_EN
Definition: Ixm42xxxDefs.h:1539
IXM42XXX_ACCEL_CONFIG0_ODR_6_25_HZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_6_25_HZ
Definition: Ixm42xxxDefs.h:777
IXM42XXX_APEX_CONFIG8_TAP_TMIN_140MS
@ IXM42XXX_APEX_CONFIG8_TAP_TMIN_140MS
Definition: Ixm42xxxDefs.h:1864
IXM42XXX_OIS2_CONFIG1_GYRO_EN_t
IXM42XXX_OIS2_CONFIG1_GYRO_EN_t
Definition: Ixm42xxxDefs.h:1528
IXM42XXX_DEVICE_CONFIG_RESET_EN
@ IXM42XXX_DEVICE_CONFIG_RESET_EN
Definition: Ixm42xxxDefs.h:316
IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_RESERVED
@ IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_RESERVED
Definition: Ixm42xxxDefs.h:1477
IXM42XXX_ACCEL_CONFIG0_ODR_200_HZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_200_HZ
Definition: Ixm42xxxDefs.h:782
IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_EN
@ IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_EN
Definition: Ixm42xxxDefs.h:541
IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_EN
@ IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_EN
Definition: Ixm42xxxDefs.h:557
IXM42XXX_ACCEL_CONFIG0_ODR_3_125_HZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_3_125_HZ
Definition: Ixm42xxxDefs.h:776
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t
Definition: Ixm42xxxDefs.h:1750
BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS
#define BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS
Definition: Ixm42xxxDefs.h:1401
IXM42XXX_FIFO_CONFIG1_GYRO_EN
@ IXM42XXX_FIFO_CONFIG1_GYRO_EN
Definition: Ixm42xxxDefs.h:1082
IXM42XXX_PWR_MGMT_0_TEMP_t
IXM42XXX_PWR_MGMT_0_TEMP_t
Definition: Ixm42xxxDefs.h:645
IXM42XXX_OIS2_CONFIG1_ACCEL_DIS
@ IXM42XXX_OIS2_CONFIG1_ACCEL_DIS
Definition: Ixm42xxxDefs.h:1540
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_2000dps
@ IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_2000dps
Definition: Ixm42xxxDefs.h:1563
IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_t
IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_t
Definition: Ixm42xxxDefs.h:565
IXM42XXX_ACCEL_CONFIG0_FS_SEL_2g
@ IXM42XXX_ACCEL_CONFIG0_FS_SEL_2g
Definition: Ixm42xxxDefs.h:759
IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_DIS
@ IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_DIS
Definition: Ixm42xxxDefs.h:542
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_40
@ IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_40
Definition: Ixm42xxxDefs.h:849
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_48S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_48S
Definition: Ixm42xxxDefs.h:1620
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2483027_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2483027_MG
Definition: Ixm42xxxDefs.h:1674
IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_NORMAL
@ IXM42XXX_APEX_CONFIG9_SENSITIVITY_MODE_NORMAL
Definition: Ixm42xxxDefs.h:1881
IXM42XXX_ACCEL_CONFIG0_ODR_16_KHZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_16_KHZ
Definition: Ixm42xxxDefs.h:787
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_20
@ IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_20
Definition: Ixm42xxxDefs.h:828
IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t
IXM42XXX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t
Definition: Ixm42xxxDefs.h:356
IXM42XXX_OIS1_CONFIG1_DEC_2
@ IXM42XXX_OIS1_CONFIG1_DEC_2
Definition: Ixm42xxxDefs.h:1419
BIT_APEX_CONFIG8_TAP_TAVG_POS
#define BIT_APEX_CONFIG8_TAP_TAVG_POS
Definition: Ixm42xxxDefs.h:1846
IXM42XXX_TMST_CONFIG_TMST_TO_REGS_DIS
@ IXM42XXX_TMST_CONFIG_TMST_TO_REGS_DIS
Definition: Ixm42xxxDefs.h:891
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_6S
@ IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_6S
Definition: Ixm42xxxDefs.h:1799
IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_0_3
@ IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS2_0_3
Definition: Ixm42xxxDefs.h:597
BIT_APEX_DATA4_TAP_NUM_POS
#define BIT_APEX_DATA4_TAP_NUM_POS
Definition: Ixm42xxxDefs.h:444
BIT_FIFO_SREG_INVALID_IND_POS
#define BIT_FIFO_SREG_INVALID_IND_POS
Definition: Ixm42xxxDefs.h:551
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_5
@ IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_5
Definition: Ixm42xxxDefs.h:854
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_75_SAMPLES
@ IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_75_SAMPLES
Definition: Ixm42xxxDefs.h:1704
IXM42XXX_INT_CONFIG_INT1_POLARITY_t
IXM42XXX_INT_CONFIG_INT1_POLARITY_t
Definition: Ixm42xxxDefs.h:366
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_10
@ IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_10
Definition: Ixm42xxxDefs.h:852
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_50_SAMPLES
@ IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_50_SAMPLES
Definition: Ixm42xxxDefs.h:1703
IXM42XXX_INTF_CONFIG4_AP_SPI_t
IXM42XXX_INTF_CONFIG4_AP_SPI_t
Definition: Ixm42xxxDefs.h:1310
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t
Definition: Ixm42xxxDefs.h:1607
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_16
@ IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_16
Definition: Ixm42xxxDefs.h:839
IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_EN
@ IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_EN
Definition: Ixm42xxxDefs.h:531
IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_0_3
@ IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_0_3
Definition: Ixm42xxxDefs.h:607
IXM42XXX_ACCEL_AAF_EN
@ IXM42XXX_ACCEL_AAF_EN
Definition: Ixm42xxxDefs.h:1365
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_62dps
@ IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_62dps
Definition: Ixm42xxxDefs.h:1461
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1275068_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1275068_MG
Definition: Ixm42xxxDefs.h:1665
BIT_GYRO_NF_DIS_POS
#define BIT_GYRO_NF_DIS_POS
Definition: Ixm42xxxDefs.h:1262
IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_DIS
@ IXM42XXX_SIGNAL_PATH_RESET_TMST_STROBE_DIS
Definition: Ixm42xxxDefs.h:532
IXM42XXX_CHIP_CONFIG_SPI_MODE_0_3
@ IXM42XXX_CHIP_CONFIG_SPI_MODE_0_3
Definition: Ixm42xxxDefs.h:304
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3355443MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3355443MG
Definition: Ixm42xxxDefs.h:1647
IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_DIS
@ IXM42XXX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_DIS
Definition: Ixm42xxxDefs.h:556
BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS
#define BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS
Definition: Ixm42xxxDefs.h:1698
IXM42XXX_SMD_CONFIG_WOM_MODE_CMP_INIT
@ IXM42XXX_SMD_CONFIG_WOM_MODE_CMP_INIT
Definition: Ixm42xxxDefs.h:1014
BIT_SMD_CONFIG_WOM_INT_MODE_POS
#define BIT_SMD_CONFIG_WOM_INT_MODE_POS
Definition: Ixm42xxxDefs.h:998
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_3_84S
@ IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_3_84S
Definition: Ixm42xxxDefs.h:1753
IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_4g
@ IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_4g
Definition: Ixm42xxxDefs.h:1479
IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_EN
@ IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_EN
Definition: Ixm42xxxDefs.h:935
IXM42XXX_INTF_CONFIG1_RTC_MODE_DIS
@ IXM42XXX_INTF_CONFIG1_RTC_MODE_DIS
Definition: Ixm42xxxDefs.h:631
fifo_header_t::fsync_bit
unsigned char fsync_bit
Definition: Ixm42xxxDefs.h:248
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t
Definition: Ixm42xxxDefs.h:1772
IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_t
IXM42XXX_APEX_CONFIG0_DMP_POWER_SAVE_t
Definition: Ixm42xxxDefs.h:934
BIT_FIFO_CONFIG1_TEMP_POS
#define BIT_FIFO_CONFIG1_TEMP_POS
Definition: Ixm42xxxDefs.h:1067
IXM42XXX_GYRO_CONFIG0_ODR_t
IXM42XXX_GYRO_CONFIG0_ODR_t
Gyroscope ODR selection.
Definition: Ixm42xxxDefs.h:723
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_6
@ IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_6
Definition: Ixm42xxxDefs.h:1779
IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_t
IXM42XXX_SIGNAL_PATH_RESET_FIFO_FLUSH_t
Definition: Ixm42xxxDefs.h:540
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_24S
@ IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_24S
Definition: Ixm42xxxDefs.h:1801
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2684354MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2684354MG
Definition: Ixm42xxxDefs.h:1643
IXM42XXX_DEVICE_CONFIG_RESET_t
IXM42XXX_DEVICE_CONFIG_RESET_t
Definition: Ixm42xxxDefs.h:315
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_0S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_0S
Definition: Ixm42xxxDefs.h:1608
BIT_FIFO_COUNT_REC_POS
#define BIT_FIFO_COUNT_REC_POS
Definition: Ixm42xxxDefs.h:561
IXM42XXX_CHIP_CONFIG_SPI_MODE_t
IXM42XXX_CHIP_CONFIG_SPI_MODE_t
Definition: Ixm42xxxDefs.h:302
IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_Y
@ IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_Y
Definition: Ixm42xxxDefs.h:1113
IXM42XXX_APEX_CONFIG0_TILT_EN_EN
@ IXM42XXX_APEX_CONFIG0_TILT_EN_EN
Definition: Ixm42xxxDefs.h:975
IXM42XXX_SMD_CONFIG_SMD_MODE_t
IXM42XXX_SMD_CONFIG_SMD_MODE_t
Definition: Ixm42xxxDefs.h:1022
IXM42XXX_GYRO_CONFIG0_FS_SEL_2000dps
@ IXM42XXX_GYRO_CONFIG0_FS_SEL_2000dps
Definition: Ixm42xxxDefs.h:712
BIT_INT_CONFIG1_ASY_RST_POS
#define BIT_INT_CONFIG1_ASY_RST_POS
Definition: Ixm42xxxDefs.h:1123
IXM42XXX_INTF_CONFIG4_AP_SPI3W
@ IXM42XXX_INTF_CONFIG4_AP_SPI3W
Definition: Ixm42xxxDefs.h:1312
IXM42XXX_APEX_CONFIG8_TAP_TMAX_t
IXM42XXX_APEX_CONFIG8_TAP_TMAX_t
Definition: Ixm42xxxDefs.h:1838
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_500dps
@ IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_500dps
Definition: Ixm42xxxDefs.h:1464
IXM42XXX_GYRO_CONFIG0_ODR_2_KHZ
@ IXM42XXX_GYRO_CONFIG0_ODR_2_KHZ
Definition: Ixm42xxxDefs.h:731
BIT_ACCEL_AAF_DIS_POS
#define BIT_ACCEL_AAF_DIS_POS
Definition: Ixm42xxxDefs.h:1360
IXM42XXX_APEX_DATA4_TAP_AXIS_X
@ IXM42XXX_APEX_DATA4_TAP_AXIS_X
Definition: Ixm42xxxDefs.h:459
IXM42XXX_FIFO_CONFIG_MODE_STREAM
@ IXM42XXX_FIFO_CONFIG_MODE_STREAM
Definition: Ixm42xxxDefs.h:383
IXM42XXX_FIFO_CONFIG1_HIRES_EN
@ IXM42XXX_FIFO_CONFIG1_HIRES_EN
Definition: Ixm42xxxDefs.h:1052
IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_X
@ IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_X
Definition: Ixm42xxxDefs.h:1112
IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_RESERVED
@ IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_RESERVED
Definition: Ixm42xxxDefs.h:1574
BIT_APEX_CONFIG8_TAP_TMAX_POS
#define BIT_APEX_CONFIG8_TAP_TMAX_POS
Definition: Ixm42xxxDefs.h:1834
IXM42XXX_APEX_CONFIG0_TILT_EN_DIS
@ IXM42XXX_APEX_CONFIG0_TILT_EN_DIS
Definition: Ixm42xxxDefs.h:976
IXM42XXX_TMST_CONFIG_TMST_EN
@ IXM42XXX_TMST_CONFIG_TMST_EN
Definition: Ixm42xxxDefs.h:920
IXM42XXX_GYRO_NF_DIS
@ IXM42XXX_GYRO_NF_DIS
Definition: Ixm42xxxDefs.h:1267
BIT_RTC_MODE_POS
#define BIT_RTC_MODE_POS
Definition: Ixm42xxxDefs.h:626
IXM42XXX_APEX_CONFIG0_DMP_ODR_50Hz
@ IXM42XXX_APEX_CONFIG0_DMP_ODR_50Hz
Definition: Ixm42xxxDefs.h:988
IXM42XXX_SENSOR_CONFIG2_OIS_MODE_32KHZ
@ IXM42XXX_SENSOR_CONFIG2_OIS_MODE_32KHZ
Definition: Ixm42xxxDefs.h:1240
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2348810MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2348810MG
Definition: Ixm42xxxDefs.h:1641
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_t
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_t
OIS1 gyroscope FSR selection.
Definition: Ixm42xxxDefs.h:1458
BIT_FSYNC_CONFIG_UI_SEL_POS
#define BIT_FSYNC_CONFIG_UI_SEL_POS
Definition: Ixm42xxxDefs.h:1102
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_2_56S
@ IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_2_56S
Definition: Ixm42xxxDefs.h:1752
IXM42XXX_ACCEL_CONFIG0_ODR_t
IXM42XXX_ACCEL_CONFIG0_ODR_t
Accelerometer ODR selection.
Definition: Ixm42xxxDefs.h:773
IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_16g
@ IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_16g
Definition: Ixm42xxxDefs.h:1481
BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS
#define BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS
Definition: Ixm42xxxDefs.h:1567
IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC
@ IXM42XXX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC
Definition: Ixm42xxxDefs.h:1504
IXM42XXX_APEX_CONFIG8_TAP_TMIN_187MS
@ IXM42XXX_APEX_CONFIG8_TAP_TMIN_187MS
Definition: Ixm42xxxDefs.h:1867
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_150_SAMPLES
@ IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_150_SAMPLES
Definition: Ixm42xxxDefs.h:1707
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_92S
@ IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_92S
Definition: Ixm42xxxDefs.h:1800
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1006632_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1006632_MG
Definition: Ixm42xxxDefs.h:1663
BIT_FIFO_COUNT_ENDIAN_POS
#define BIT_FIFO_COUNT_ENDIAN_POS
Definition: Ixm42xxxDefs.h:571
IXM42XXX_GYRO_AAF_DIS_t
IXM42XXX_GYRO_AAF_DIS_t
Definition: Ixm42xxxDefs.h:1256
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_8
@ IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_8
Definition: Ixm42xxxDefs.h:853
IXM42XXX_TMST_CONFIG_TMST_FSYNC_EN
@ IXM42XXX_TMST_CONFIG_TMST_FSYNC_EN
Definition: Ixm42xxxDefs.h:910
BIT_SMD_CONFIG_WOM_MODE_POS
#define BIT_SMD_CONFIG_WOM_MODE_POS
Definition: Ixm42xxxDefs.h:1008
IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_t
IXM42XXX_INTF_CONFIG0_SPI_MODE_OIS1_t
Definition: Ixm42xxxDefs.h:605
IXM42XXX_GYRO_CONFIG0_FS_SEL_31dps
@ IXM42XXX_GYRO_CONFIG0_FS_SEL_31dps
Definition: Ixm42xxxDefs.h:706
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_32S
@ IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_32S
Definition: Ixm42xxxDefs.h:1795
IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_WALK
@ IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_WALK
Definition: Ixm42xxxDefs.h:418
IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_7
@ IXM42XXX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_7
Definition: Ixm42xxxDefs.h:1780
IXM42XXX_ACCEL_CONFIG0_FS_SEL_t
IXM42XXX_ACCEL_CONFIG0_FS_SEL_t
Accelerometer FSR selection.
Definition: Ixm42xxxDefs.h:750
BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS
#define BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS
Definition: Ixm42xxxDefs.h:1470
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_2
@ IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_2
Definition: Ixm42xxxDefs.h:834
IXM42XXX_FIFO_CONFIG1_WM_GT_TH_EN
@ IXM42XXX_FIFO_CONFIG1_WM_GT_TH_EN
Definition: Ixm42xxxDefs.h:1042
IXM42XXX_APEX_CONFIG8_TAP_TMIN_156MS
@ IXM42XXX_APEX_CONFIG8_TAP_TMIN_156MS
Definition: Ixm42xxxDefs.h:1865
IXM42XXX_OIS2_CONFIG1_DEC_32
@ IXM42XXX_OIS2_CONFIG1_DEC_32
Definition: Ixm42xxxDefs.h:1520
IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_EN
@ IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_EN
Definition: Ixm42xxxDefs.h:511
IXM42XXX_OIS2_CONFIG1_DEC_1
@ IXM42XXX_OIS2_CONFIG1_DEC_1
Definition: Ixm42xxxDefs.h:1515
IXM42XXX_INT_CONFIG_INT2_POLARITY_HIGH
@ IXM42XXX_INT_CONFIG_INT2_POLARITY_HIGH
Definition: Ixm42xxxDefs.h:347
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1677721_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1677721_MG
Definition: Ixm42xxxDefs.h:1668
IXM42XXX_ACCEL_AAF_DIS_t
IXM42XXX_ACCEL_AAF_DIS_t
Definition: Ixm42xxxDefs.h:1364
IXM42XXX_APEX_CONFIG0_TAP_ENABLE_t
IXM42XXX_APEX_CONFIG0_TAP_ENABLE_t
Definition: Ixm42xxxDefs.h:944
IXM42XXX_APEX_CONFIG0_TILT_EN_t
IXM42XXX_APEX_CONFIG0_TILT_EN_t
Definition: Ixm42xxxDefs.h:974
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3019898MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3019898MG
Definition: Ixm42xxxDefs.h:1645
IXM42XXX_APEX_DATA3_DMP_IDLE_ON
@ IXM42XXX_APEX_DATA3_DMP_IDLE_ON
Definition: Ixm42xxxDefs.h:428
IXM42XXX_PWR_MGMT_0_GYRO_MODE_OFF
@ IXM42XXX_PWR_MGMT_0_GYRO_MODE_OFF
Definition: Ixm42xxxDefs.h:668
IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_OD
@ IXM42XXX_INT_CONFIG_INT2_DRIVE_CIRCUIT_OD
Definition: Ixm42xxxDefs.h:338
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_8S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_8S
Definition: Ixm42xxxDefs.h:1610
IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_225_SAMPLES
@ IXM42XXX_APEX_CONFIG3_PEDO_SB_TIMER_TH_225_SAMPLES
Definition: Ixm42xxxDefs.h:1710
IXM42XXX_FIFO_CONFIG1_TEMP_EN
@ IXM42XXX_FIFO_CONFIG1_TEMP_EN
Definition: Ixm42xxxDefs.h:1072
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_28S
@ IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_28S
Definition: Ixm42xxxDefs.h:1798
IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_56S
@ IXM42XXX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_56S
Definition: Ixm42xxxDefs.h:1802
IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_DIS
@ IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_DIS
Definition: Ixm42xxxDefs.h:1063
IXM42XXX_APEX_CONFIG0_PEDO_EN_DIS
@ IXM42XXX_APEX_CONFIG0_PEDO_EN_DIS
Definition: Ixm42xxxDefs.h:956
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_44S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_44S
Definition: Ixm42xxxDefs.h:1619
BIT_APEX_CONFIG0_TAP_ENABLE_POS
#define BIT_APEX_CONFIG0_TAP_ENABLE_POS
Definition: Ixm42xxxDefs.h:940
IXM42XXX_ACCEL_CONFIG0_ODR_2_KHZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_2_KHZ
Definition: Ixm42xxxDefs.h:784
IXM42XXX_APEX_CONFIG8_TAP_TMAX_625MS
@ IXM42XXX_APEX_CONFIG8_TAP_TMAX_625MS
Definition: Ixm42xxxDefs.h:1842
IXM42XXX_SMD_CONFIG_WOM_INT_MODE_ORED
@ IXM42XXX_SMD_CONFIG_WOM_INT_MODE_ORED
Definition: Ixm42xxxDefs.h:1004
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2516582MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2516582MG
Definition: Ixm42xxxDefs.h:1642
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2617245_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_2617245_MG
Definition: Ixm42xxxDefs.h:1675
IXM42XXX_PWR_MGMT_0_ACCEL_MODE_t
IXM42XXX_PWR_MGMT_0_ACCEL_MODE_t
Definition: Ixm42xxxDefs.h:676
IXM42XXX_APEX_CONFIG8_TAP_TMIN_125MS
@ IXM42XXX_APEX_CONFIG8_TAP_TMIN_125MS
Definition: Ixm42xxxDefs.h:1863
IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_t
IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_t
Definition: Ixm42xxxDefs.h:1737
BIT_GYRO_CONFIG0_FS_SEL_POS
#define BIT_GYRO_CONFIG0_FS_SEL_POS
Definition: Ixm42xxxDefs.h:688
BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS
#define BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS
Definition: Ixm42xxxDefs.h:1746
IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_2ND_ORDER
@ IXM42XXX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_2ND_ORDER
Definition: Ixm42xxxDefs.h:871
IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_250dps
@ IXM42XXX_OIS1_CONFIG2_GYRO_FS_SEL_250dps
Definition: Ixm42xxxDefs.h:1463
IXM42XXX_FIFO_CONFIG1_ACCEL_EN
@ IXM42XXX_FIFO_CONFIG1_ACCEL_EN
Definition: Ixm42xxxDefs.h:1092
IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_DIS
@ IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_DIS
Definition: Ixm42xxxDefs.h:512
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_4
@ IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_4
Definition: Ixm42xxxDefs.h:833
IXM42XXX_PWR_MGMT_0_IDLE_t
IXM42XXX_PWR_MGMT_0_IDLE_t
Definition: Ixm42xxxDefs.h:655
IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t
IXM42XXX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t
Definition: Ixm42xxxDefs.h:1719
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_32S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_32S
Definition: Ixm42xxxDefs.h:1616
IXM42XXX_SMD_CONFIG_SMD_MODE_SHORT
@ IXM42XXX_SMD_CONFIG_SMD_MODE_SHORT
Definition: Ixm42xxxDefs.h:1024
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_t
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_t
OIS2 gyroscope FSR selection.
Definition: Ixm42xxxDefs.h:1555
IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_0
@ IXM42XXX_APEX_CONFIG4_TILT_WAIT_TIME_0
Definition: Ixm42xxxDefs.h:1738
IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_t
IXM42XXX_SIGNAL_PATH_RESET_DMP_INIT_t
Definition: Ixm42xxxDefs.h:510
IXM42XXX_FSYNC_CONFIG_UI_SEL_NO
@ IXM42XXX_FSYNC_CONFIG_UI_SEL_NO
Definition: Ixm42xxxDefs.h:1107
BIT_CHIP_CONFIG_SPI_MODE_POS
#define BIT_CHIP_CONFIG_SPI_MODE_POS
Definition: Ixm42xxxDefs.h:293
IXM42XXX_INT_CONFIG1_ASY_RST_t
IXM42XXX_INT_CONFIG1_ASY_RST_t
Definition: Ixm42xxxDefs.h:1127
IXM42XXX_OIS2_CONFIG1_ACCEL_EN_t
IXM42XXX_OIS2_CONFIG1_ACCEL_EN_t
Definition: Ixm42xxxDefs.h:1538
IXM42XXX_FIFO_CONFIG_MODE_t
IXM42XXX_FIFO_CONFIG_MODE_t
Definition: Ixm42xxxDefs.h:381
BIT_APEX_CONFIG0_TILT_EN_POS
#define BIT_APEX_CONFIG0_TILT_EN_POS
Definition: Ixm42xxxDefs.h:970
IXM42XXX_TMST_CONFIG_RESOL_t
IXM42XXX_TMST_CONFIG_RESOL_t
Definition: Ixm42xxxDefs.h:899
IXM42XXX_GYRO_CONFIG0_ODR_12_5_HZ
@ IXM42XXX_GYRO_CONFIG0_ODR_12_5_HZ
Definition: Ixm42xxxDefs.h:725
fifo_header_t::accel_bit
unsigned char accel_bit
Definition: Ixm42xxxDefs.h:252
IXM42XXX_SMD_CONFIG_WOM_MODE_t
IXM42XXX_SMD_CONFIG_WOM_MODE_t
Definition: Ixm42xxxDefs.h:1012
IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1543503_MG
@ IXM42XXX_APEX_CONFIG2_PEDO_AMP_TH_1543503_MG
Definition: Ixm42xxxDefs.h:1667
fifo_header_t::gyro_bit
unsigned char gyro_bit
Definition: Ixm42xxxDefs.h:251
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3187671MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3187671MG
Definition: Ixm42xxxDefs.h:1646
IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_t
IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_t
Definition: Ixm42xxxDefs.h:520
IXM42XXX_APEX_CONFIG8_TAP_TMAX_375MS
@ IXM42XXX_APEX_CONFIG8_TAP_TMAX_375MS
Definition: Ixm42xxxDefs.h:1840
IXM42XXX_OIS1_CONFIG1_DEC_32
@ IXM42XXX_OIS1_CONFIG1_DEC_32
Definition: Ixm42xxxDefs.h:1423
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_28S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_28S
Definition: Ixm42xxxDefs.h:1615
IXM42XXX_ACCEL_CONFIG0_ODR_500_HZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_500_HZ
Definition: Ixm42xxxDefs.h:774
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_36S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_36S
Definition: Ixm42xxxDefs.h:1617
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_12S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_12S
Definition: Ixm42xxxDefs.h:1611
BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS
#define BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS
Definition: Ixm42xxxDefs.h:1790
IXM42XXX_OIS1_CONFIG1_ACCEL_DIS
@ IXM42XXX_OIS1_CONFIG1_ACCEL_DIS
Definition: Ixm42xxxDefs.h:1443
IXM42XXX_APEX_CONFIG8_TAP_TMIN_171MS
@ IXM42XXX_APEX_CONFIG8_TAP_TMIN_171MS
Definition: Ixm42xxxDefs.h:1866
IXM42XXX_CHIP_CONFIG_RESET_EN
@ IXM42XXX_CHIP_CONFIG_RESET_EN
Definition: Ixm42xxxDefs.h:322
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_16
@ IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_16
Definition: Ixm42xxxDefs.h:851
BIT_APEX_DATA4_TAP_DIR_POS
#define BIT_APEX_DATA4_TAP_DIR_POS
Definition: Ixm42xxxDefs.h:463
IXM42XXX_APEX_DATA4_TAP_DIR_t
IXM42XXX_APEX_DATA4_TAP_DIR_t
Definition: Ixm42xxxDefs.h:466
IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_1_28S
@ IXM42XXX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_1_28S
Definition: Ixm42xxxDefs.h:1751
IXM42XXX_TMST_CONFIG_TMST_FSYNC_EN_t
IXM42XXX_TMST_CONFIG_TMST_FSYNC_EN_t
Definition: Ixm42xxxDefs.h:909
BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS
#define BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS
Definition: Ixm42xxxDefs.h:822
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_40
@ IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_40
Definition: Ixm42xxxDefs.h:827
IXM42XXX_ACCEL_CONFIG0_FS_SEL_4g
@ IXM42XXX_ACCEL_CONFIG0_FS_SEL_4g
Definition: Ixm42xxxDefs.h:760
IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_t
IXM42XXX_FIFO_CONFIG1_TMST_FSYNC_t
Definition: Ixm42xxxDefs.h:1061
IXM42XXX_APEX_DATA4_TAP_NUM_t
IXM42XXX_APEX_DATA4_TAP_NUM_t
Definition: Ixm42xxxDefs.h:447
IXM42XXX_INTF_CONFIG0_DATA_BIG_ENDIAN
@ IXM42XXX_INTF_CONFIG0_DATA_BIG_ENDIAN
Definition: Ixm42xxxDefs.h:586
IXM42XXX_DEVICE_CONFIG_RESET_NONE
@ IXM42XXX_DEVICE_CONFIG_RESET_NONE
Definition: Ixm42xxxDefs.h:317
IXM42XXX_INT_CONFIG1_ASY_RST_DISABLED
@ IXM42XXX_INT_CONFIG1_ASY_RST_DISABLED
Definition: Ixm42xxxDefs.h:1128
IXM42XXX_FIFO_CONFIG1_GYRO_DIS
@ IXM42XXX_FIFO_CONFIG1_GYRO_DIS
Definition: Ixm42xxxDefs.h:1083
IXM42XXX_ACCEL_CONFIG0_FS_SEL_8g
@ IXM42XXX_ACCEL_CONFIG0_FS_SEL_8g
Definition: Ixm42xxxDefs.h:761
IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN
@ IXM42XXX_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN
Definition: Ixm42xxxDefs.h:521
IXM42XXX_FIFO_CONFIG1_TEMP_DIS
@ IXM42XXX_FIFO_CONFIG1_TEMP_DIS
Definition: Ixm42xxxDefs.h:1073
IXM42XXX_FIFO_CONFIG1_ACCEL_DIS
@ IXM42XXX_FIFO_CONFIG1_ACCEL_DIS
Definition: Ixm42xxxDefs.h:1093
IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_Z
@ IXM42XXX_FSYNC_CONFIG_UI_SEL_ACCEL_Z
Definition: Ixm42xxxDefs.h:1114
IXM42XXX_GYRO_AAF_EN
@ IXM42XXX_GYRO_AAF_EN
Definition: Ixm42xxxDefs.h:1257
BIT_OIS2_CONFIG1_ACCEL_EN_POS
#define BIT_OIS2_CONFIG1_ACCEL_EN_POS
Definition: Ixm42xxxDefs.h:1534
IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_RCOSC
@ IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_RCOSC
Definition: Ixm42xxxDefs.h:622
IXM42XXX_APEX_DATA4_TAP_NUM_SINGLE
@ IXM42XXX_APEX_DATA4_TAP_NUM_SINGLE
Definition: Ixm42xxxDefs.h:449
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t
Definition: Ixm42xxxDefs.h:838
IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_RECORD
@ IXM42XXX_INTF_CONFIG0_FIFO_COUNT_REC_RECORD
Definition: Ixm42xxxDefs.h:566
IXM42XXX_GYRO_CONFIG0_ODR_500_HZ
@ IXM42XXX_GYRO_CONFIG0_ODR_500_HZ
Definition: Ixm42xxxDefs.h:724
IXM42XXX_APEX_CONFIG8_TAP_TMIN_203MS
@ IXM42XXX_APEX_CONFIG8_TAP_TMIN_203MS
Definition: Ixm42xxxDefs.h:1868
BIT_APEX_CONFIG2_PEDO_AMP_TH_POS
#define BIT_APEX_CONFIG2_PEDO_AMP_TH_POS
Definition: Ixm42xxxDefs.h:1658
IXM42XXX_FIFO_CONFIG1_WM_GT_TH_DIS
@ IXM42XXX_FIFO_CONFIG1_WM_GT_TH_DIS
Definition: Ixm42xxxDefs.h:1043
IXM42XXX_ACCEL_CONFIG0_ODR_100_HZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_100_HZ
Definition: Ixm42xxxDefs.h:781
IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_t
IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_t
OIS1 accelerometer FSR selection.
Definition: Ixm42xxxDefs.h:1476
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3523215MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3523215MG
Definition: Ixm42xxxDefs.h:1648
IXM42XXX_PWR_MGMT_0_ACCEL_MODE_LP
@ IXM42XXX_PWR_MGMT_0_ACCEL_MODE_LP
Definition: Ixm42xxxDefs.h:678
BIT_OIS1_CONFIG1_DEC_POS
#define BIT_OIS1_CONFIG1_DEC_POS
Definition: Ixm42xxxDefs.h:1411
IXM42XXX_APEX_CONFIG0_R2W_EN_DIS
@ IXM42XXX_APEX_CONFIG0_R2W_EN_DIS
Definition: Ixm42xxxDefs.h:966
IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_WUOSC
@ IXM42XXX_INTF_CONFIG1_ACCEL_LP_CLK_WUOSC
Definition: Ixm42xxxDefs.h:621
IXM42XXX_INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN
@ IXM42XXX_INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN
Definition: Ixm42xxxDefs.h:577
IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_2g
@ IXM42XXX_OIS1_CONFIG2_ACCEL_FS_SEL_2g
Definition: Ixm42xxxDefs.h:1478
IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_20
@ IXM42XXX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_20
Definition: Ixm42xxxDefs.h:850
IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_37
@ IXM42XXX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_37
Definition: Ixm42xxxDefs.h:1824
IXM42XXX_GYRO_CONFIG0_ODR_100_HZ
@ IXM42XXX_GYRO_CONFIG0_ODR_100_HZ
Definition: Ixm42xxxDefs.h:728
IXM42XXX_FIFO_CONFIG_MODE_STOP_ON_FULL
@ IXM42XXX_FIFO_CONFIG_MODE_STOP_ON_FULL
Definition: Ixm42xxxDefs.h:382
IXM42XXX_OIS1_CONFIG1_DEC_16
@ IXM42XXX_OIS1_CONFIG1_DEC_16
Definition: Ixm42xxxDefs.h:1422
IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_125dps
@ IXM42XXX_OIS2_CONFIG2_GYRO_FS_SEL_125dps
Definition: Ixm42xxxDefs.h:1559
IXM42XXX_INTF_CONFIG1_RTC_MODE_t
IXM42XXX_INTF_CONFIG1_RTC_MODE_t
Definition: Ixm42xxxDefs.h:630
IXM42XXX_INT_CONFIG_INT2_POLARITY_LOW
@ IXM42XXX_INT_CONFIG_INT2_POLARITY_LOW
Definition: Ixm42xxxDefs.h:348
IXM42XXX_APEX_CONFIG0_R2W_EN_EN
@ IXM42XXX_APEX_CONFIG0_R2W_EN_EN
Definition: Ixm42xxxDefs.h:965
IXM42XXX_SENSOR_CONFIG2_OIS_MODE_t
IXM42XXX_SENSOR_CONFIG2_OIS_MODE_t
Definition: Ixm42xxxDefs.h:1239
BIT_PWR_MGMT_0_GYRO_MODE_POS
#define BIT_PWR_MGMT_0_GYRO_MODE_POS
Definition: Ixm42xxxDefs.h:661
IXM42XXX_SMD_CONFIG_SMD_MODE_DISABLED
@ IXM42XXX_SMD_CONFIG_SMD_MODE_DISABLED
Definition: Ixm42xxxDefs.h:1026
IXM42XXX_GYRO_CONFIG0_ODR_8_KHZ
@ IXM42XXX_GYRO_CONFIG0_ODR_8_KHZ
Definition: Ixm42xxxDefs.h:733
IXM42XXX_OIS1_CONFIG1_DEC_4
@ IXM42XXX_OIS1_CONFIG1_DEC_4
Definition: Ixm42xxxDefs.h:1420
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1677721MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1677721MG
Definition: Ixm42xxxDefs.h:1637
BIT_ACCEL_LP_CLK_SEL_POS
#define BIT_ACCEL_LP_CLK_SEL_POS
Definition: Ixm42xxxDefs.h:616
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2852126MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2852126MG
Definition: Ixm42xxxDefs.h:1644
IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2181038MG
@ IXM42XXX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2181038MG
Definition: Ixm42xxxDefs.h:1640
IXM42XXX_PWR_MGMT_0_ACCEL_MODE_OFF
@ IXM42XXX_PWR_MGMT_0_ACCEL_MODE_OFF
Definition: Ixm42xxxDefs.h:679
IXM42XXX_FIFO_CONFIG_MODE_BYPASS
@ IXM42XXX_FIFO_CONFIG_MODE_BYPASS
Definition: Ixm42xxxDefs.h:384
IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_8g
@ IXM42XXX_OIS2_CONFIG2_ACCEL_FS_SEL_8g
Definition: Ixm42xxxDefs.h:1577
IXM42XXX_ACCEL_CONFIG0_FS_SEL_RESERVED
@ IXM42XXX_ACCEL_CONFIG0_FS_SEL_RESERVED
Definition: Ixm42xxxDefs.h:758
IXM42XXX_ACCEL_CONFIG0_ODR_32_KHZ
@ IXM42XXX_ACCEL_CONFIG0_ODR_32_KHZ
Definition: Ixm42xxxDefs.h:788
IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_60S
@ IXM42XXX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_60S
Definition: Ixm42xxxDefs.h:1623
IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_RUN
@ IXM42XXX_APEX_DATA3_ACTIVITY_CLASS_RUN
Definition: Ixm42xxxDefs.h:419
BIT_TMST_CONFIG_TMST_FSYNC_POS
#define BIT_TMST_CONFIG_TMST_FSYNC_POS
Definition: Ixm42xxxDefs.h:905
IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_1
@ IXM42XXX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_1
Definition: Ixm42xxxDefs.h:840
BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS
#define BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS
Definition: Ixm42xxxDefs.h:352