| ICM-4268x-V Driver API 1.0.1 ICM-4268x-V Driver API

Icm426xxDefs.h
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1 /*
2 * ________________________________________________________________________________________________________
3 * Copyright (c) 2017 InvenSense Inc. All rights reserved.
4 *
5 * This software, related documentation and any modifications thereto (collectively “Software”) is subject
6 * to InvenSense and its licensors' intellectual property rights under U.S. and international copyright
7 * and other intellectual property rights laws.
8 *
9 * InvenSense and its licensors retain all intellectual property and proprietary rights in and to the Software
10 * and any use, reproduction, disclosure or distribution of the Software without an express license agreement
11 * from InvenSense is strictly prohibited.
12 *
13 * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, THE SOFTWARE IS
14 * PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
15 * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
16 * EXCEPT AS OTHERWISE PROVIDED IN A LICENSE AGREEMENT BETWEEN THE PARTIES, IN NO EVENT SHALL
17 * INVENSENSE BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY
18 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
19 * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THE SOFTWARE.
21 * ________________________________________________________________________________________________________
22 */
23
24 #ifndef _INV_ICM426XX_DEFS_H_
25 #define _INV_ICM426XX_DEFS_H_
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
35 #include <stdint.h>
36
37 /* List whoami values for all icm426xx variants*/
38 #define ICM40608_WHOAMI 0x39
39 #define ICM42600_WHOAMI 0x40
40 #define ICM42602_WHOAMI 0x41
41 #define ICM42605_WHOAMI 0x42
42 #define ICM42622_WHOAMI 0x46
43 #define ICM42631_WHOAMI 0x5C
44 #define ICM42633_WHOAMI 0x5B
45 #define ICM42686P_WHOAMI 0x44
46 #define ICM42688P_WHOAMI 0x47
47 #define ICM42686V_WHOAMI 0xDA
48 #define ICM42688V_WHOAMI 0xDB
49 #define ICM42608_WHOAMI 0x48
50
51 /* Define whoami value for the targeted product and make sure the target is valid */
52 #if defined(ICM42600)
53 #define ICM_WHOAMI ICM42600_WHOAMI
54 #elif defined(ICM42602)
55 #define ICM_WHOAMI ICM42602_WHOAMI
56 #elif defined(ICM42605)
57 #define ICM_WHOAMI ICM42605_WHOAMI
58 #elif defined(ICM42622)
59 #define ICM_WHOAMI ICM42622_WHOAMI
60 #elif defined(ICM42631)
61 #define ICM_WHOAMI ICM42631_WHOAMI
62 #elif defined(ICM42633)
63 #define ICM_WHOAMI ICM42633_WHOAMI
64 #elif defined(ICM42686V)
65 #define ICM_WHOAMI ICM42686V_WHOAMI
66 #elif defined(ICM42688V)
67 #define ICM_WHOAMI ICM42688V_WHOAMI
68 #elif defined(ICM42686P)
69 #define ICM_WHOAMI ICM42686P_WHOAMI
70 #elif defined(ICM42688P)
71 #define ICM_WHOAMI ICM42688P_WHOAMI
72 #elif defined(ICM42608)
73 #define ICM_WHOAMI ICM42608_WHOAMI
74 #elif defined(ICM40608)
75 #define ICM_WHOAMI ICM40608_WHOAMI
76 #else
77 #error "Please define which ICM variant is targeted. Possible values: " \
78 "ICM42600, " \
79 "ICM42602, " \
80 "ICM42605, " \
81 "ICM42622, " \
82 "ICM42631, " \
83 "ICM42633, " \
84 "ICM42686V, " \
85 "ICM42688V, " \
86 "ICM42686P, " \
87 "ICM42688P, " \
88 "ICM42608, " \
89 "ICM40608"
90 #endif
91
95 #if (defined(ICM42631) || defined(ICM42633))
96 #define ICM_FAMILY_CPLUS
97 #else
98 #define ICM_FAMILY_BPLUS
99 #endif
100
101
102 /* ----------------------------------------------------------------------------
103 * Device Register map
104 *
105 * Next macros defines address for all icm426xx registers as listed by device
106 * datasheet.
107 * Macros name is MPUREG_<REGISTER_NAME> with REGISTER_NAME being the name of
108 * the corresponding register in datasheet.
109 * Note that macro name is MPUREG_<REGISTER_NAME>_Bx with x being the bank
110 * number for registers that are in bank 1 and 2 (suffix is ommitted for
111 * bank0 registers)
112 * ---------------------------------------------------------------------------- */
113
114 /* Bank 0 */
115 #define MPUREG_DEVICE_CONFIG 0x11
116 #define MPUREG_CHIP_CONFIG MPUREG_DEVICE_CONFIG // Retro-compatibility
117 #define MPUREG_DRIVE_CONFIG 0x13
118 #define MPUREG_INT_CONFIG 0x14
119 #define MPUREG_FIFO_CONFIG 0x16
120 #define MPUREG_TEMP_DATA0_UI 0x1D
121 #define MPUREG_ACCEL_DATA_X0_UI 0x1F
122 #define MPUREG_GYRO_DATA_X0_UI 0x25
123 #define MPUREG_TMST_FSYNCH 0x2B
124 #define MPUREG_TMST_FSYNC1 MPUREG_TMST_FSYNCH // Retro-compatibility
125 #define MPUREG_INT_STATUS 0x2D
126 #define MPUREG_FIFO_COUNTH 0x2E
127 #define MPUREG_FIFO_BYTE_COUNT1 MPUREG_FIFO_COUNTH // Retro-compatibility
128 #define MPUREG_FIFO_COUNTL 0x2F
129 #define MPUREG_FIFO_BYTE_COUNT2 MPUREG_FIFO_COUNTL // Retro-compatibility
130 #define MPUREG_FIFO_DATA 0x30
131 #define MPUREG_APEX_DATA0 0x31
132 #define MPUREG_APEX_DATA1 0x32
133 #define MPUREG_APEX_DATA2 0x33
134 #define MPUREG_APEX_DATA3 0x34
135 #define MPUREG_APEX_DATA4 0x35
136 #define MPUREG_APEX_DATA5 0x36
137 #define MPUREG_INT_STATUS2 0x37
138 #define MPUREG_INT_STATUS3 0x38
139 #define MPUREG_SIGNAL_PATH_RESET 0x4B
140 #define MPUREG_INTF_CONFIG0 0x4C
141 #define MPUREG_INTF_CONFIG1 0x4D
142 #define MPUREG_PWR_MGMT_0 0x4E
143 #define MPUREG_GYRO_CONFIG0 0x4F
144 #define MPUREG_ACCEL_CONFIG0 0x50
145 #define MPUREG_GYRO_CONFIG1 0x51
146 #define MPUREG_ACCEL_GYRO_CONFIG0 0x52
147 #define MPUREG_ACCEL_CONFIG1 0x53
148 #define MPUREG_TMST_CONFIG 0x54
149 #define MPUREG_APEX_CONFIG0 0x56
150 #define MPUREG_SMD_CONFIG 0x57
151 #define MPUREG_FIFO_CONFIG1 0x5F
152 #define MPUREG_FIFO_CONFIG2 0x60
153 #define MPUREG_FSYNC_CONFIG 0x62
154 #define MPUREG_INT_CONFIG0 0x63
155 #define MPUREG_INT_CONFIG1 0x64
156 #define MPUREG_INT_SOURCE0 0x65
157 #define MPUREG_INT_SOURCE1 0x66
158 #define MPUREG_INT_SOURCE2 0x67
159 #define MPUREG_INT_SOURCE3 0x68
160 #define MPUREG_INT_SOURCE4 0x69
161 #define MPUREG_INT_SOURCE5 0x6A
162 #define MPUREG_FIFO_LOST_PKT0 0x6C
163 #define MPUREG_SELF_TEST_CONFIG 0x70
164 #define MPUREG_WHO_AM_I 0x75
165 #define MPUREG_SCAN0 0x71
166 #define MPUREG_MEM_BANK_SEL 0x72
167 #define MPUREG_MEM_START_ADDR 0x73
168 #define MPUREG_MEM_R_W 0x74
169 #define MPUREG_REG_BANK_SEL 0x76
170
171 /* Bank 1 */
172 #define MPUREG_SENSOR_CONFIG1_B1 0x04
173 #define MPUREG_GYRO_CONFIG_STATIC2_B1 0x0B
174 #define MPUREG_GYRO_CONFIG_STATIC3_B1 0x0C
175 #define MPUREG_GYRO_CONFIG_STATIC4_B1 0x0D
176 #define MPUREG_GYRO_CONFIG_STATIC5_B1 0x0E
177 #define MPUREG_XG_ST_DATA_B1 0x5F
178 #define MPUREG_YG_ST_DATA_B1 0x60
179 #define MPUREG_ZG_ST_DATA_B1 0x61
180 #define MPUREG_TMST_VAL0_B1 0x62
181 #define MPUREG_INTF_CONFIG4_B1 0x7A
182 #define MPUREG_INTF_CONFIG5_B1 0x7B
183 #define MPUREG_INTF_CONFIG6_B1 0x7C
184 #define MPUREG_INTF_CONFIG3_B1 0x79
185
186 /* Bank 2 */
187 #define MPUREG_ACCEL_CONFIG_STATIC2_B2 0x03
188 #define MPUREG_ACCEL_CONFIG_STATIC3_B2 0x04
189 #define MPUREG_ACCEL_CONFIG_STATIC4_B2 0x05
190 #define MPUREG_ACCEL_CONFIG_STATIC0_B2 0x39
191 #define MPUREG_XA_ST_DATA_B2 0x3B
192 #define MPUREG_YA_ST_DATA_B2 0x3C
193 #define MPUREG_ZA_ST_DATA_B2 0x3D
194 /* Only accessible from AUX1 */
195 #define MPUREG_OIS1_CONFIG1_B2 0x44
196 #define MPUREG_OIS1_CONFIG2_B2 0x45
197 #define MPUREG_OIS1_CONFIG3_B2 0x46
198 #define MPUREG_ACCEL_DATA_X0_OIS1_B2 0x49
199 #define MPUREG_GYRO_DATA_X0_OIS1_B2 0x4F
200 #define MPUREG_INT_STATUS_OIS1_B2 0x57
201 /* End of Only accessible from AUX1 */
202 /* Only accessible from AUX2 */
203 #define MPUREG_OIS2_CONFIG1_B2 0x59
204 #define MPUREG_OIS2_CONFIG2_B2 0x5A
205 #define MPUREG_OIS2_CONFIG3_B2 0x5B
206 #define MPUREG_ACCEL_DATA_X0_OIS2_B2 0x5E
207 #define MPUREG_GYRO_DATA_X0_OIS2_B2 0x64
208 #define MPUREG_INT_STATUS_OIS2_B2 0x6C
209 /* End of Only accessible from AUX2 */
210 #define MPUREG_TMD4_B2 0x70
211 #define MPUREG_TMD5_B2 0x71
212 #define MPUREG_TMD6_B2 0x72
213 #define MPUREG_TMD7_B2 0x73
214
215 /* Bank 3 */
216 #define MPUREG_PU_PD_CONFIG1_B3 0x06
217 #define MPUREG_PU_PD_CONFIG2_B3 0x0E
218
219 /* Bank 4 */
220 #define MPUREG_FDR_CONFIG_B4 0x09
221 #define MPUREG_APEX_CONFIG1_B4 0x40
222 #define MPUREG_APEX_CONFIG2_B4 0x41
223 #define MPUREG_APEX_CONFIG3_B4 0x42
224 #define MPUREG_APEX_CONFIG4_B4 0x43
225 #define MPUREG_APEX_CONFIG5_B4 0x44
226 #define MPUREG_APEX_CONFIG6_B4 0x45
227 #define MPUREG_APEX_CONFIG7_B4 0x46
228 #define MPUREG_APEX_CONFIG8_B4 0x47
229 #define MPUREG_APEX_CONFIG9_B4 0x48
230 #define MPUREG_APEX_CONFIG10_B4 0x49
231 #define MPUREG_ACCEL_WOM_X_THR_B4 0x4A
232 #define MPUREG_ACCEL_WOM_Y_THR_B4 0x4B
233 #define MPUREG_ACCEL_WOM_Z_THR_B4 0x4C
234 #define MPUREG_INT_SOURCE6_B4 0x4D
235 #define MPUREG_INT_SOURCE7_B4 0x4E
236 #define MPUREG_INT_SOURCE8_B4 0x4F
237 #define MPUREG_INT_SOURCE9_B4 0x50
238 #define MPUREG_INT_SOURCE10_B4 0x51
239 #define MPUREG_OFFSET_USER_0_B4 0x77
240 #define MPUREG_OFFSET_USER_1_B4 0x78
241 #define MPUREG_OFFSET_USER_2_B4 0x79
242 #define MPUREG_OFFSET_USER_3_B4 0x7A
243 #define MPUREG_OFFSET_USER_4_B4 0x7B
244 #define MPUREG_OFFSET_USER_5_B4 0x7C
245 #define MPUREG_OFFSET_USER_6_B4 0x7D
246 #define MPUREG_OFFSET_USER_7_B4 0x7E
247 #define MPUREG_OFFSET_USER_8_B4 0x7F
248
249 /* ----------------------------------------------------------------------------
250 * Device features
251 *
252 * Next macros define some of the device features such as FIFO, sensor data
253 * size or whoami value.
254 * ---------------------------------------------------------------------------- */
255
256 #define ACCEL_DATA_SIZE 6
257 #define GYRO_DATA_SIZE 6
258 #define TEMP_DATA_SIZE 2
259
260 #define FIFO_HEADER_SIZE 1
261 #define FIFO_ACCEL_DATA_SIZE ACCEL_DATA_SIZE
262 #define FIFO_GYRO_DATA_SIZE GYRO_DATA_SIZE
263 #define FIFO_TEMP_DATA_SIZE 1
264 #define FIFO_TS_FSYNC_SIZE 2
265 #define FIFO_TEMP_HIGH_RES_SIZE 1
266 #define FIFO_ACCEL_GYRO_HIGH_RES_SIZE 3
267
268 #define FIFO_16BYTES_PACKET_SIZE (FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + FIFO_TS_FSYNC_SIZE)
269 #define FIFO_20BYTES_PACKET_SIZE (FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + FIFO_TS_FSYNC_SIZE +\
270 FIFO_TEMP_HIGH_RES_SIZE + FIFO_ACCEL_GYRO_HIGH_RES_SIZE)
271
272 #define FIFO_HEADER_ODR_ACCEL 0x01
273 #define FIFO_HEADER_ODR_GYRO 0x02
274 #define FIFO_HEADER_FSYNC 0x04
275 #define FIFO_HEADER_TMST 0x08
276 #define FIFO_HEADER_HEADER_20 0x10
277 #define FIFO_HEADER_GYRO 0x20
278 #define FIFO_HEADER_ACC 0x40
279 #define FIFO_HEADER_MSG 0x80
280
281
282 #define INVALID_VALUE_FIFO ((int16_t)0x8000)
283 #define INVALID_VALUE_FIFO_1B ((int8_t)0x80)
284
286 typedef union
287 {
288 unsigned char Byte;
289 struct
290 {
291 unsigned char gyro_odr_different : 1;
292 unsigned char accel_odr_different : 1;
293 unsigned char fsync_bit : 1;
294 unsigned char timestamp_bit : 1;
295 unsigned char twentybits_bit : 1;
296 unsigned char gyro_bit : 1;
297 unsigned char accel_bit : 1;
298 unsigned char msg_bit : 1;
299 }bits;
300 } fifo_header_t;
301
302 #define I3C_IBI_PAYLOAD_ALL 0xFF
303 #define I3C_IBI_PAYLOAD_TIMEC 0x80
304 #define I3C_IBI_PAYLOAD_CAT_MISC 0x40
305 #define I3C_IBI_PAYLOAD_CAT_ERROR 0x20
306 #define I3C_IBI_PAYLOAD_CAT_APEX2 0x10
307 #define I3C_IBI_PAYLOAD_CAT_APEX1 0x08
308 #define I3C_IBI_PAYLOAD_CAT_OIS1_DRDY 0x04
309 #define I3C_IBI_PAYLOAD_CAT_FIFO 0x02
310 #define I3C_IBI_PAYLOAD_CAT_UI_DRDY 0x01
311
312
313 /* ----------------------------------------------------------------------------
314 * Device registers description
315 *
316 * Next section defines some of the registers bitfield and declare corresponding
317 * accessors.
318 * Note that descriptors and accessors are not provided for all the registers
319 * but only for the most useful ones.
320 * For all details on registers and bitfields functionalities please refer to
321 * the device datasheet.
322 * ---------------------------------------------------------------------------- */
323
324
325 /* ---------------------------------------------------------------------------
326 * register bank 0
327 * ---------------------------------------------------------------------------- */
328
329 /*
330 * MPUREG_DEVICE_CONFIG
331 * Register Name : DEVICE_CONFIG
332 */
333
334 /* SPI_MODE */
335 #define BIT_DEVICE_CONFIG_SPI_MODE_POS 4
336 #define BIT_DEVICE_CONFIG_SPI_MODE_MASK (0x1 << BIT_DEVICE_CONFIG_SPI_MODE_POS)
337 #define BIT_CHIP_CONFIG_SPI_MODE_MASK BIT_DEVICE_CONFIG_SPI_MODE_MASK //retro-compatibility
338 #define BIT_CHIP_CONFIG_SPI_MODE_POS BIT_DEVICE_CONFIG_SPI_MODE_POS //retro-compatibility
339
340 typedef enum
341 {
342 ICM426XX_DEVICE_CONFIG_SPI_MODE_1_2 = (0x1 << BIT_DEVICE_CONFIG_SPI_MODE_POS),
343 ICM426XX_DEVICE_CONFIG_SPI_MODE_0_3 = (0x0 << BIT_DEVICE_CONFIG_SPI_MODE_POS),
344 } ICM426XX_DEVICE_CONFIG_SPI_MODE_t;
345
346 typedef enum
347 {
348 ICM426XX_CHIP_CONFIG_SPI_MODE_1_2 = (0x1 << BIT_CHIP_CONFIG_SPI_MODE_POS),
349 ICM426XX_CHIP_CONFIG_SPI_MODE_0_3 = (0x0 << BIT_CHIP_CONFIG_SPI_MODE_POS),
350 } ICM426XX_CHIP_CONFIG_SPI_MODE_t; //retro-compatibility
351
352
353 /* SOFT_RESET */
354 #define BIT_DEVICE_CONFIG_RESET_POS 0
355 #define BIT_DEVICE_CONFIG_RESET_MASK 0x01
356 #define BIT_CHIP_CONFIG_RESET_MASK BIT_DEVICE_CONFIG_RESET_MASK //retro-compatibility
357 #define BIT_CHIP_CONFIG_RESET_POS BIT_DEVICE_CONFIG_RESET_POS //retro-compatibility
358
359 typedef enum
360 {
361 ICM426XX_DEVICE_CONFIG_RESET_EN = 0x01,
362 ICM426XX_DEVICE_CONFIG_RESET_NONE = 0x00,
363 } ICM426XX_DEVICE_CONFIG_RESET_t;
364
365 typedef enum
366 {
367 ICM426XX_CHIP_CONFIG_RESET_EN = 0x01,
368 ICM426XX_CHIP_CONFIG_RESET_NONE = 0x00,
369 } ICM426XX_CHIP_CONFIG_RESET_t; //retro-compatibility
370
371 /*
372 * MPUREG_INT_CONFIG
373 * Register Name: INT_CONFIG
374 */
375
376 /* INT2_DRIVE_CIRCUIT */
377 #define BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS 4
378 #define BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS)
379
380 typedef enum
381 {
382 ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_PP = (0x01 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS),
383 ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_OD = (0x00 << BIT_INT_CONFIG_INT2_DRIVE_CIRCUIT_POS),
384 } ICM426XX_INT_CONFIG_INT2_DRIVE_CIRCUIT_t;
385
386 /* INT2_POLARITY */
387 #define BIT_INT_CONFIG_INT2_POLARITY_POS 3
388 #define BIT_INT_CONFIG_INT2_POLARITY_MASK (0x01 << BIT_INT_CONFIG_INT2_POLARITY_POS)
389
390 typedef enum
391 {
392 ICM426XX_INT_CONFIG_INT2_POLARITY_HIGH = (0x01 << BIT_INT_CONFIG_INT2_POLARITY_POS),
393 ICM426XX_INT_CONFIG_INT2_POLARITY_LOW = (0x00 << BIT_INT_CONFIG_INT2_POLARITY_POS),
394 } ICM426XX_INT_CONFIG_INT2_POLARITY_t;
395
396 /* INT1_DRIVE_CIRCUIT */
397 #define BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS 1
398 #define BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_MASK (0x01 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS)
399
400 typedef enum
401 {
402 ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_PP = (0x01 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS),
403 ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_OD = (0x00 << BIT_INT_CONFIG_INT1_DRIVE_CIRCUIT_POS),
404 } ICM426XX_INT_CONFIG_INT1_DRIVE_CIRCUIT_t;
405
406 /* INT1_POLARITY */
407 #define BIT_INT_CONFIG_INT1_POLARITY_POS 0
408 #define BIT_INT_CONFIG_INT1_POLARITY_MASK 0x01
409
410 typedef enum
411 {
412 ICM426XX_INT_CONFIG_INT1_POLARITY_HIGH = 0x01,
413 ICM426XX_INT_CONFIG_INT1_POLARITY_LOW = 0x00,
414 } ICM426XX_INT_CONFIG_INT1_POLARITY_t;
415
416 /*
417 * MPUREG_FIFO_CONFIG
418 * Register Name: FIFO_CONFIG
419 */
420
421 /* FIFO_MODE */
422 #define BIT_FIFO_CONFIG_MODE_POS 6
423 #define BIT_FIFO_CONFIG_MODE_MASK (0x03 << BIT_FIFO_CONFIG_MODE_POS)
424
425 typedef enum
426 {
427 ICM426XX_FIFO_CONFIG_MODE_STOP_ON_FULL = (0x02 << BIT_FIFO_CONFIG_MODE_POS),
428 ICM426XX_FIFO_CONFIG_MODE_STREAM = (0x01 << BIT_FIFO_CONFIG_MODE_POS),
429 ICM426XX_FIFO_CONFIG_MODE_BYPASS = (0x00 << BIT_FIFO_CONFIG_MODE_POS),
430 } ICM426XX_FIFO_CONFIG_MODE_t;
431
432 #define ICM426XX_FIFO_CONFIG_MODE_SNAPSHOT = ICM426XX_FIFO_CONFIG_MODE_STOP_ON_FULL; // For retro-compatibility
433 /*
434 * MPUREG_INT_STATUS
435 * Register Name: INT_STATUS
436 */
437 #define BIT_INT_STATUS_UI_FSYNC 0x40
438 #define BIT_INT_STATUS_PLL_RDY 0x20
439 #define BIT_INT_STATUS_RESET_DONE 0x10
440 #define BIT_INT_STATUS_DRDY 0x08
441 #define BIT_INT_STATUS_FIFO_THS 0x04
442 #define BIT_INT_STATUS_FIFO_FULL 0x02
443 #define BIT_INT_STATUS_AGC_RDY 0x01
444
445 /*
446 * MPUREG_APEX_DATA0
447 * MPUREG_APEX_DATA1
448 * MPUREG_APEX_DATA2
449 * MPUREG_APEX_DATA3
450 * Register Name: APEX_DATA0
451 * Register Name: APEX_DATA1
452 * Register Name: APEX_DATA2
453 * Register Name: APEX_DATA3
454 */
455
456 /* ACTIVITY_CLASS */
457 #define BIT_APEX_DATA3_ACTIVITY_CLASS_POS 0
458 #define BIT_APEX_DATA3_ACTIVITY_CLASS_MASK 0x03
459
460 typedef enum
461 {
462 ICM426XX_APEX_DATA3_ACTIVITY_CLASS_OTHER = 0x0,
463 ICM426XX_APEX_DATA3_ACTIVITY_CLASS_WALK = 0x1,
464 ICM426XX_APEX_DATA3_ACTIVITY_CLASS_RUN = 0x2,
465 } ICM426XX_APEX_DATA3_ACTIVITY_CLASS_t;
466
467 /* DMP_IDLE */
468 #define BIT_APEX_DATA3_DMP_IDLE_POS 2
469 #define BIT_APEX_DATA3_DMP_IDLE_MASK (0x01 << BIT_APEX_DATA3_DMP_IDLE_POS)
470
471 typedef enum
472 {
473 ICM426XX_APEX_DATA3_DMP_IDLE_ON = (0x01 << BIT_APEX_DATA3_DMP_IDLE_POS),
474 ICM426XX_APEX_DATA3_DMP_IDLE_OFF = (0x00 << BIT_APEX_DATA3_DMP_IDLE_POS),
475 } ICM426XX_APEX_DATA3_DMP_IDLE_OFF_t;
476
477 /*
478 * MPUREG_APEX_DATA4
479 * Register Name: APEX_DATA4
480 */
481
488 /* TAP_NUM */
489 #define BIT_APEX_DATA4_TAP_NUM_POS 3
490 #define BIT_APEX_DATA4_TAP_NUM_MASK (0x03 << BIT_APEX_DATA4_TAP_NUM_POS)
491 typedef enum
492 {
493 ICM426XX_APEX_DATA4_TAP_NUM_DOUBLE = (0x02 << BIT_APEX_DATA4_TAP_NUM_POS),
494 ICM426XX_APEX_DATA4_TAP_NUM_SINGLE = (0x01 << BIT_APEX_DATA4_TAP_NUM_POS),
495 } ICM426XX_APEX_DATA4_TAP_NUM_t;
496
497 /* TAP_AXIS */
498 #define BIT_APEX_DATA4_TAP_AXIS_POS 1
499 #define BIT_APEX_DATA4_TAP_AXIS_MASK (0x03 << BIT_APEX_DATA4_TAP_AXIS_POS)
500 typedef enum
501 {
502 ICM426XX_APEX_DATA4_TAP_AXIS_Z = (0x02 << BIT_APEX_DATA4_TAP_AXIS_POS),
503 ICM426XX_APEX_DATA4_TAP_AXIS_Y = (0x01 << BIT_APEX_DATA4_TAP_AXIS_POS),
504 ICM426XX_APEX_DATA4_TAP_AXIS_X = (0x00 << BIT_APEX_DATA4_TAP_AXIS_POS),
505 } ICM426XX_APEX_DATA4_TAP_AXIS_t;
506
507 /* TAP_DIR */
508 #define BIT_APEX_DATA4_TAP_DIR_POS 0
509 #define BIT_APEX_DATA4_TAP_DIR_MASK 0x01
510 typedef enum
511 {
512 ICM426XX_APEX_DATA4_TAP_DIR_POSITIVE = (0x01 << BIT_APEX_DATA4_TAP_DIR_POS),
513 ICM426XX_APEX_DATA4_TAP_DIR_NEGATIVE = (0x00 << BIT_APEX_DATA4_TAP_DIR_POS),
514 } ICM426XX_APEX_DATA4_TAP_DIR_t;
515
516 /*
517 * MPUREG_APEX_DATA5
518 * Register Name: APEX_DATA5
519 */
520
521 /* DOUBLE_TAP_TIMING */
522 #define BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS 0
523 #define BIT_APEX_DATA5_DOUBLE_TAP_TIMING_MASK (0x3F << BIT_APEX_DATA5_DOUBLE_TAP_TIMING_POS)
524
525 /*
526 * MPUREG_INT_STATUS2
527 * Register Name: INT_STATUS2
528 */
529 #define BIT_INT_STATUS2_SMD_INT 0x08
530 #define BIT_INT_STATUS2_WOM_Z_INT 0x04
531 #define BIT_INT_STATUS2_WOM_Y_INT 0x02
532 #define BIT_INT_STATUS2_WOM_X_INT 0x01
533
534 /*
535 * MPUREG_INT_STATUS3
536 * Register Name: INT_STATUS3
537 */
538 #define BIT_INT_STATUS3_STEP_DET 0x20
539 #define BIT_INT_STATUS3_STEP_CNT_OVFL 0x10
540 #define BIT_INT_STATUS3_TILT_DET 0x08
541 #if defined(ICM_FAMILY_BPLUS)
542 #define BIT_INT_STATUS3_WAKE_DET 0x04
543 #define BIT_INT_STATUS3_SLEEP_DET 0x02
544 #elif defined(ICM_FAMILY_CPLUS)
545 #define BIT_INT_STATUS3_LOWG_DET 0x04
546 #define BIT_INT_STATUS3_FF_DET 0x02
547 #endif
548 #define BIT_INT_STATUS3_TAP_DET 0x01
549
550 /*
551 * MPUREG_SIGNAL_PATH_RESET
552 * Register Name: SIGNAL_PATH_RESET
553 */
554
555 /* DMP_INIT_EN */
556 #define BIT_SIGNAL_PATH_RESET_DMP_INIT_POS 6
557 #define BIT_SIGNAL_PATH_RESET_DMP_INIT_MASK (0x01 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS)
558
559 typedef enum
560 {
561 ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_EN = (0x01 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS),
562 ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_DMP_INIT_POS),
563 } ICM426XX_SIGNAL_PATH_RESET_DMP_INIT_t;
564
565 /* DMP_MEM_RESET_EN */
566 #define BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS 5
567 #define BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_MASK (0x01 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS)
568
569 typedef enum
570 {
571 ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN = (0x01 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS),
572 ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_POS),
573 } ICM426XX_SIGNAL_PATH_RESET_DMP_MEM_RESET_t;
574
575 /* TMST_STROBE */
576 #define BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS 2
577 #define BIT_SIGNAL_PATH_RESET_TMST_STROBE_MASK (0x01 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS)
578
579 typedef enum
580 {
581 ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_EN = (0x01 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS),
582 ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_TMST_STROBE_POS),
583 } ICM426XX_SIGNAL_PATH_RESET_TMST_STROBE_t;
584
585 /* FIFO_FLUSH */
586 #define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS 1
587 #define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_MASK (0x01 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS)
588
589 typedef enum
590 {
591 ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_EN = (0x01 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS),
592 ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_DIS = (0x00 << BIT_SIGNAL_PATH_RESET_FIFO_FLUSH_POS),
593 } ICM426XX_SIGNAL_PATH_RESET_FIFO_FLUSH_t;
594
595 /*
596 * MPUREG_INTF_CONFIG0
597 * Register Name: INTF_CONFIG0
598 */
599
600 /* FIFO_SREG_INVALID_IND */
601 #define BIT_FIFO_SREG_INVALID_IND_POS 7
602 #define BIT_FIFO_SREG_INVALID_IND_MASK (0x01 << BIT_FIFO_SREG_INVALID_IND_POS)
603
604 typedef enum
605 {
606 ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_DIS = (0x01 << BIT_FIFO_SREG_INVALID_IND_POS),
607 ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_EN = (0x00 << BIT_FIFO_SREG_INVALID_IND_POS),
608 } ICM426XX_INTF_CONFIG0_FIFO_SREG_INVALID_IND_t;
609
610 /* FIFO_COUNT_REC */
611 #define BIT_FIFO_COUNT_REC_POS 6
612 #define BIT_FIFO_COUNT_REC_MASK (0x01 << BIT_FIFO_COUNT_REC_POS)
613
614 typedef enum
615 {
616 ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_RECORD = (0x01 << BIT_FIFO_COUNT_REC_POS),
617 ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_BYTE = (0x00 << BIT_FIFO_COUNT_REC_POS),
618 } ICM426XX_INTF_CONFIG0_FIFO_COUNT_REC_t;
619
620 /* FIFO_COUNT_ENDIAN */
621 #define BIT_FIFO_COUNT_ENDIAN_POS 5
622 #define BIT_FIFO_COUNT_ENDIAN_MASK (0x01 << BIT_FIFO_COUNT_ENDIAN_POS)
623
624 typedef enum
625 {
626 ICM426XX_INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN = (0x01 << BIT_FIFO_COUNT_ENDIAN_POS),
627 ICM426XX_INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN = (0x00 << BIT_FIFO_COUNT_ENDIAN_POS),
628 } ICM426XX_INTF_CONFIG0_FIFO_COUNT_ENDIAN_t;
629
630 /* DATA_ENDIAN */
631 #define BIT_DATA_ENDIAN_POS 4
632 #define BIT_DATA_ENDIAN_MASK (0x01 << BIT_DATA_ENDIAN_POS)
633
634 typedef enum
635 {
636 ICM426XX_INTF_CONFIG0_DATA_BIG_ENDIAN = (0x01 << BIT_DATA_ENDIAN_POS),
637 ICM426XX_INTF_CONFIG0_DATA_LITTLE_ENDIAN = (0x00 << BIT_DATA_ENDIAN_POS),
638 } ICM426XX_INTF_CONFIG0_DATA_ENDIAN_t;
639
640 /* SPI_MODE_OIS2 */
641 #define BIT_SPI_MODE_OIS2_POS 3
642 #define BIT_SPI_MODE_OIS2_MASK (0x01 << BIT_SPI_MODE_OIS2_POS)
643
644 typedef enum
645 {
646 ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_1_2 = (0x01 << BIT_SPI_MODE_OIS2_POS),
647 ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_0_3 = (0x00 << BIT_SPI_MODE_OIS2_POS),
648 } ICM426XX_INTF_CONFIG0_SPI_MODE_OIS2_t;
649
650 /* SPI_MODE_AUX1 */
651 #define BIT_SPI_MODE_OIS1_POS 2
652 #define BIT_SPI_MODE_OIS1_MASK (0x01 << BIT_SPI_MODE_OIS1_POS)
653
654 typedef enum
655 {
656 ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_1_2 = (0x01 << BIT_SPI_MODE_OIS1_POS),
657 ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_0_3 = (0x00 << BIT_SPI_MODE_OIS1_POS),
658 } ICM426XX_INTF_CONFIG0_SPI_MODE_OIS1_t;
659
660 /*
661 * MPUREG_INTF_CONFIG1
662 * Register Name: INTF_CONFIG1
663 */
664
665 /* ACCEL_LP_CLK_SEL */
666 #define BIT_ACCEL_LP_CLK_SEL_POS 3
667 #define BIT_ACCEL_LP_CLK_SEL_MASK (0x01 << BIT_ACCEL_LP_CLK_SEL_POS)
668
669 typedef enum
670 {
671 ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_WUOSC = (0x00 << BIT_ACCEL_LP_CLK_SEL_POS),
672 ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_RCOSC = (0x01 << BIT_ACCEL_LP_CLK_SEL_POS),
673 } ICM426XX_INTF_CONFIG1_ACCEL_LP_CLK_t;
674
675 /* RTC_MODE */
676 #define BIT_RTC_MODE_POS 2
677 #define BIT_RTC_MODE_MASK (0x01 << BIT_RTC_MODE_POS)
678
679 typedef enum
680 {
681 ICM426XX_INTF_CONFIG1_RTC_MODE_DIS = (0x00 << BIT_RTC_MODE_POS),
682 ICM426XX_INTF_CONFIG1_RTC_MODE_EN = (0x01 << BIT_RTC_MODE_POS),
683 } ICM426XX_INTF_CONFIG1_RTC_MODE_t;
684
685 /*
686 * MPUREG_PWR_MGMT_0
687 * Register Name: PWR_MGMT_0
688 */
689
690 /* TEMP_DIS */
691 #define BIT_PWR_MGMT_0_TEMP_POS 5
692 #define BIT_PWR_MGMT_0_TEMP_MASK (0x01 << BIT_PWR_MGMT_0_TEMP_POS)
693
694 typedef enum
695 {
696 ICM426XX_PWR_MGMT_0_TEMP_DIS = (0x01 << BIT_PWR_MGMT_0_TEMP_POS),
697 ICM426XX_PWR_MGMT_0_TEMP_EN = (0x00 << BIT_PWR_MGMT_0_TEMP_POS),
698 } ICM426XX_PWR_MGMT_0_TEMP_t;
699
700 /* IDLE */
701 #define BIT_PWR_MGMT_0_IDLE_POS 4
702 #define BIT_PWR_MGMT_0_IDLE_MASK (0x01 << BIT_PWR_MGMT_0_IDLE_POS)
703
704 typedef enum
705 {
706 ICM426XX_PWR_MGMT_0_IDLE_DIS = (0x01 << BIT_PWR_MGMT_0_IDLE_POS),
707 ICM426XX_PWR_MGMT_0_IDLE_EN = (0x00 << BIT_PWR_MGMT_0_IDLE_POS),
708 } ICM426XX_PWR_MGMT_0_IDLE_t;
709
710 /* GYRO_MODE */
711 #define BIT_PWR_MGMT_0_GYRO_MODE_POS 2
712 #define BIT_PWR_MGMT_0_GYRO_MODE_MASK (0x03 << BIT_PWR_MGMT_0_GYRO_MODE_POS)
713
714 typedef enum
715 {
716 ICM426XX_PWR_MGMT_0_GYRO_MODE_LN = (0x03 << BIT_PWR_MGMT_0_GYRO_MODE_POS),
717 ICM426XX_PWR_MGMT_0_GYRO_MODE_STANDBY = (0x01 << BIT_PWR_MGMT_0_GYRO_MODE_POS),
718 ICM426XX_PWR_MGMT_0_GYRO_MODE_OFF = (0x00 << BIT_PWR_MGMT_0_GYRO_MODE_POS),
719 } ICM426XX_PWR_MGMT_0_GYRO_MODE_t;
720
721 /* ACCEL_MODE */
722 #define BIT_PWR_MGMT_0_ACCEL_MODE_POS 0
723 #define BIT_PWR_MGMT_0_ACCEL_MODE_MASK 0x03
724
725 typedef enum
726 {
727 ICM426XX_PWR_MGMT_0_ACCEL_MODE_LN = 0x03,
728 ICM426XX_PWR_MGMT_0_ACCEL_MODE_LP = 0x02,
729 ICM426XX_PWR_MGMT_0_ACCEL_MODE_OFF = 0x00,
730 } ICM426XX_PWR_MGMT_0_ACCEL_MODE_t;
731
732 /*
733 * MPUREG_GYRO_CONFIG0
734 * Register Name: GYRO_CONFIG0
735 */
736
737 /* GYRO_FS_SEL*/
738 #define BIT_GYRO_CONFIG0_FS_SEL_POS 5
739 #define BIT_GYRO_CONFIG0_FS_SEL_MASK (7 << BIT_GYRO_CONFIG0_FS_SEL_POS)
740
743 typedef enum
744 {
745 #if defined(ICM42686P) || defined(ICM42686V)
746 ICM426XX_GYRO_CONFIG0_FS_SEL_31dps = (7 << BIT_GYRO_CONFIG0_FS_SEL_POS),
747 ICM426XX_GYRO_CONFIG0_FS_SEL_62dps = (6 << BIT_GYRO_CONFIG0_FS_SEL_POS),
748 ICM426XX_GYRO_CONFIG0_FS_SEL_125dps = (5 << BIT_GYRO_CONFIG0_FS_SEL_POS),
749 ICM426XX_GYRO_CONFIG0_FS_SEL_250dps = (4 << BIT_GYRO_CONFIG0_FS_SEL_POS),
750 ICM426XX_GYRO_CONFIG0_FS_SEL_500dps = (3 << BIT_GYRO_CONFIG0_FS_SEL_POS),
751 ICM426XX_GYRO_CONFIG0_FS_SEL_1000dps = (2 << BIT_GYRO_CONFIG0_FS_SEL_POS),
752 ICM426XX_GYRO_CONFIG0_FS_SEL_2000dps = (1 << BIT_GYRO_CONFIG0_FS_SEL_POS),
753 ICM426XX_GYRO_CONFIG0_FS_SEL_4000dps = (0 << BIT_GYRO_CONFIG0_FS_SEL_POS),
754 #else
755 ICM426XX_GYRO_CONFIG0_FS_SEL_16dps = (7 << BIT_GYRO_CONFIG0_FS_SEL_POS),
756 ICM426XX_GYRO_CONFIG0_FS_SEL_31dps = (6 << BIT_GYRO_CONFIG0_FS_SEL_POS),
757 ICM426XX_GYRO_CONFIG0_FS_SEL_62dps = (5 << BIT_GYRO_CONFIG0_FS_SEL_POS),
758 ICM426XX_GYRO_CONFIG0_FS_SEL_125dps = (4 << BIT_GYRO_CONFIG0_FS_SEL_POS),
759 ICM426XX_GYRO_CONFIG0_FS_SEL_250dps = (3 << BIT_GYRO_CONFIG0_FS_SEL_POS),
760 ICM426XX_GYRO_CONFIG0_FS_SEL_500dps = (2 << BIT_GYRO_CONFIG0_FS_SEL_POS),
761 ICM426XX_GYRO_CONFIG0_FS_SEL_1000dps = (1 << BIT_GYRO_CONFIG0_FS_SEL_POS),
762 ICM426XX_GYRO_CONFIG0_FS_SEL_2000dps = (0 << BIT_GYRO_CONFIG0_FS_SEL_POS),
763 #endif
764 } ICM426XX_GYRO_CONFIG0_FS_SEL_t;
765
766 /* GYRO_ODR */
767 #define BIT_GYRO_CONFIG0_ODR_POS 0
768 #define BIT_GYRO_CONFIG0_ODR_MASK 0x0F
769
772 typedef enum
773 {
774 ICM426XX_GYRO_CONFIG0_ODR_500_HZ = 0x0F,
775 ICM426XX_GYRO_CONFIG0_ODR_12_5_HZ = 0x0B,
776 ICM426XX_GYRO_CONFIG0_ODR_25_HZ = 0x0A,
777 ICM426XX_GYRO_CONFIG0_ODR_50_HZ = 0x09,
778 ICM426XX_GYRO_CONFIG0_ODR_100_HZ = 0x08,
779 ICM426XX_GYRO_CONFIG0_ODR_200_HZ = 0x07,
780 ICM426XX_GYRO_CONFIG0_ODR_1_KHZ = 0x06,
781 ICM426XX_GYRO_CONFIG0_ODR_2_KHZ = 0x05,
782 ICM426XX_GYRO_CONFIG0_ODR_4_KHZ = 0x04,
783 ICM426XX_GYRO_CONFIG0_ODR_8_KHZ = 0x03,
784 ICM426XX_GYRO_CONFIG0_ODR_16_KHZ = 0x02,
785 ICM426XX_GYRO_CONFIG0_ODR_32_KHZ = 0x01,
786 } ICM426XX_GYRO_CONFIG0_ODR_t;
787
788 /*
789 * MPUREG_ACCEL_CONFIG0
790 * Register Name: ACCEL_CONFIG0
791 */
792
793 /* ACCEL_FS_SEL */
794 #define BIT_ACCEL_CONFIG0_FS_SEL_POS 5
795 #define BIT_ACCEL_CONFIG0_FS_SEL_MASK (0x7 << BIT_ACCEL_CONFIG0_FS_SEL_POS)
796
799 typedef enum
800 {
801 #if defined(ICM42686P) || defined(ICM42686V)
802 ICM426XX_ACCEL_CONFIG0_FS_SEL_2g = (0x4 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
803 ICM426XX_ACCEL_CONFIG0_FS_SEL_4g = (0x3 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
804 ICM426XX_ACCEL_CONFIG0_FS_SEL_8g = (0x2 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
805 ICM426XX_ACCEL_CONFIG0_FS_SEL_16g = (0x1 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
806 ICM426XX_ACCEL_CONFIG0_FS_SEL_32g = (0x0 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
807 #else
808 ICM426XX_ACCEL_CONFIG0_FS_SEL_RESERVED = (0x4 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
809 ICM426XX_ACCEL_CONFIG0_FS_SEL_2g = (0x3 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
810 ICM426XX_ACCEL_CONFIG0_FS_SEL_4g = (0x2 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
811 ICM426XX_ACCEL_CONFIG0_FS_SEL_8g = (0x1 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
812 ICM426XX_ACCEL_CONFIG0_FS_SEL_16g = (0x0 << BIT_ACCEL_CONFIG0_FS_SEL_POS),
813 #endif
814 } ICM426XX_ACCEL_CONFIG0_FS_SEL_t;
815
816 /* ACCEL_ODR */
817 #define BIT_ACCEL_CONFIG0_ODR_POS 0
818 #define BIT_ACCEL_CONFIG0_ODR_MASK 0x0F
819
822 typedef enum
823 {
824 ICM426XX_ACCEL_CONFIG0_ODR_500_HZ = 0xF,
825 ICM426XX_ACCEL_CONFIG0_ODR_1_5625_HZ = 0xE,
826 ICM426XX_ACCEL_CONFIG0_ODR_3_125_HZ = 0xD,
827 ICM426XX_ACCEL_CONFIG0_ODR_6_25_HZ = 0xC,
828 ICM426XX_ACCEL_CONFIG0_ODR_12_5_HZ = 0xB,
829 ICM426XX_ACCEL_CONFIG0_ODR_25_HZ = 0xA,
830 ICM426XX_ACCEL_CONFIG0_ODR_50_HZ = 0x9,
831 ICM426XX_ACCEL_CONFIG0_ODR_100_HZ = 0x8,
832 ICM426XX_ACCEL_CONFIG0_ODR_200_HZ = 0x7,
833 ICM426XX_ACCEL_CONFIG0_ODR_1_KHZ = 0x6,
834 ICM426XX_ACCEL_CONFIG0_ODR_2_KHZ = 0x5,
835 ICM426XX_ACCEL_CONFIG0_ODR_4_KHZ = 0x4,
836 ICM426XX_ACCEL_CONFIG0_ODR_8_KHZ = 0x3,
837 ICM426XX_ACCEL_CONFIG0_ODR_16_KHZ = 0x2,
838 ICM426XX_ACCEL_CONFIG0_ODR_32_KHZ = 0x1,
839 } ICM426XX_ACCEL_CONFIG0_ODR_t;
840
841 /*
842 * MPUREG_GYRO_CONFIG1
843 * Register Name: GYRO_CONFIG1
844 */
845
846 /* TEMP_FILT_BW */
847 #define BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS 5
848 #define BIT_GYRO_CONFIG1_TEMP_FILT_BW_MASK (0x7 << BIT_GYRO_CONFIG1_TEMP_FILT_BW_POS)
849
850 /* GYRO_UI_FILT_ORD */
851 #define BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS 2
852 #define BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_MASK (0x3 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS)
853
854 typedef enum
855 {
856 ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_1ST_ORDER = (0x0 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS),
857 ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_2ND_ORDER = (0x1 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS),
858 ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_3RD_ORDER = (0x2 << BIT_GYRO_CONFIG1_GYRO_UI_FILT_ORD_POS),
859 } ICM426XX_GYRO_CONFIG_GYRO_UI_FILT_ORD_t;
860
861 /* GYRO_DEC2_M2_ORD */
862 #define BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_POS 0
863 #define BIT_GYRO_CONFIG1_GYRO_DEC2_M2_ORD_MASK 0x3
864
865
866 /*
867 * MPUREG_ACCEL_GYRO_CONFIG0
868 * Register Name: GYRO_ACCEL_CONFIG0
869 */
870
871 /* ACCEL_UI_FILT_BW_IND */
872 #define BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS 4
873 #define BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_MASK (0xF << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS)
874
875 typedef enum
876 {
877 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_40 = (0x7 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
878 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_20 = (0x6 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
879 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_16 = (0x5 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
880 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_10 = (0x4 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
881 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_8 = (0x3 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
882 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_5 = (0x2 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
883 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_4 = (0x1 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
884 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_2 = (0x0 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
885 } ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_BW_t;
886
887 typedef enum
888 {
889 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_16 = (0x6 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
890 ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_1 = (0x1 << BIT_GYRO_ACCEL_CONFIG0_ACCEL_FILT_POS),
891 } ICM426XX_GYRO_ACCEL_CONFIG0_ACCEL_FILT_AVG_t;
892
893 /* GYRO_UI_FILT_BW_IND */
894 #define BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_POS 0
895 #define BIT_GYRO_ACCEL_CONFIG0_GYRO_FILT_MASK 0x0F
896
897 typedef enum
898 {
899 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_40 = 0x07,
900 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_20 = 0x06,
901 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_16 = 0x05,
902 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_10 = 0x04,
903 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_8 = 0x03,
904 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_5 = 0x02,
905 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_4 = 0x01,
906 ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_2 = 0x00,
907 } ICM426XX_GYRO_ACCEL_CONFIG0_GYRO_FILT_BW_t;
908
909 /*
910 * MPUREG_ACCEL_CONFIG1
911 * Register Name: ACCEL_CONFIG1
912 */
913
914 /* ACCEL_UI_FILT_ORD */
915 #define BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS 3
916 #define BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS)
917
918 typedef enum
919 {
920 ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_1ST_ORDER = (0x0 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS),
921 ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_2ND_ORDER = (0x1 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS),
922 ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_3RD_ORDER = (0x2 << BIT_ACCEL_CONFIG1_ACCEL_UI_FILT_ORD_POS),
923 } ICM426XX_ACCEL_CONFIG_ACCEL_UI_FILT_ORD_t;
924
925 /* ACCEL_DEC2_M2_ORD */
926 #define BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS 1
927 #define BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_MASK (0x3 << BIT_ACCEL_CONFIG1_ACCEL_DEC2_M2_ORD_POS)
928
929 /*
930 * MPUREG_TMST_CONFIG
931 * Register Name: TMST_CONFIG
932 */
933
934 /* TMST_TO_REGS */
935 #define BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS 4
936 #define BIT_TMST_CONFIG_TMST_TO_REGS_EN_MASK (0x1 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS)
937
938 typedef enum
939 {
940 ICM426XX_TMST_CONFIG_TMST_TO_REGS_EN = (0x1 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS),
941 ICM426XX_TMST_CONFIG_TMST_TO_REGS_DIS = (0x0 << BIT_TMST_CONFIG_TMST_TO_REGS_EN_POS),
942 } ICM426XX_TMST_CONFIG_TMST_TO_REGS_EN_t;
943
944 /* TMST_RES */
945 #define BIT_TMST_CONFIG_RESOL_POS 3
946 #define BIT_TMST_CONFIG_RESOL_MASK (0x1 << BIT_TMST_CONFIG_RESOL_POS)
947
948 typedef enum
949 {
950 ICM426XX_TMST_CONFIG_RESOL_16us = (0x01 << BIT_TMST_CONFIG_RESOL_POS),
951 ICM426XX_TMST_CONFIG_RESOL_1us = (0x00 << BIT_TMST_CONFIG_RESOL_POS),
952 } ICM426XX_TMST_CONFIG_RESOL_t;
953
954 /* TMST_FSYNC */
955 #define BIT_TMST_CONFIG_TMST_FSYNC_POS 1
956 #define BIT_TMST_CONFIG_TMST_FSYNC_MASK (0x1 << BIT_TMST_CONFIG_TMST_FSYNC_POS)
957
958 typedef enum
959 {
960 ICM426XX_TMST_CONFIG_TMST_FSYNC_EN = (0x01 << BIT_TMST_CONFIG_TMST_FSYNC_POS),
961 ICM426XX_TMST_CONFIG_TMST_FSYNC_DIS = (0x00 << BIT_TMST_CONFIG_TMST_FSYNC_POS),
962 } ICM426XX_TMST_CONFIG_TMST_FSYNC_EN_t;
963
964 /* TMST_EN */
965 #define BIT_TMST_CONFIG_TMST_EN_POS 0
966 #define BIT_TMST_CONFIG_TMST_EN_MASK 0x1
967
968 typedef enum
969 {
970 ICM426XX_TMST_CONFIG_TMST_EN = 0x01,
971 ICM426XX_TMST_CONFIG_TMST_DIS = 0x00,
972 } ICM426XX_TMST_CONFIG_TMST_EN_t;
973
974 /*
975 * MPUREG_APEX_CONFIG0
976 * Register Name: APEX_CONFIG0
977 */
978
979 /* DMP_POWER_SAVE_EN */
980 #define BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS 7
981 #define BIT_APEX_CONFIG0_DMP_POWER_SAVE_MASK (0x1 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS)
982
983 typedef enum
984 {
985 ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_EN = (0x1 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS),
986 ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_DIS = (0x0 << BIT_APEX_CONFIG0_DMP_POWER_SAVE_POS),
987 } ICM426XX_APEX_CONFIG0_DMP_POWER_SAVE_t;
988
989 /* TAP_ENABLE */
990 #define BIT_APEX_CONFIG0_TAP_ENABLE_POS 6
991 #define BIT_APEX_CONFIG0_TAP_ENABLE_MASK (0x1 << BIT_APEX_CONFIG0_TAP_ENABLE_POS)
992
993 typedef enum
994 {
995 ICM426XX_APEX_CONFIG0_TAP_ENABLE_EN = (0x1 << BIT_APEX_CONFIG0_TAP_ENABLE_POS),
996 ICM426XX_APEX_CONFIG0_TAP_ENABLE_DIS = (0x0 << BIT_APEX_CONFIG0_TAP_ENABLE_POS),
997 } ICM426XX_APEX_CONFIG0_TAP_ENABLE_t;
998
999 /* PEDO_EN */
1000 #define BIT_APEX_CONFIG0_PEDO_EN_POS 5
1001 #define BIT_APEX_CONFIG0_PEDO_EN_MASK (0x1 << BIT_APEX_CONFIG0_PEDO_EN_POS)
1002
1003 typedef enum
1004 {
1005 ICM426XX_APEX_CONFIG0_PEDO_EN_EN = (0x1 << BIT_APEX_CONFIG0_PEDO_EN_POS),
1006 ICM426XX_APEX_CONFIG0_PEDO_EN_DIS = (0x0 << BIT_APEX_CONFIG0_PEDO_EN_POS),
1007 } ICM426XX_APEX_CONFIG0_PEDO_EN_t;
1008
1009 #if defined(ICM_FAMILY_BPLUS)
1010
1011 /* R2W_EN */
1012 #define BIT_APEX_CONFIG0_R2W_EN_POS 3
1013 #define BIT_APEX_CONFIG0_R2W_EN_MASK (0x1 << BIT_APEX_CONFIG0_R2W_EN_POS)
1014
1015 typedef enum
1016 {
1017 ICM426XX_APEX_CONFIG0_R2W_EN_EN = (0x1 << BIT_APEX_CONFIG0_R2W_EN_POS),
1018 ICM426XX_APEX_CONFIG0_R2W_EN_DIS = (0x0 << BIT_APEX_CONFIG0_R2W_EN_POS),
1019 } ICM426XX_APEX_CONFIG0_R2W_EN_t;
1020
1021 #elif defined(ICM_FAMILY_CPLUS)
1022
1023 /* FF_EN */
1024 #define BIT_APEX_CONFIG0_FF_EN_POS 2
1025 #define BIT_APEX_CONFIG0_FF_EN_MASK (0x1 << BIT_APEX_CONFIG0_FF_EN_POS)
1026
1027 typedef enum
1028 {
1029 ICM426XX_APEX_CONFIG0_FF_EN_EN = (0x1 << BIT_APEX_CONFIG0_FF_EN_POS),
1030 ICM426XX_APEX_CONFIG0_FF_EN_DIS = (0x0 << BIT_APEX_CONFIG0_FF_EN_POS),
1031 } ICM426XX_APEX_CONFIG0_FF_EN_t;
1032
1033 /* LOWG_EN */
1034 #define BIT_APEX_CONFIG0_LOWG_EN_POS 3
1035 #define BIT_APEX_CONFIG0_LOWG_EN_MASK (0x1 << BIT_APEX_CONFIG0_LOWG_EN_POS)
1036
1037 typedef enum
1038 {
1039 ICM426XX_APEX_CONFIG0_LOWG_EN_EN = (0x1 << BIT_APEX_CONFIG0_LOWG_EN_POS),
1040 ICM426XX_APEX_CONFIG0_LOWG_EN_DIS = (0x0 << BIT_APEX_CONFIG0_LOWG_EN_POS),
1041 } ICM426XX_APEX_CONFIG0_LOWG_EN_t;
1042
1043 #endif
1044
1045 /* TILT_EN */
1046 #define BIT_APEX_CONFIG0_TILT_EN_POS 4
1047 #define BIT_APEX_CONFIG0_TILT_EN_MASK (0x1 << BIT_APEX_CONFIG0_TILT_EN_POS)
1048
1049 typedef enum
1050 {
1051 ICM426XX_APEX_CONFIG0_TILT_EN_EN = (0x1 << BIT_APEX_CONFIG0_TILT_EN_POS),
1052 ICM426XX_APEX_CONFIG0_TILT_EN_DIS = (0x0 << BIT_APEX_CONFIG0_TILT_EN_POS),
1053 } ICM426XX_APEX_CONFIG0_TILT_EN_t;
1054
1055 /* DMP_ODR */
1056 #define BIT_APEX_CONFIG0_DMP_ODR_POS 0
1057 #define BIT_APEX_CONFIG0_DMP_ODR_MASK (0x3 << BIT_APEX_CONFIG0_DMP_ODR_POS)
1058
1061 typedef enum
1062 {
1063 ICM426XX_APEX_CONFIG0_DMP_ODR_25Hz = (0x0 << BIT_APEX_CONFIG0_DMP_ODR_POS),
1064 ICM426XX_APEX_CONFIG0_DMP_ODR_50Hz = (0x2 << BIT_APEX_CONFIG0_DMP_ODR_POS),
1065 ICM426XX_APEX_CONFIG0_DMP_ODR_100Hz = (0x3 << BIT_APEX_CONFIG0_DMP_ODR_POS),
1066 ICM426XX_APEX_CONFIG0_DMP_ODR_500Hz = (0x1 << BIT_APEX_CONFIG0_DMP_ODR_POS),
1067 } ICM426XX_APEX_CONFIG0_DMP_ODR_t;
1068
1069 /*
1070 * MPUREG_SMD_CONFIG
1071 * Register Name: SMD_CONFIG
1072 */
1073
1074 /* WOM_INT_MODE */
1075 #define BIT_SMD_CONFIG_WOM_INT_MODE_POS 3
1076 #define BIT_SMD_CONFIG_WOM_INT_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_INT_MODE_POS)
1077
1078 typedef enum
1079 {
1080 ICM426XX_SMD_CONFIG_WOM_INT_MODE_ANDED = (0x01 << BIT_SMD_CONFIG_WOM_INT_MODE_POS),
1081 ICM426XX_SMD_CONFIG_WOM_INT_MODE_ORED = (0x00 << BIT_SMD_CONFIG_WOM_INT_MODE_POS),
1082 } ICM426XX_SMD_CONFIG_WOM_INT_MODE_t;
1083
1084 /* WOM_MODE */
1085 #define BIT_SMD_CONFIG_WOM_MODE_POS 2
1086 #define BIT_SMD_CONFIG_WOM_MODE_MASK (0x1 << BIT_SMD_CONFIG_WOM_MODE_POS)
1087
1088 typedef enum
1089 {
1090 ICM426XX_SMD_CONFIG_WOM_MODE_CMP_PREV = (0x01 << BIT_SMD_CONFIG_WOM_MODE_POS),
1091 ICM426XX_SMD_CONFIG_WOM_MODE_CMP_INIT = (0x00 << BIT_SMD_CONFIG_WOM_MODE_POS),
1092 } ICM426XX_SMD_CONFIG_WOM_MODE_t;
1093
1094 /* SMD_MODE */
1095 #define BIT_SMD_CONFIG_SMD_MODE_POS 0
1096 #define BIT_SMD_CONFIG_SMD_MODE_MASK 0x3
1097
1098 typedef enum
1099 {
1100 ICM426XX_SMD_CONFIG_SMD_MODE_LONG = 0x03,
1101 ICM426XX_SMD_CONFIG_SMD_MODE_SHORT = 0x02,
1102 ICM426XX_SMD_CONFIG_SMD_MODE_WOM = 0x01,
1103 ICM426XX_SMD_CONFIG_SMD_MODE_DISABLED = 0x00,
1104 } ICM426XX_SMD_CONFIG_SMD_MODE_t;
1105
1106 /*
1107 * MPUREG_FIFO_CONFIG1
1108 * Register Name: FIFO_CONFIG1
1109 */
1110 #define BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS 6
1111 #define BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_MASK (0x1 << BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD_POS)
1112
1113 /* FIFO_WM_GT_TH */
1114 #define BIT_FIFO_CONFIG1_WM_GT_TH_POS 5
1115 #define BIT_FIFO_CONFIG1_WM_GT_TH_MASK (0x1 << BIT_FIFO_CONFIG1_WM_GT_TH_POS)
1116
1117 typedef enum
1118 {
1119 ICM426XX_FIFO_CONFIG1_WM_GT_TH_EN = (0x1 << BIT_FIFO_CONFIG1_WM_GT_TH_POS),
1120 ICM426XX_FIFO_CONFIG1_WM_GT_TH_DIS = (0x0 << BIT_FIFO_CONFIG1_WM_GT_TH_POS),
1121 } ICM426XX_FIFO_CONFIG1_WM_GT_t;
1122
1123 /* FIFO_HIRES_EN */
1124 #define BIT_FIFO_CONFIG1_HIRES_POS 4
1125 #define BIT_FIFO_CONFIG1_HIRES_MASK (0x1 << BIT_FIFO_CONFIG1_HIRES_POS)
1126
1127 typedef enum
1128 {
1129 ICM426XX_FIFO_CONFIG1_HIRES_EN = (0x1 << BIT_FIFO_CONFIG1_HIRES_POS),
1130 ICM426XX_FIFO_CONFIG1_HIRES_DIS = (0x0 << BIT_FIFO_CONFIG1_HIRES_POS),
1131 } ICM426XX_FIFO_CONFIG1_HIRES_t;
1132
1133 /* FIFO_TMST_FSYNC_EN */
1134 #define BIT_FIFO_CONFIG1_TMST_FSYNC_POS 3
1135 #define BIT_FIFO_CONFIG1_TMST_FSYNC_MASK (0x1 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS)
1136
1137 typedef enum
1138 {
1139 ICM426XX_FIFO_CONFIG1_TMST_FSYNC_EN = (0x1 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS),
1140 ICM426XX_FIFO_CONFIG1_TMST_FSYNC_DIS = (0x0 << BIT_FIFO_CONFIG1_TMST_FSYNC_POS),
1141 } ICM426XX_FIFO_CONFIG1_TMST_FSYNC_t;
1142
1143 /* FIFO_TEMP_EN */
1144 #define BIT_FIFO_CONFIG1_TEMP_POS 2
1145 #define BIT_FIFO_CONFIG1_TEMP_MASK (0x1 << BIT_FIFO_CONFIG1_TEMP_POS)
1146
1147 typedef enum
1148 {
1149 ICM426XX_FIFO_CONFIG1_TEMP_EN = (0x1 << BIT_FIFO_CONFIG1_TEMP_POS),
1150 ICM426XX_FIFO_CONFIG1_TEMP_DIS = (0x0 << BIT_FIFO_CONFIG1_TEMP_POS),
1151 } ICM426XX_FIFO_CONFIG1_TEMP_t;
1152
1153 /* FIFO_GYRO_EN */
1154 #define BIT_FIFO_CONFIG1_GYRO_POS 1
1155 #define BIT_FIFO_CONFIG1_GYRO_MASK (0x1 << BIT_FIFO_CONFIG1_GYRO_POS)
1156
1157 typedef enum
1158 {
1159 ICM426XX_FIFO_CONFIG1_GYRO_EN = (0x1 << BIT_FIFO_CONFIG1_GYRO_POS),
1160 ICM426XX_FIFO_CONFIG1_GYRO_DIS = (0x0 << BIT_FIFO_CONFIG1_GYRO_POS),
1161 } ICM426XX_FIFO_CONFIG1_GYRO_t;
1162
1163 /* FIFO_ACCEL_EN*/
1164 #define BIT_FIFO_CONFIG1_ACCEL_POS 0
1165 #define BIT_FIFO_CONFIG1_ACCEL_MASK 0x1
1166
1167 typedef enum
1168 {
1169 ICM426XX_FIFO_CONFIG1_ACCEL_EN = 0x01,
1170 ICM426XX_FIFO_CONFIG1_ACCEL_DIS = 0x00,
1171 } ICM426XX_FIFO_CONFIG1_ACCEL_t;
1172
1173 /*
1174 * MPUREG_FSYNC_CONFIG
1175 * Register Name: FSYNC_CONFIG
1176 */
1177
1178 /* FSYNC_UI_SEL */
1179 #define BIT_FSYNC_CONFIG_UI_SEL_POS 4
1180 #define BIT_FSYNC_CONFIG_UI_SEL_MASK (0x7 << BIT_FSYNC_CONFIG_UI_SEL_POS)
1181
1182 typedef enum
1183 {
1184 ICM426XX_FSYNC_CONFIG_UI_SEL_NO = (0x0 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1185 ICM426XX_FSYNC_CONFIG_UI_SEL_TEMP = (0x1 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1186 ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_X = (0x2 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1187 ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_Y = (0x3 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1188 ICM426XX_FSYNC_CONFIG_UI_SEL_GYRO_Z = (0x4 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1189 ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_X = (0x5 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1190 ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_Y = (0x6 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1191 ICM426XX_FSYNC_CONFIG_UI_SEL_ACCEL_Z = (0x7 << BIT_FSYNC_CONFIG_UI_SEL_POS),
1192 } ICM426XX_FSYNC_CONFIG_UI_SEL_t;
1193
1194 /*
1195 * MPUREG_INT_CONFIG1
1196 * Register Name: INT_CONFIG1
1197 */
1198
1199 /* INT_TPULSE_DURATION */
1200 #define BIT_INT_TPULSE_DURATION_POS 6
1201 #define BIT_INT_TPULSE_DURATION_MASK (0x1 << BIT_INT_TPULSE_DURATION_POS)
1202
1203 typedef enum
1204 {
1205 ICM426XX_INT_TPULSE_DURATION_8_US = (0x1 << BIT_INT_TPULSE_DURATION_POS),
1206 ICM426XX_INT_TPULSE_DURATION_100_US = (0x0 << BIT_INT_TPULSE_DURATION_POS),
1207 } ICM426XX_INT_TPULSE_DURATION_t;
1208
1209 /* INT_TDEASSERT_DISABLE */
1210 #define BIT_INT_TDEASSERT_POS 5
1211 #define BIT_INT_TDEASSERT_MASK (0x1 << BIT_INT_TDEASSERT_POS)
1212
1213 typedef enum
1214 {
1215 ICM426XX_INT_TDEASSERT_DISABLED = (0x1 << BIT_INT_TDEASSERT_POS),
1216 ICM426XX_INT_TDEASSERT_ENABLED = (0x0 << BIT_INT_TDEASSERT_POS),
1217 } ICM426XX_INT_TDEASSERT_t;
1218
1219 /* ASY_RESET_DISABLE */
1220 #define BIT_INT_CONFIG1_ASY_RST_POS 4
1221 #define BIT_INT_CONFIG1_ASY_RST_MASK (0x1 << BIT_INT_CONFIG1_ASY_RST_POS)
1222
1223 typedef enum
1224 {
1225 ICM426XX_INT_CONFIG1_ASY_RST_DISABLED = (0x1 << BIT_INT_CONFIG1_ASY_RST_POS),
1226 ICM426XX_INT_CONFIG1_ASY_RST_ENABLED = (0x0 << BIT_INT_CONFIG1_ASY_RST_POS),
1227 } ICM426XX_INT_CONFIG1_ASY_RST_t;
1228
1229 /*
1230 * MPUREG_INT_SOURCE0
1231 * Register Name: INT_SOURCE0
1232 */
1233 #define BIT_INT_UI_FSYNC_INT_EN_POS 6
1234 #define BIT_INT_PLL_RDY_INT_EN_POS 5
1235 #define BIT_INT_RESET_DONE_INT_EN_POS 4
1236 #define BIT_INT_UI_DRDY_INT_EN_POS 3
1237 #define BIT_INT_FIFO_THS_INT_EN_POS 2
1238 #define BIT_INT_FIFO_FULL_INT_EN_POS 1
1239 #define BIT_INT_UI_AGC_RDY_INT_EN_POS 0
1240
1241 #define BIT_INT_SOURCE0_UI_FSYNC_INT1_EN 0x40
1242 #define BIT_INT_SOURCE0_PLL_RDY_INT1_EN 0x20
1243 #define BIT_INT_SOURCE0_RESET_DONE_INT1_EN 0x10
1244 #define BIT_INT_SOURCE0_UI_DRDY_INT1_EN 0x08
1245 #define BIT_INT_SOURCE0_FIFO_THS_INT1_EN 0x04
1246 #define BIT_INT_SOURCE0_FIFO_FULL_INT1_EN 0x02
1247 #define BIT_INT_SOURCE0_UI_AGC_RDY_INT1_EN 0x01
1248
1249 /*
1250 * MPUREG_INT_SOURCE1
1251 * Register Name: INT_SOURCE1
1252 */
1253 #define BIT_INT_SMD_INT_EN_POS 3
1254 #define BIT_INT_WOM_Z_INT_EN_POS 2
1255 #define BIT_INT_WOM_Y_INT_EN_POS 1
1256 #define BIT_INT_WOM_X_INT_EN_POS 0
1257
1258 #define BIT_INT_SOURCE1_SMD_INT1_EN 0x08
1259 #define BIT_INT_SOURCE1_WOM_Z_INT1_EN 0x04
1260 #define BIT_INT_SOURCE1_WOM_Y_INT1_EN 0x02
1261 #define BIT_INT_SOURCE1_WOM_X_INT1_EN 0x01
1262
1263 /*
1264 * MPUREG_INT_SOURCE2
1265 * Register Name: INT_SOURCE2
1266 */
1267 #define BIT_INT_SOURCE2_OIS2_AGC_RDY_INT1_EN 0x20
1268 #define BIT_INT_SOURCE2_OIS2_FSYNC_INT1_EN 0x10
1269 #define BIT_INT_SOURCE2_OIS2_DRDY_INT1_EN 0x08
1270 #define BIT_INT_SOURCE2_OIS1_AGC_RDY_INT1_EN 0x04
1271 #define BIT_INT_SOURCE2_OIS1_FSYNC_INT1_EN 0x02
1272 #define BIT_INT_SOURCE2_OIS1_DRDY_INT1_EN 0x01
1273
1274 /*
1275 * MPUREG_INT_SOURCE3
1276 * Register Name: INT_SOURCE3
1277 */
1278 #define BIT_INT_SOURCE3_UI_FSYNC_INT2_EN 0x40
1279 #define BIT_INT_SOURCE3_PLL_RDY_INT2_EN 0x20
1280 #define BIT_INT_SOURCE3_RESET_DONE_INT2_EN 0x10
1281 #define BIT_INT_SOURCE3_UI_DRDY_INT2_EN 0x08
1282 #define BIT_INT_SOURCE3_FIFO_THS_INT2_EN 0x04
1283 #define BIT_INT_SOURCE3_FIFO_FULL_INT2_EN 0x02
1284 #define BIT_INT_SOURCE3_UI_AGC_RDY_INT2_EN 0x01
1285
1286 /*
1287 * MPUREG_INT_SOURCE4
1288 * Register Name: INT_SOURCE4
1289 */
1290 #define BIT_INT_SOURCE4_SMD_INT2_EN 0x08
1291 #define BIT_INT_SOURCE4_WOM_Z_INT2_EN 0x04
1292 #define BIT_INT_SOURCE4_WOM_Y_INT2_EN 0x02
1293 #define BIT_INT_SOURCE4_WOM_X_INT2_EN 0x01
1294
1295 /*
1296 * MPUREG_INT_SOURCE5
1297 * Register Name: INT_SOURCE5
1298 */
1299 #define BIT_INT_SOURCE5_OIS2_AGC_RDY_INT2_EN 0x20
1300 #define BIT_INT_SOURCE5_OIS2_FSYNC_INT2_EN 0x10
1301 #define BIT_INT_SOURCE5_OIS2_DRDY_INT2_EN 0x08
1302 #define BIT_INT_SOURCE5_OIS1_AGC_RDY_INT2_EN 0x04
1303 #define BIT_INT_SOURCE5_OIS1_FSYNC_INT2_EN 0x02
1304 #define BIT_INT_SOURCE5_OIS1_DRDY_INT2_EN 0x01
1305
1306 /*
1307 * MPUREG_SELF_TEST_CONFIG
1308 * Register Name: SELF_TEST_CONFIG
1309 */
1310 #define BIT_ST_REGULATOR_EN 0x40
1311 #define BIT_ACCEL_Z_ST_EN 0x20
1312 #define BIT_ACCEL_Y_ST_EN 0x10
1313 #define BIT_ACCEL_X_ST_EN 0x08
1314 #define BIT_GYRO_Z_ST_EN 0x04
1315 #define BIT_GYRO_Y_ST_EN 0x02
1316 #define BIT_GYRO_X_ST_EN 0x01
1317
1318
1319 /*
1320 * MPUREG_SCAN0
1321 * Register Name: SCAN0
1322 */
1323 #define BIT_DMP_MEM_ACCESS_EN 0x08
1324 #define BIT_MEM_OTP_ACCESS_EN 0x04
1325 #define BIT_FIFO_MEM_RD_SYS 0x02
1326 #define BIT_FIFO_MEM_WR_SER 0x01
1327
1328 /* ----------------------------------------------------------------------------
1329 * Register bank 1
1330 * ---------------------------------------------------------------------------- */
1331
1332 #define BIT_SENSOR_CONFIG2_OIS_MODE_POS 4
1333 #define BIT_SENSOR_CONFIG2_OIS_MODE_MASK (0x03 << BIT_SENSOR_CONFIG2_OIS_MODE_POS)
1334
1335 typedef enum
1336 {
1337 ICM426XX_SENSOR_CONFIG2_OIS_MODE_32KHZ = (0x2 << BIT_SENSOR_CONFIG2_OIS_MODE_POS),
1338 ICM426XX_SENSOR_CONFIG2_OIS_MODE_8KHZ = (0x1 << BIT_SENSOR_CONFIG2_OIS_MODE_POS),
1339 ICM426XX_SENSOR_CONFIG2_OIS_MODE_DIS = (0x0 << BIT_SENSOR_CONFIG2_OIS_MODE_POS)
1340 } ICM426XX_SENSOR_CONFIG2_OIS_MODE_t;
1341
1342
1343 /*
1344 * MPUREG_GYRO_CONFIG_STATIC2_B1
1345 * Register Name: GYRO_CONFIG_STATIC2
1346 */
1347
1348 /* GYRO_AAF_DIS */
1349 #define BIT_GYRO_AAF_DIS_POS 1
1350 #define BIT_GYRO_AAF_DIS_MASK (0x01 << BIT_GYRO_AAF_DIS_POS)
1351
1352 typedef enum
1353 {
1354 ICM426XX_GYRO_AAF_EN = (0x0 << BIT_GYRO_AAF_DIS_POS),
1355 ICM426XX_GYRO_AAF_DIS = (0x1 << BIT_GYRO_AAF_DIS_POS),
1356 } ICM426XX_GYRO_AAF_DIS_t;
1357
1358 /* GYRO_NF_DIS */
1359 #define BIT_GYRO_NF_DIS_POS 0
1360 #define BIT_GYRO_NF_DIS_MASK (0x01 << BIT_GYRO_NF_DIS_POS)
1361 typedef enum
1362 {
1363 ICM426XX_GYRO_NF_EN = (0x0 << BIT_GYRO_NF_DIS_POS),
1364 ICM426XX_GYRO_NF_DIS = (0x1 << BIT_GYRO_NF_DIS_POS),
1365 } ICM426XX_GYRO_NF_DIS_t;
1366
1367 /*
1368 * MPUREG_GYRO_CONFIG_STATIC3_B1
1369 * Register Name: GYRO_CONFIG_STATIC3
1370 */
1371
1372 /* GYRO_AAF_DELT */
1373 #define BIT_GYRO_AAF_DELT_POS 0
1374 #define BIT_GYRO_AAF_DELT_MASK (0x3F << BIT_GYRO_AAF_DELT_POS)
1375
1376 /*
1377 * MPUREG_GYRO_CONFIG_STATIC4_B1
1378 * Register Name: GYRO_CONFIG_STATIC4
1379 */
1380
1381 /* GYRO_AAF_DELTSQR */
1382 #define BIT_GYRO_AAF_DELTSQR_POS_LO 0
1383 #define BIT_GYRO_AAF_DELTSQR_MASK_LO (0xFF << BIT_GYRO_AAF_DELTSQR_POS_LO)
1384
1385 /*
1386 * MPUREG_GYRO_CONFIG_STATIC5_B1
1387 * Register Name: GYRO_CONFIG_STATIC5
1388 */
1389
1390 #define BIT_GYRO_AAF_DELTSQR_POS_HI 0
1391 #define BIT_GYRO_AAF_DELTSQR_MASK_HI (0x0F << BIT_GYRO_AAF_DELTSQR_POS_HI)
1392
1393 /* GYRO_AAF_BITSHIFT */
1394 #define BIT_GYRO_AAF_BITSHIFT_POS 4
1395 #define BIT_GYRO_AAF_BITSHIFT_MASK (0x0F << BIT_GYRO_AAF_BITSHIFT_POS)
1396
1397 /*
1398 * MPUREG_INTF_CONFIG4_B1
1399 * Register Name: INTF_CONFIG4
1400 */
1401
1402 /* SPI_AP_4WIRE */
1403 #define BIT_INTF_CONFIG4_AP_SPI_POS 1
1404 #define BIT_INTF_CONFIG4_AP_SPI_MASK (0x1 << BIT_INTF_CONFIG4_AP_SPI_POS)
1405
1406 typedef enum
1407 {
1408 ICM426XX_INTF_CONFIG4_AP_SPI4W = (0x1 << BIT_INTF_CONFIG4_AP_SPI_POS),
1409 ICM426XX_INTF_CONFIG4_AP_SPI3W = (0x0 << BIT_INTF_CONFIG4_AP_SPI_POS),
1410 } ICM426XX_INTF_CONFIG4_AP_SPI_t;
1411
1412 /* SPI_AUX1_4WIRE */
1413 #define BIT_INTF_CONFIG4_AUX1_SPI_POS 2
1414 #define BIT_INTF_CONFIG4_AUX1_SPI_MASK (0x1 << BIT_INTF_CONFIG4_AUX1_SPI_POS)
1415
1416 typedef enum
1417 {
1418 ICM426XX_INTF_CONFIG4_AUX1_SPI4W = (0x1 << BIT_INTF_CONFIG4_AUX1_SPI_POS),
1419 ICM426XX_INTF_CONFIG4_AUX1_SPI3W = (0x0 << BIT_INTF_CONFIG4_AUX1_SPI_POS),
1420 } ICM426XX_INTF_CONFIG4_AUX1_SPI_t;
1421
1422 /*
1423 * MPUREG_INTF_CONFIG5_B1
1424 * Register Name: INTF_CONFIG5
1425 */
1426
1427 /* GPIO_PAD_SEL */
1428 #define BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS 1
1429 #define BIT_INTF_CONFIG5_GPIO_PAD_SEL_MASK (0x3 << BIT_INTF_CONFIG5_GPIO_PAD_SEL_POS)
1430
1431 /*
1432 * MPUREG_INTF_CONFIG6_B1
1433 * Register Name: INTF_CONFIG6
1434 */
1435
1436 /* I3C_DDR_EN */
1437 #define BIT_INTF_CONFIG6_I3C_DDR_EN_POS 1
1438 #define BIT_INTF_CONFIG6_I3C_DDR_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_DDR_EN_POS)
1439
1440 /* I3C_SDR_EN */
1441 #define BIT_INTF_CONFIG6_I3C_SDR_EN_POS 0
1442 #define BIT_INTF_CONFIG6_I3C_SDR_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_SDR_EN_POS)
1443
1444 /*
1445 * MPUREG_INTF_CONFIG6_B1
1446 * Register Name: INTF_CONFIG6
1447 */
1448
1449 /* I3C_IBI_BYTE_EN */
1450 #define BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS 3
1451 #define BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_IBI_BYTE_EN_POS)
1452
1453 /* I3C_IBI_EN */
1454 #define BIT_INTF_CONFIG6_I3C_IBI_EN_POS 2
1455 #define BIT_INTF_CONFIG6_I3C_IBI_EN_MASK (0x1 << BIT_INTF_CONFIG6_I3C_IBI_EN_POS)
1456
1457 /* ----------------------------------------------------------------------------
1458 * Register bank 2
1459 * ---------------------------------------------------------------------------- */
1460
1461 /*
1462 * MPUREG_ACCEL_CONFIG_STATIC2_B2
1463 * Register Name: ACCEL_CONFIG_STATIC2
1464 */
1465
1466 /* ACCEL_AAF_DIS */
1467 #define BIT_ACCEL_AAF_DIS_POS 0
1468 #define BIT_ACCEL_AAF_DIS_MASK (0x01 << BIT_ACCEL_AAF_DIS_POS)
1469
1470 typedef enum
1471 {
1472 ICM426XX_ACCEL_AAF_EN = (0x0 << BIT_ACCEL_AAF_DIS_POS),
1473 ICM426XX_ACCEL_AAF_DIS = (0x1 << BIT_ACCEL_AAF_DIS_POS),
1474 } ICM426XX_ACCEL_AAF_DIS_t;
1475
1476 /* ACCEL_AAF_DELT */
1477 #define BIT_ACCEL_AAF_DELT_POS 1
1478 #define BIT_ACCEL_AAF_DELT_MASK (0x3F << BIT_ACCEL_AAF_DELT_POS)
1479
1480 /*
1481 * MPUREG_ACCEL_CONFIG_STATIC3_B2
1482 * Register Name: ACCEL_CONFIG_STATIC3
1483 */
1484
1485 /* ACCEL_AAF_DELTSQR */
1486 #define BIT_ACCEL_AAF_DELTSQR_POS_LO 0
1487 #define BIT_ACCEL_AAF_DELTSQR_MASK_LO (0xFF << BIT_ACCEL_AAF_DELTSQR_POS_LO)
1488
1489 /*
1490 * MPUREG_ACCEL_CONFIG_STATIC4_B2
1491 * Register Name: ACCEL_CONFIG_STATIC4
1492 */
1493
1494 /* ACCEL_AAF_DELTSQR */
1495 #define BIT_ACCEL_AAF_DELTSQR_POS_HI 0
1496 #define BIT_ACCEL_AAF_DELTSQR_MASK_HI (0x0F << BIT_ACCEL_AAF_DELTSQR_POS_HI)
1497
1498 /* ACCEL_AAF_BITSHIFT */
1499 #define BIT_ACCEL_AAF_BITSHIFT_POS 4
1500 #define BIT_ACCEL_AAF_BITSHIFT_MASK (0x0F << BIT_ACCEL_AAF_BITSHIFT_POS)
1501
1502 /*
1503 * MPUREG_OIS1_CONFIG1_B2
1504 * Register Name: OIS1_CONFIG1
1505 */
1506
1507 /* OIS1_ACCEL_LP_CLK_SEL */
1508 #define BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS 5
1509 #define BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_MASK (0x1 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS)
1510
1511 typedef enum
1512 {
1513 ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC = (0x0 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS),
1514 ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC = (0x1 << BIT_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_POS),
1515 } ICM426XX_OIS1_CONFIG1_ACCEL_LP_CLK_SEL_t;
1516
1517 /* OIS1_DEC */
1518 #define BIT_OIS1_CONFIG1_DEC_POS 2
1519 #define BIT_OIS1_CONFIG1_DEC_MASK (0x7 << BIT_OIS1_CONFIG1_DEC_POS)
1520
1523 typedef enum
1524 {
1525 ICM426XX_OIS1_CONFIG1_DEC_1 = (0x0 << BIT_OIS1_CONFIG1_DEC_POS),
1526 ICM426XX_OIS1_CONFIG1_DEC_2 = (0x1 << BIT_OIS1_CONFIG1_DEC_POS),
1527 ICM426XX_OIS1_CONFIG1_DEC_4 = (0x2 << BIT_OIS1_CONFIG1_DEC_POS),
1528 ICM426XX_OIS1_CONFIG1_DEC_8 = (0x3 << BIT_OIS1_CONFIG1_DEC_POS),
1529 ICM426XX_OIS1_CONFIG1_DEC_16 = (0x4 << BIT_OIS1_CONFIG1_DEC_POS),
1530 ICM426XX_OIS1_CONFIG1_DEC_32 = (0x5 << BIT_OIS1_CONFIG1_DEC_POS),
1531 } ICM426XX_OIS1_CONFIG1_DEC_t;
1532
1533 /* GYRO_OIS1_EN */
1534 #define BIT_OIS1_CONFIG1_GYRO_EN_POS 1
1535 #define BIT_OIS1_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS1_CONFIG1_GYRO_EN_POS)
1536
1537 typedef enum
1538 {
1539 ICM426XX_OIS1_CONFIG1_GYRO_EN = (0x1 << BIT_OIS1_CONFIG1_GYRO_EN_POS),
1540 ICM426XX_OIS1_CONFIG1_GYRO_DIS = (0x0 << BIT_OIS1_CONFIG1_GYRO_EN_POS),
1541 } ICM426XX_OIS1_CONFIG1_GYRO_EN_t;
1542
1543 /* ACCEL_OIS1_EN */
1544 #define BIT_OIS1_CONFIG1_ACCEL_EN_POS 0
1545 #define BIT_OIS1_CONFIG1_ACCEL_EN_MASK (0x1 << BIT_OIS1_CONFIG1_ACCEL_EN_POS)
1546
1547 typedef enum
1548 {
1549 ICM426XX_OIS1_CONFIG1_ACCEL_EN = (0x1 << BIT_OIS1_CONFIG1_ACCEL_EN_POS),
1550 ICM426XX_OIS1_CONFIG1_ACCEL_DIS = (0x0 << BIT_OIS1_CONFIG1_ACCEL_EN_POS),
1551 } ICM426XX_OIS1_CONFIG1_ACCEL_EN_t;
1552
1553 /*
1554 * MPUREG_OIS1_CONFIG2_B2
1555 * Register Name: OIS1_CONFIG2
1556 */
1557
1558 /* GYRO_OIS1_FS_SEL */
1559 #define BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS 3
1560 #define BIT_OIS1_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS)
1561
1564 typedef enum
1565 {
1566 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_16dps = (0x7 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1567 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_31dps = (0x6 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1568 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_62dps = (0x5 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1569 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_125dps = (0x4 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1570 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_250dps = (0x3 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1571 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_500dps = (0x2 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1572 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_1000dps = (0x1 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1573 ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_2000dps = (0x0 << BIT_OIS1_CONFIG2_GYRO_FS_SEL_POS),
1574 } ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_t;
1575
1576 /* ACCEL_OIS1_FS_SEL */
1577 #define BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS 0
1578 #define BIT_OIS1_CONFIG2_ACCEL_FS_SEL_MASK (0x7 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS)
1579
1582 typedef enum
1583 {
1584 ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_RESERVED = (0x4 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1585 ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_2g = (0x3 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1586 ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_4g = (0x2 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1587 ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_8g = (0x1 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1588 ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_16g = (0x0 << BIT_OIS1_CONFIG2_ACCEL_FS_SEL_POS),
1589 } ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_t;
1590
1591 /*
1592 * MPUREG_INT_STATUS_OIS1_B2
1593 * Register Name: INT_STATUS_OIS1
1594 */
1595 #define BIT_INT_STATUS_OIS1_FSYNC 0x04
1596 #define BIT_INT_STATUS_OIS1_DRDY 0x02
1597 #define BIT_INT_STATUS_OIS1_AGC_RDY 0x01
1598
1599 /*
1600 * MPUREG_OIS2_CONFIG1_B2
1601 * Register Name: OIS2_CONFIG1
1602 */
1603
1604 /* OIS2_ACCEL_LP_CLK_SEL */
1605 #define BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS 5
1606 #define BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_MASK (0x1 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS)
1607
1608 typedef enum
1609 {
1610 ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_WUOSC = (0x0 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS),
1611 ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_RCOSC = (0x1 << BIT_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_POS),
1612 } ICM426XX_OIS2_CONFIG1_ACCEL_LP_CLK_SEL_t;
1613
1614 /* OIS2_DEC */
1615 #define BIT_OIS2_CONFIG1_DEC_POS 2
1616 #define BIT_OIS2_CONFIG1_DEC_MASK (0x7 << BIT_OIS2_CONFIG1_DEC_POS)
1617
1620 typedef enum
1621 {
1622 ICM426XX_OIS2_CONFIG1_DEC_1 = (0x0 << BIT_OIS2_CONFIG1_DEC_POS),
1623 ICM426XX_OIS2_CONFIG1_DEC_2 = (0x1 << BIT_OIS2_CONFIG1_DEC_POS),
1624 ICM426XX_OIS2_CONFIG1_DEC_4 = (0x2 << BIT_OIS2_CONFIG1_DEC_POS),
1625 ICM426XX_OIS2_CONFIG1_DEC_8 = (0x3 << BIT_OIS2_CONFIG1_DEC_POS),
1626 ICM426XX_OIS2_CONFIG1_DEC_16 = (0x4 << BIT_OIS2_CONFIG1_DEC_POS),
1627 ICM426XX_OIS2_CONFIG1_DEC_32 = (0x5 << BIT_OIS2_CONFIG1_DEC_POS),
1628 } ICM426XX_OIS2_CONFIG1_DEC_t;
1629
1630 /* GYRO_OIS2_EN */
1631 #define BIT_OIS2_CONFIG1_GYRO_EN_POS 1
1632 #define BIT_OIS2_CONFIG1_GYRO_EN_MASK (0x1 << BIT_OIS2_CONFIG1_GYRO_EN_POS)
1633
1634 typedef enum
1635 {
1636 ICM426XX_OIS2_CONFIG1_GYRO_EN = (0x1 << BIT_OIS2_CONFIG1_GYRO_EN_POS),
1637 ICM426XX_OIS2_CONFIG1_GYRO_DIS = (0x0 << BIT_OIS2_CONFIG1_GYRO_EN_POS),
1638 } ICM426XX_OIS2_CONFIG1_GYRO_EN_t;
1639
1640 /* ACCEL_OIS2_EN */
1641 #define BIT_OIS2_CONFIG1_ACCEL_EN_POS 0
1642 #define BIT_OIS2_CONFIG1_ACCEL_EN_MASK (0x1 << BIT_OIS2_CONFIG1_ACCEL_EN_POS)
1643
1644 typedef enum
1645 {
1646 ICM426XX_OIS2_CONFIG1_ACCEL_EN = (0x1 << BIT_OIS2_CONFIG1_ACCEL_EN_POS),
1647 ICM426XX_OIS2_CONFIG1_ACCEL_DIS = (0x0 << BIT_OIS2_CONFIG1_ACCEL_EN_POS),
1648 } ICM426XX_OIS2_CONFIG1_ACCEL_EN_t;
1649
1650 /*
1651 * MPUREG_OIS2_CONFIG2_B2
1652 * Register Name: OIS2_CONFIG2
1653 */
1654
1655 /* GYRO_OIS2_FS_SEL */
1656 #define BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS 3
1657 #define BIT_OIS2_CONFIG2_GYRO_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS)
1658
1661 typedef enum
1662 {
1663 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_16dps = (0x7 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1664 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_31dps = (0x6 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1665 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_62dps = (0x5 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1666 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_125dps = (0x4 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1667 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_250dps = (0x3 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1668 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_500dps = (0x2 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1669 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_1000dps = (0x1 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1670 ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_2000dps = (0x0 << BIT_OIS2_CONFIG2_GYRO_FS_SEL_POS),
1671 } ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_t;
1672
1673 /* ACCEL_OIS2_FS_SEL */
1674 #define BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS 0
1675 #define BIT_OIS2_CONFIG2_ACCEL_FS_SEL_MASK (0x7 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS)
1676
1679 typedef enum
1680 {
1681 ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_RESERVED = (0x4 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1682 ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_2g = (0x3 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1683 ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_4g = (0x2 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1684 ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_8g = (0x1 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1685 ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_16g = (0x0 << BIT_OIS2_CONFIG2_ACCEL_FS_SEL_POS),
1686 } ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_t;
1687
1688
1689 /*
1690 * MPUREG_INT_STATUS_OIS2_B2
1691 * Register Name: INT_STATUS_OIS2
1692 */
1693 #define BIT_INT_STATUS_OIS2_FSYNC 0x04
1694 #define BIT_INT_STATUS_OIS2_DRDY 0x02
1695 #define BIT_INT_STATUS_OIS2_AGC_RDY 0x01
1696
1697
1698 /* ----------------------------------------------------------------------------
1699 * Register bank 4
1700 * ---------------------------------------------------------------------------- */
1701
1702 /*
1703 * MPUREG_FDR_CONFIG_B4
1704 * Register Name: FDR_CONFIG
1705 */
1706
1707 /* FDR_SEL */
1708
1709 #define BIT_FDR_CONFIG_FDR_SEL_POS 0
1710 #define BIT_FDR_CONFIG_FDR_SEL_MASK 0x7F
1711
1712 /*
1713 * MPUREG_APEX_CONFIG1_B4
1714 * Register Name: APEX_CONFIG1
1715 */
1716
1717 /* DMP_POWER_SAVE_TIME_SEL */
1718
1719 #define BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_POS 0
1720 #define BIT_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_MASK 0x0F
1721
1722 typedef enum
1723 {
1724 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_0S = 0x0,
1725 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_4S = 0x1,
1726 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_8S = 0x2,
1727 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_12S = 0x3,
1728 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_16S = 0x4,
1729 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_20S = 0x5,
1730 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_24S = 0x6,
1731 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_28S = 0x7,
1732 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_32S = 0x8,
1733 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_36S = 0x9,
1734 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_40S = 0xA,
1735 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_44S = 0xB,
1736 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_48S = 0xC,
1737 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_52S = 0xD,
1738 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_56S = 0xE,
1739 ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_SEL_60S = 0xF
1740 } ICM426XX_APEX_CONFIG1_DMP_POWER_SAVE_TIME_t;
1741
1742 /* LOW_ENERGY_AMP_TH_SEL */
1743
1744 #define BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS 4
1745 #define BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_MASK (0x0F << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS)
1746
1747 typedef enum
1748 {
1749 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_30MG = (0 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1750 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_35MG = (1 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1751 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_40MG = (2 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1752 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_45MG = (3 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1753 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_50MG = (4 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1754 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_55MG = (5 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1755 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_60MG = (6 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1756 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_65MG = (7 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1757 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_70MG = (8 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1758 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_75MG = (9 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1759 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_80MG = (10 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1760 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_85MG = (11 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1761 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_90MG = (12 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1762 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_95MG = (13 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1763 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_100MG = (14 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS),
1764 ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_105MG = (15 << BIT_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_POS)
1765 } ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_t;
1766
1767 // Retro-compatibility
1768 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1006632MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_30MG
1769 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1174405MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_35MG
1770 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1342177MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_40MG
1771 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1509949MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_45MG
1772 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1677721MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_50MG
1773 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_1845493MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_55MG
1774 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2013265MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_60MG
1775 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2181038MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_65MG
1776 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2348810MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_70MG
1777 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2516582MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_75MG
1778 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2684354MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_80MG
1779 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_2852126MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_85MG
1780 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3019898MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_90MG
1781 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3187671MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_95MG
1782 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3355443MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_100MG
1783 #define ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_3523215MG ICM426XX_APEX_CONFIG1_LOW_ENERGY_AMP_TH_SEL_105MG
1784
1785 /*
1786 * MPUREG_APEX_CONFIG2_B4
1787 * Register Name: APEX_CONFIG2
1788 */
1789
1790 /* PEDO_AMP_TH_SEL */
1791
1792 #define BIT_APEX_CONFIG2_PEDO_AMP_TH_POS 4
1793 #define BIT_APEX_CONFIG2_PEDO_AMP_TH_MASK (0x0F<<BIT_APEX_CONFIG2_PEDO_AMP_TH_POS)
1794
1795 typedef enum
1796 {
1797 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_30MG = (0 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1798 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_34MG = (1 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1799 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_38MG = (2 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1800 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_42MG = (3 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1801 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_46MG = (4 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1802 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_50MG = (5 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1803 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_54MG = (6 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1804 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_58MG = (7 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1805 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_62MG = (8 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1806 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_66MG = (9 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1807 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_70MG = (10 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1808 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_74MG = (11 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1809 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_78MG = (12 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1810 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_82MG = (13 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1811 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_86MG = (14 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS),
1812 ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_90MG = (15 << BIT_APEX_CONFIG2_PEDO_AMP_TH_POS)
1813 } ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_t;
1814
1815 // Retro-compatibility
1816 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1006632_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_30MG
1817 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1140850_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_34MG
1818 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1275068_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_38MG
1819 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1409286_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_42MG
1820 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1543503_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_46MG
1821 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1677721_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_50MG
1822 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1811939_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_54MG
1823 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_1946157_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_58MG
1824 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2080374_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_62MG
1825 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2214592_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_66MG
1826 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2348810_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_70MG
1827 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2483027_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_74MG
1828 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2617245_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_78MG
1829 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2751463_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_82MG
1830 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_2885681_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_86MG
1831 #define ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_3019898_MG ICM426XX_APEX_CONFIG2_PEDO_AMP_TH_90MG
1832
1833
1834 /* PEDO_STEP_CNT_TH_SEL */
1835
1836 #define BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_POS 0
1837 #define BIT_APEX_CONFIG2_PEDO_STEP_CNT_TH_MASK 0x0F
1838
1839 /*
1840 * MPUREG_APEX_CONFIG3_B4
1841 * Register Name: APEX_CONFIG3
1842 */
1843
1844 /* PEDO_STEP_DET_TH_SEL */
1845
1846 #define BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS 5
1847 #define BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_MASK (0x07<<BIT_APEX_CONFIG3_PEDO_STEP_DET_TH_POS)
1848
1849 /* PEDO_SB_TIMER_TH_SEL */
1850
1851 #define BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS 2
1852 #define BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_MASK (0x07<<BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS)
1853
1854 typedef enum
1855 {
1856 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_50_SAMPLES = (0 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1857 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_75_SAMPLES = (1 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1858 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_100_SAMPLES = (2 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1859 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_125_SAMPLES = (3 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1860 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_150_SAMPLES = (4 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1861 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_175_SAMPLES = (5 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1862 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_200_SAMPLES = (6 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS),
1863 ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_225_SAMPLES = (7 << BIT_APEX_CONFIG3_PEDO_SB_TIMER_TH_POS)
1864 } ICM426XX_APEX_CONFIG3_PEDO_SB_TIMER_TH_t;
1865
1866 /* PEDO_HI_ENRGY_TH_SEL */
1867
1868 #define BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_POS 0
1869 #define BIT_APEX_CONFIG3_PEDO_HI_ENRGY_TH_MASK 0x03
1870
1871 typedef enum
1872 {
1873 ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_90 = 0x0,
1874 ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_107 = 0x1,
1875 ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_136 = 0x2,
1876 ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_159 = 0x3
1877 } ICM426XX_APEX_CONFIG3_PEDO_HI_ENRGY_TH_t;
1878
1879 /*
1880 * MPUREG_APEX_CONFIG4_B4
1881 * Register Name: APEX_CONFIG4
1882 */
1883
1884 /* TILT_WAIT_TIME_SEL */
1885
1886 #define BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS 6
1887 #define BIT_APEX_CONFIG4_TILT_WAIT_TIME_MASK (0x03<<BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS)
1888
1889 typedef enum
1890 {
1891 ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_0S = (0 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS),
1892 ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_2S = (1 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS),
1893 ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_4S = (2 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS),
1894 ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_6S = (3 << BIT_APEX_CONFIG4_TILT_WAIT_TIME_POS)
1895 } ICM426XX_APEX_CONFIG4_TILT_WAIT_TIME_t;
1896
1897 #if defined(ICM_FAMILY_BPLUS)
1898 /* R2W_SLEEP_TIME_OUT */
1899
1900 #define BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS 3
1901 #define BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_MASK (0x07<<BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS)
1902
1903 typedef enum
1904 {
1905 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_1_28S = (0 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1906 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_2_56S = (1 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1907 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_3_84S = (2 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1908 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_5_12S = (3 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1909 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_6_4S = (4 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1910 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_7_68S = (5 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1911 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_8_96S = (6 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS),
1912 ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_10_24S = (7 << BIT_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_POS)
1913 } ICM426XX_APEX_CONFIG4_R2W_SLEEP_TIME_OUT_t;
1914
1915 /*
1916 * MPUREG_APEX_CONFIG5_B4
1917 * Register Name: APEX_CONFIG5
1918 */
1919
1920 /* R2W_MOUNTING_MATRIX */
1921
1922 #define BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS 0
1923 #define BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_MASK (0x07<<BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS)
1924
1925 typedef enum
1926 {
1927 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_0 = (0 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1928 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_1 = (1 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1929 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_2 = (2 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1930 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_3 = (3 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1931 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_4 = (4 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1932 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_5 = (5 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1933 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_6 = (6 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS),
1934 ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_7 = (7 << BIT_APEX_CONFIG5_R2W_MOUNTING_MATRIX_POS)
1935 } ICM426XX_APEX_CONFIG5_R2W_MOUNTING_MATRIX_t;
1936
1937 /*
1938 * MPUREG_APEX_CONFIG6_B4
1939 * Register Name: APEX_CONFIG6
1940 */
1941
1942 /* R2W_SLEEP_GEST_DELAY */
1943
1944 #define BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS 0
1945 #define BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_MASK (0x07<<BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS)
1946
1947 typedef enum
1948 {
1949 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_32S = (0 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1950 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_64S = (1 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1951 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_0_96S = (2 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1952 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_28S = (3 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1953 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_6S = (4 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1954 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_1_92S = (5 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1955 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_24S = (6 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS),
1956 ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_2_56S = (7 << BIT_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_POS)
1957 } ICM426XX_APEX_CONFIG6_R2W_SLEEP_GEST_DELAY_t;
1958
1959 #elif defined(ICM_FAMILY_CPLUS)
1960
1961 /* LOWG_PEAK_TH_HYST */
1962
1963 #define BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS 3
1964 #define BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_MASK (0x07<<BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS)
1965
1966 typedef enum
1967 {
1968 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_31MG = (0 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS),
1969 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_63MG = (1 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS),
1970 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_94MG = (2 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS),
1971 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_125MG = (3 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS),
1972 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_156MG = (4 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS),
1973 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_188MG = (5 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS),
1974 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_219MG = (6 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS),
1975 ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_250MG = (7 << BIT_APEX_CONFIG4_LOWG_PEAK_TH_HYST_POS)
1976 } ICM426XX_APEX_CONFIG4_LOWG_PEAK_TH_HYST_t;
1977
1978 /* HIGHG_PEAK_TH_HYST */
1979
1980 #define BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS 0
1981 #define BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_MASK (0x07<<BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS)
1982
1983 typedef enum
1984 {
1985 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_31MG = (0 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS),
1986 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_63MG = (1 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS),
1987 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_94MG = (2 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS),
1988 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_125MG = (3 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS),
1989 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_156MG = (4 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS),
1990 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_188MG = (5 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS),
1991 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_219MG = (6 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS),
1992 ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_250MG = (7 << BIT_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_POS)
1993 } ICM426XX_APEX_CONFIG4_HIGHG_PEAK_TH_HYST_t;
1994
1995 /*
1996 * MPUREG_APEX_CONFIG5_B4
1997 * Register Name: APEX_CONFIG5
1998 */
1999
2000 /* LOWG_PEAK_TH */
2001
2002 #define BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS 3
2003 #define BIT_APEX_CONFIG5_LOWG_PEAK_TH_MASK (0x1f<<BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS)
2004
2005 typedef enum
2006 {
2007 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_31MG = (0x00 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2008 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_63MG = (0x01 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2009 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_94MG = (0x02 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2010 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_125MG = (0x03 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2011 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_156MG = (0x04 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2012 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_188MG = (0x05 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2013 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_219MG = (0x06 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2014 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_250MG = (0x07 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2015 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_281MG = (0x08 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2016 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_313MG = (0x09 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2017 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_344MG = (0x0A << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2018 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_375MG = (0x0B << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2019 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_406MG = (0x0C << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2020 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_438MG = (0x0D << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2021 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_469MG = (0x0E << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2022 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_500MG = (0x0F << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2023 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_531MG = (0x10 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2024 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_563MG = (0x11 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2025 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_594MG = (0x12 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2026 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_625MG = (0x13 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2027 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_656MG = (0x14 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2028 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_688MG = (0x15 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2029 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_719MG = (0x16 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2030 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_750MG = (0x17 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2031 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_781MG = (0x18 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2032 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_813MG = (0x19 << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2033 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_844MG = (0x1A << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2034 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_875MG = (0x1B << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2035 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_906MG = (0x1C << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2036 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_938MG = (0x1D << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2037 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_969MG = (0x1E << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS),
2038 ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_1000MG = (0x1F << BIT_APEX_CONFIG5_LOWG_PEAK_TH_POS)
2039 } ICM426XX_APEX_CONFIG5_LOWG_PEAK_TH_t;
2040
2041 /* LOWG_TIME_TH */
2042
2043 #define BIT_APEX_CONFIG5_LOWG_TIME_TH_POS 0
2044 #define BIT_APEX_CONFIG5_LOWG_TIME_TH_MASK (0x07<<BIT_APEX_CONFIG5_LOWG_TIME_TH_POS)
2045
2046 typedef enum
2047 {
2048 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_1_SAMPLE = (0x00 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS),
2049 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_2_SAMPLES = (0x01 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS),
2050 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_3_SAMPLES = (0x02 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS),
2051 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_4_SAMPLES = (0x03 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS),
2052 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_5_SAMPLES = (0x04 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS),
2053 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_6_SAMPLES = (0x05 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS),
2054 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_7_SAMPLES = (0x06 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS),
2055 ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_8_SAMPLES = (0x07 << BIT_APEX_CONFIG5_LOWG_TIME_TH_POS)
2056 } ICM426XX_APEX_CONFIG5_LOWG_TIME_TH_SAMPLES_t;
2057
2058 /*
2059 * MPUREG_APEX_CONFIG6_B4
2060 * Register Name: APEX_CONFIG6
2061 */
2062 /* HIGHG_PEAK_TH */
2063
2064 #define BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS 3
2065 #define BIT_APEX_CONFIG6_HIGHG_PEAK_TH_MASK (0x1f<<BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS)
2066
2067 typedef enum
2068 {
2069 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_250MG = (0x00 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2070 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_500MG = (0x01 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2071 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_750MG = (0x02 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2072 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_1000MG = (0x03 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2073 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_1250MG = (0x04 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2074 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_1500MG = (0x05 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2075 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_1750MG = (0x06 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2076 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_2000MG = (0x07 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2077 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_2250MG = (0x08 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2078 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_2500MG = (0x09 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2079 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_2750MG = (0x0A << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2080 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_3000MG = (0x0B << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2081 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_3250MG = (0x0C << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2082 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_3500MG = (0x0D << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2083 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_3750MG = (0x0E << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2084 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_4000MG = (0x0F << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2085 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_4250MG = (0x10 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2086 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_4500MG = (0x11 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2087 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_4750MG = (0x12 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2088 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_5000MG = (0x13 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2089 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_5250MG = (0x14 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2090 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_5500MG = (0x15 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2091 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_5750MG = (0x16 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2092 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_6000MG = (0x17 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2093 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_6250MG = (0x18 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2094 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_6500MG = (0x19 << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2095 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_6750MG = (0x1A << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2096 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_7000MG = (0x1B << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2097 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_7250MG = (0x1C << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2098 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_7500MG = (0x1D << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2099 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_7750MG = (0x1E << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS),
2100 ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_8000MG = (0x1F << BIT_APEX_CONFIG6_HIGHG_PEAK_TH_POS)
2101 } ICM426XX_APEX_CONFIG6_HIGHG_PEAK_TH_t;
2102
2103 /* HIGHG_TIME_TH */
2104
2105 #define BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS 0
2106 #define BIT_APEX_CONFIG6_HIGHG_TIME_TH_MASK (0x07<<BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS)
2107
2108 typedef enum
2109 {
2110 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_1_SAMPLE = (0x00 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS),
2111 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_2_SAMPLES = (0x01 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS),
2112 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_3_SAMPLES = (0x02 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS),
2113 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_4_SAMPLES = (0x03 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS),
2114 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_5_SAMPLES = (0x04 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS),
2115 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_6_SAMPLES = (0x05 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS),
2116 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_7_SAMPLES = (0x06 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS),
2117 ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_8_SAMPLES = (0x07 << BIT_APEX_CONFIG6_HIGHG_TIME_TH_POS)
2118 } ICM426XX_APEX_CONFIG6_HIGHG_TIME_TH_SAMPLES_t;
2119
2120 #endif
2121
2122 /*
2123 * MPUREG_APEX_CONFIG7_B4
2124 * Register Name: APEX_CONFIG7
2125 */
2126
2127 /* TAP_MIN_JERK_THR */
2128 #define BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS 2
2129 #define BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_MASK (0x3F << BIT_APEX_CONFIG7_TAP_MIN_JERK_THR_POS)
2130
2131 #define ICM426XX_APEX_CONFIG7_TAP_MIN_JERK_THR_281MG_DEFAULT 0x11
2132
2133 /* TAP_MAX_PEAK_TOL */
2134 #define BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_POS 0
2135 #define BIT_APEX_CONFIG7_TAP_MAX_PEAK_TOL_MASK 0x3
2136
2137 typedef enum
2138 {
2139 ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_12 = 0x0,
2140 ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_25 = 0x1,
2141 ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_37 = 0x2,
2142 ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_50 = 0x3
2143 } ICM426XX_APEX_CONFIG7_TAP_MAX_PEAK_TOL_t;
2144
2145 /*
2146 * MPUREG_APEX_CONFIG8_B4
2147 * Register Name: APEX_CONFIG8
2148 */
2149
2150 /* TAP_TMAX */
2151 #define BIT_APEX_CONFIG8_TAP_TMAX_POS 5
2152 #define BIT_APEX_CONFIG8_TAP_TMAX_MASK (0x03 << BIT_APEX_CONFIG8_TAP_TMAX_POS)
2153
2154 typedef enum
2155 {
2156 ICM426XX_APEX_CONFIG8_TAP_TMAX_250MS = (0 << BIT_APEX_CONFIG8_TAP_TMAX_POS),
2157 ICM426XX_APEX_CONFIG8_TAP_TMAX_375MS = (1 << BIT_APEX_CONFIG8_TAP_TMAX_POS),
2158 ICM426XX_APEX_CONFIG8_TAP_TMAX_500MS = (2 << BIT_APEX_CONFIG8_TAP_TMAX_POS),
2159 ICM426XX_APEX_CONFIG8_TAP_TMAX_625MS = (3 << BIT_APEX_CONFIG8_TAP_TMAX_POS)
2160 } ICM426XX_APEX_CONFIG8_TAP_TMAX_t;
2161
2162 /* TAP_TAVG */
2163 #define BIT_APEX_CONFIG8_TAP_TAVG_POS 3
2164 #define BIT_APEX_CONFIG8_TAP_TAVG_MASK (0x03 << BIT_APEX_CONFIG8_TAP_TAVG_POS)
2165
2166 typedef enum
2167 {
2168 ICM426XX_APEX_CONFIG8_TAP_TAVG_1SAMPLE = (0 << BIT_APEX_CONFIG8_TAP_TAVG_POS),
2169 ICM426XX_APEX_CONFIG8_TAP_TAVG_2SAMPLE = (1 << BIT_APEX_CONFIG8_TAP_TAVG_POS),
2170 ICM426XX_APEX_CONFIG8_TAP_TAVG_4SAMPLE = (2 << BIT_APEX_CONFIG8_TAP_TAVG_POS),
2171 ICM426XX_APEX_CONFIG8_TAP_TAVG_8SAMPLE = (3 << BIT_APEX_CONFIG8_TAP_TAVG_POS)
2172 } ICM426XX_APEX_CONFIG8_TAP_TAVG_t;
2173
2174 /* TAP_TMIN */
2175 #define BIT_APEX_CONFIG8_TAP_TMIN_POS 0
2176 #define BIT_APEX_CONFIG8_TAP_TMIN_MASK 0x07
2177
2178 typedef enum
2179 {
2180 ICM426XX_APEX_CONFIG8_TAP_TMIN_125MS = 0x0,
2181 ICM426XX_APEX_CONFIG8_TAP_TMIN_140MS = 0x1,
2182 ICM426XX_APEX_CONFIG8_TAP_TMIN_156MS = 0x2,
2183 ICM426XX_APEX_CONFIG8_TAP_TMIN_171MS = 0x3,
2184 ICM426XX_APEX_CONFIG8_TAP_TMIN_187MS = 0x4,
2185 ICM426XX_APEX_CONFIG8_TAP_TMIN_203MS = 0x5,
2186 ICM426XX_APEX_CONFIG8_TAP_TMIN_218MS = 0x6,
2187 ICM426XX_APEX_CONFIG8_TAP_TMIN_234MS = 0x7
2188 } ICM426XX_APEX_CONFIG8_TAP_TMIN_t;
2189
2190 /*
2191 * MPUREG_APEX_CONFIG9_B4
2192 * Register Name: APEX_CONFIG9
2193 */
2194 #define BIT_APEX_CONFIG9_SENSITIVITY_MODE_POS 0
2195 #define BIT_APEX_CONFIG9_SENSITIVITY_MODE_MASK 0x01
2196 typedef enum
2197 {
2198 ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_NORMAL = 0x00,
2199 ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_RESERVED = 0x01
2200 } ICM426XX_APEX_CONFIG9_SENSITIVITY_MODE_t;
2201
2202 #if defined(ICM_FAMILY_CPLUS)
2203
2204 /*
2205 * MPUREG_APEX_CONFIG10_B4
2206 * Register Name: APEX_CONFIG10
2207 */
2208
2209 /* FF_DEBOUNCE_DURATION */
2210 #define BIT_APEX_CONFIG10_FF_DEBOUNCE_DURATION_POS 0
2211 #define BIT_APEX_CONFIG10_FF_DEBOUNCE_DURATION_MASK (0x03 << BIT_APEX_CONFIG10_FF_DEBOUNCE_DURATION_POS)
2212
2213 typedef enum
2214 {
2215 ICM426XX_APEX_CONFIG10_FF_DEBOUNCE_DURATION_0_MS = (0 << BIT_APEX_CONFIG10_FF_DEBOUNCE_DURATION_POS),
2216 ICM426XX_APEX_CONFIG10_FF_DEBOUNCE_DURATION_1000_MS = (1 << BIT_APEX_CONFIG10_FF_DEBOUNCE_DURATION_POS),
2217 ICM426XX_APEX_CONFIG10_FF_DEBOUNCE_DURATION_2000_MS = (2 << BIT_APEX_CONFIG10_FF_DEBOUNCE_DURATION_POS),
2218 ICM426XX_APEX_CONFIG10_FF_DEBOUNCE_DURATION_3000_MS = (3 << BIT_APEX_CONFIG10_FF_DEBOUNCE_DURATION_POS)
2219 } ICM426XX_APEX_CONFIG10_FF_DEBOUNCE_DURATION_t;
2220
2221 /* FF_MAX_DURATION */
2222 #define BIT_APEX_CONFIG10_FF_MAX_DURATION_POS 2
2223 #define BIT_APEX_CONFIG10_FF_MAX_DURATION_MASK (0x07 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS)
2224
2225 typedef enum
2226 {
2227 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_113_CM = (0 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS),
2228 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_154_CM = (1 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS),
2229 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_201_CM = (2 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS),
2230 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_255_CM = (3 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS),
2231 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_314_CM = (4 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS),
2232 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_380_CM = (5 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS),
2233 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_452_CM = (6 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS),
2234 ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_531_CM = (7 << BIT_APEX_CONFIG10_FF_MAX_DURATION_POS)
2235 } ICM426XX_APEX_CONFIG10_FF_MAX_DURATION_t;
2236
2237 /* FF_MIN_DURATION */
2238 #define BIT_APEX_CONFIG10_FF_MIN_DURATION_POS 5
2239 #define BIT_APEX_CONFIG10_FF_MIN_DURATION_MASK (0x07 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS)
2240
2241 typedef enum
2242 {
2243 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_13_CM = (0 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS),
2244 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_19_CM = (1 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS),
2245 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_28_CM = (2 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS),
2246 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_38_CM = (3 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS),
2247 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_50_CM = (4 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS),
2248 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_64_CM = (5 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS),
2249 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_78_CM = (6 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS),
2250 ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_95_CM = (7 << BIT_APEX_CONFIG10_FF_MIN_DURATION_POS)
2251 } ICM426XX_APEX_CONFIG10_FF_MIN_DURATION_t;
2252
2253 #endif
2254
2255 /*
2256 * MPUREG_INT_SOURCE6_B4
2257 * Register Name: INT_SOURCE6
2258 */
2259 #define BIT_INT_STEP_DET_INT_EN_POS 5
2260 #define BIT_INT_STEP_CNT_OVFL_INT_EN_POS 4
2261 #define BIT_INT_TILT_DET_INT_EN_POS 3
2262 #if defined(ICM_FAMILY_BPLUS)
2263 #define BIT_INT_WAKE_DET_INT_EN_POS 2
2264 #define BIT_INT_SLEEP_DET_INT_EN_POS 1
2265 #elif defined(ICM_FAMILY_CPLUS)
2266 #define BIT_INT_LOWG_DET_INT_EN_POS 2
2267 #define BIT_INT_FF_DET_INT_EN_POS 1
2268 #endif
2269 #define BIT_INT_TAP_DET_INT_EN_POS 0
2270
2271 #define BIT_INT_SOURCE6_STEP_DET_INT1_EN 0x20
2272 #define BIT_INT_SOURCE6_STEP_CNT_OVFL_INT1_EN 0x10
2273 #define BIT_INT_SOURCE6_TILT_DET_INT1_EN 0x8
2274 #if defined(ICM_FAMILY_BPLUS)
2275 #define BIT_INT_SOURCE6_WAKE_DET_INT1_EN 0x4
2276 #define BIT_INT_SOURCE6_SLEEP_DET_INT1_EN 0x2
2277 #elif defined(ICM_FAMILY_CPLUS)
2278 #define BIT_INT_SOURCE6_LOWG_DET_INT1_EN 0x4
2279 #define BIT_INT_SOURCE6_FF_DET_INT1_EN 0x2
2280 #endif
2281 #define BIT_INT_SOURCE6_TAP_DET_INT1_EN 0x1
2282
2283 /*
2284 * MPUREG_INT_SOURCE7_B4
2285 * Register Name: INT_SOURCE7
2286 */
2287 #define BIT_INT_SOURCE7_STEP_DET_INT2_EN 0x20
2288 #define BIT_INT_SOURCE7_STEP_CNT_OVFL_INT2_EN 0x10
2289 #define BIT_INT_SOURCE7_TILT_DET_INT2_EN 0x8
2290 #if defined(ICM_FAMILY_BPLUS)
2291 #define BIT_INT_SOURCE7_WAKE_DET_INT2_EN 0x4
2292 #define BIT_INT_SOURCE7_SLEEP_DET_INT2_EN 0x2
2293 #elif defined(ICM_FAMILY_CPLUS)
2294 #define BIT_INT_SOURCE7_LOWG_DET_INT2_EN 0x4
2295 #define BIT_INT_SOURCE7_FF_DET_INT2_EN 0x2
2296 #endif
2297 #define BIT_INT_SOURCE7_TAP_DET_INT2_EN 0x1
2298
2299 /*
2300 * MPUREG_INT_SOURCE8_B4
2301 * Register Name: INT_SOURCE8
2302 */
2303 #define BIT_INT_OIS1_DRDY_IBI_EN_POS 6
2304 #define BIT_INT_UI_FSYNC_IBI_EN_POS 5
2305 #define BIT_INT_PLL_RDY_IBI_EN_POS 4
2306 #define BIT_INT_UI_DRDY_IBI_EN_POS 3
2307 #define BIT_INT_FIFO_THS_IBI_EN_POS 2
2308 #define BIT_INT_FIFO_FULL_IBI_EN_POS 1
2309 #define BIT_INT_UI_AGC_RDY_IBI_EN_POS 0
2310
2311 #define BIT_INT_SOURCE8_OIS1_DRDY_IBI_EN 0x40
2312 #define BIT_INT_SOURCE8_UI_FSYNC_IBI_EN 0x20
2313 #define BIT_INT_SOURCE8_PLL_RDY_IBI_EN 0x10
2314 #define BIT_INT_SOURCE8_UI_DRDY_IBI_EN 0x08
2315 #define BIT_INT_SOURCE8_FIFO_THS_IBI_EN 0x04
2316 #define BIT_INT_SOURCE8_FIFO_FULL_IBI_EN 0x02
2317 #define BIT_INT_SOURCE8_UI_AGC_RDY_IBI_EN 0x01
2318
2319 /*
2320 * MPUREG_INT_SOURCE9_B4
2321 * Register Name: INT_SOURCE9
2322 */
2323 #define BIT_INT_SMD_IBI_EN_POS 4
2324 #define BIT_INT_WOM_Z_IBI_EN_POS 3
2325 #define BIT_INT_WOM_Y_IBI_EN_POS 2
2326 #define BIT_INT_WOM_X_IBI_EN_POS 1
2327
2328 #define BIT_INT_SOURCE9_SMD_IBI_EN 0x10
2329 #define BIT_INT_SOURCE9_WOM_Z_IBI_EN 0x08
2330 #define BIT_INT_SOURCE9_WOM_Y_IBI_EN 0x04
2331 #define BIT_INT_SOURCE9_WOM_X_IBI_EN 0x02
2332
2333 /*
2334 * MPUREG_INT_SOURCE10_B4
2335 * Register Name: INT_SOURCE10
2336 */
2337 #define BIT_INT_STEP_DET_IBI_EN_POS 5
2338 #define BIT_INT_STEP_CNT_OVFL_IBI_EN_POS 4
2339 #define BIT_INT_TILT_DET_IBI_EN_POS 3
2340 #if defined(ICM_FAMILY_BPLUS)
2341 #define BIT_INT_WAKE_DET_IBI_EN_POS 2
2342 #define BIT_INT_SLEEP_DET_IBI_EN_POS 1
2343 #elif defined(ICM_FAMILY_CPLUS)
2344 #define BIT_INT_LOWG_DET_IBI_EN_POS 2
2345 #define BIT_INT_FF_DET_IBI_EN_POS 1
2346 #endif
2347 #define BIT_INT_TAP_DET_IBI_EN_POS 0
2348
2349 #define BIT_INT_SOURCE10_STEP_DET_IBI_EN 0x20
2350 #define BIT_INT_SOURCE10_STEP_CNT_OVFL_IBI_EN 0x10
2351 #define BIT_INT_SOURCE10_TILT_DET_IBI_EN 0x08
2352 #if defined(ICM_FAMILY_BPLUS)
2353 #define BIT_INT_SOURCE10_WAKE_DET_IBI_EN 0x04
2354 #define BIT_INT_SOURCE10_SLEEP_DET_IBI_EN 0x02
2355 #elif defined(ICM_FAMILY_CPLUS)
2356 #define BIT_INT_SOURCE10_LOWG_DET_IBI_EN 0x04
2357 #define BIT_INT_SOURCE10_FF_DET_IBI_EN 0x02
2358 #endif
2359 #define BIT_INT_SOURCE10_TAP_DET_IBI_EN 0x01
2360
2361 /*
2362 * MPUREG_OFFSET_USER_0_B4
2363 * Register Name: OFFSET_USER0
2364 */
2365
2366 /* GYRO_X_OFFUSER */
2367 #define BIT_GYRO_X_OFFUSER_POS_LO 0
2368 #define BIT_GYRO_X_OFFUSER_MASK_LO (0xFF << BIT_GYRO_X_OFFUSER_POS_LO)
2369
2370 /*
2371 * MPUREG_OFFSET_USER_1_B4
2372 * Register Name: OFFSET_USER1
2373 */
2374
2375 #define BIT_GYRO_X_OFFUSER_POS_HI 0
2376 #define BIT_GYRO_X_OFFUSER_MASK_HI (0x0F << BIT_GYRO_X_OFFUSER_POS_HI)
2377
2378 /* GYRO_Y_OFFUSER */
2379 #define BIT_GYRO_Y_OFFUSER_POS_HI 4
2380 #define BIT_GYRO_Y_OFFUSER_MASK_HI (0x0F << BIT_GYRO_Y_OFFUSER_POS_HI)
2381
2382 /*
2383 * MPUREG_OFFSET_USER_2_B4
2384 * Register Name: OFFSET_USER2
2385 */
2386
2387 #define BIT_GYRO_Y_OFFUSER_POS_LO 0
2388 #define BIT_GYRO_Y_OFFUSER_MASK_LO (0xFF << BIT_GYRO_Y_OFFUSER_POS_LO)
2389
2390 /*
2391 * MPUREG_OFFSET_USER_3_B4
2392 * Register Name: OFFSET_USER3
2393 */
2394
2395 /* GYRO_Z_OFFUSER */
2396 #define BIT_GYRO_Z_OFFUSER_POS_LO 0
2397 #define BIT_GYRO_Z_OFFUSER_MASK_LO (0xFF << BIT_GYRO_Z_OFFUSER_POS_LO)
2398
2399 /*
2400 * MPUREG_OFFSET_USER_4_B4
2401 * Register Name: OFFSET_USER4
2402 */
2403
2404 #define BIT_GYRO_Z_OFFUSER_POS_HI 0
2405 #define BIT_GYRO_Z_OFFUSER_MASK_HI (0x0F << BIT_GYRO_Z_OFFUSER_POS_HI)
2406
2407 /* ACCEL_X_OFFUSER */
2408 #define BIT_ACCEL_X_OFFUSER_POS_HI 4
2409 #define BIT_ACCEL_X_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_X_OFFUSER_POS_HI)
2410
2411 /*
2412 * MPUREG_OFFSET_USER_5_B4
2413 * Register Name: OFFSET_USER5
2414 */
2415
2416 #define BIT_ACCEL_X_OFFUSER_POS_LO 0
2417 #define BIT_ACCEL_X_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_X_OFFUSER_POS_LO)
2418
2419 /*
2420 * MPUREG_OFFSET_USER_6_B4
2421 * Register Name: OFFSET_USER_6
2422 */
2423
2424 /* ACCEL_Y_OFFUSER */
2425 #define BIT_ACCEL_Y_OFFUSER_POS_LO 0
2426 #define BIT_ACCEL_Y_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_Y_OFFUSER_POS_LO)
2427
2428
2429 /*
2430 * MPUREG_OFFSET_USER_7_B4
2431 * Register Name: OFFSET_USER_7
2432 */
2433
2434 #define BIT_ACCEL_Y_OFFUSER_POS_HI 0
2435 #define BIT_ACCEL_Y_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_Y_OFFUSER_POS_HI)
2436
2437 /* ACCEL_Z_OFFUSER */
2438 #define BIT_ACCEL_Z_OFFUSER_POS_HI 4
2439 #define BIT_ACCEL_Z_OFFUSER_MASK_HI (0x0F << BIT_ACCEL_Z_OFFUSER_POS_HI)
2440
2441 /*
2442 * MPUREG_OFFSET_USER_8_B4
2443 * Register Name: OFFSET_USER_8
2444 */
2445
2446 /* ACCEL_Z_OFFUSER_L */
2447 #define BIT_ACCEL_Z_OFFUSER_POS_LO 0
2448 #define BIT_ACCEL_Z_OFFUSER_MASK_LO (0xFF << BIT_ACCEL_Z_OFFUSER_POS_LO)
2449
2450 #ifdef __cplusplus
2451 }
2452 #endif
2453
2454 #endif /* #ifndef _INV_ICM426XX_DEFS_H_ */
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_t
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_t
OIS1 gyroscope FSR selection.
Definition: Icm426xxDefs.h:1565
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_31dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_31dps
31.25 dps
Definition: Icm426xxDefs.h:1567
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_250dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_250dps
250 dps
Definition: Icm426xxDefs.h:1570
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_2000dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_2000dps
2000 dps
Definition: Icm426xxDefs.h:1573
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_125dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_125dps
125 dps
Definition: Icm426xxDefs.h:1569
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_62dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_62dps
62.5 dps
Definition: Icm426xxDefs.h:1568
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_1000dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_1000dps
1000 dps
Definition: Icm426xxDefs.h:1572
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_500dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_500dps
500 dps
Definition: Icm426xxDefs.h:1571
ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_16dps
@ ICM426XX_OIS1_CONFIG2_GYRO_FS_SEL_16dps
15.625 dps
Definition: Icm426xxDefs.h:1566
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_t
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_t
OIS2 accelerometer FSR selection.
Definition: Icm426xxDefs.h:1680
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_2g
@ ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_2g
2g
Definition: Icm426xxDefs.h:1682
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_8g
@ ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_8g
8g
Definition: Icm426xxDefs.h:1684
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_16g
@ ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_16g
16g
Definition: Icm426xxDefs.h:1685
ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_4g
@ ICM426XX_OIS2_CONFIG2_ACCEL_FS_SEL_4g
4g
Definition: Icm426xxDefs.h:1683
ICM426XX_OIS1_CONFIG1_DEC_t
ICM426XX_OIS1_CONFIG1_DEC_t
OIS1 rate selection (base clock fixed by OTP divided by decimator value)
Definition: Icm426xxDefs.h:1524
ICM426XX_OIS1_CONFIG1_DEC_16
@ ICM426XX_OIS1_CONFIG1_DEC_16
OTP_OIS_clock / 16.
Definition: Icm426xxDefs.h:1529
ICM426XX_OIS1_CONFIG1_DEC_32
@ ICM426XX_OIS1_CONFIG1_DEC_32
OTP_OIS_clock / 32.
Definition: Icm426xxDefs.h:1530
ICM426XX_OIS1_CONFIG1_DEC_4
@ ICM426XX_OIS1_CONFIG1_DEC_4
OTP_OIS_clock / 4.
Definition: Icm426xxDefs.h:1527
ICM426XX_OIS1_CONFIG1_DEC_8
@ ICM426XX_OIS1_CONFIG1_DEC_8
OTP_OIS_clock / 8.
Definition: Icm426xxDefs.h:1528
ICM426XX_OIS1_CONFIG1_DEC_1
@ ICM426XX_OIS1_CONFIG1_DEC_1
OTP_OIS_clock / 1.
Definition: Icm426xxDefs.h:1525
ICM426XX_OIS1_CONFIG1_DEC_2
@ ICM426XX_OIS1_CONFIG1_DEC_2
OTP_OIS_clock / 2.
Definition: Icm426xxDefs.h:1526
ICM426XX_GYRO_CONFIG0_ODR_t
ICM426XX_GYRO_CONFIG0_ODR_t
Gyroscope ODR selection.
Definition: Icm426xxDefs.h:773
ICM426XX_GYRO_CONFIG0_ODR_25_HZ
@ ICM426XX_GYRO_CONFIG0_ODR_25_HZ
25 Hz (40 ms)
Definition: Icm426xxDefs.h:776
ICM426XX_GYRO_CONFIG0_ODR_50_HZ
@ ICM426XX_GYRO_CONFIG0_ODR_50_HZ
50 Hz (20 ms)
Definition: Icm426xxDefs.h:777
ICM426XX_GYRO_CONFIG0_ODR_16_KHZ
@ ICM426XX_GYRO_CONFIG0_ODR_16_KHZ
16 KHz (62.5 us)
Definition: Icm426xxDefs.h:784
ICM426XX_GYRO_CONFIG0_ODR_100_HZ
@ ICM426XX_GYRO_CONFIG0_ODR_100_HZ
100 Hz (10 ms)
Definition: Icm426xxDefs.h:778
ICM426XX_GYRO_CONFIG0_ODR_1_KHZ
@ ICM426XX_GYRO_CONFIG0_ODR_1_KHZ
1 KHz (1 ms)
Definition: Icm426xxDefs.h:780
ICM426XX_GYRO_CONFIG0_ODR_32_KHZ
@ ICM426XX_GYRO_CONFIG0_ODR_32_KHZ
32 KHz (31.25 us)
Definition: Icm426xxDefs.h:785
ICM426XX_GYRO_CONFIG0_ODR_2_KHZ
@ ICM426XX_GYRO_CONFIG0_ODR_2_KHZ
2 KHz (500 us)
Definition: Icm426xxDefs.h:781
ICM426XX_GYRO_CONFIG0_ODR_12_5_HZ
@ ICM426XX_GYRO_CONFIG0_ODR_12_5_HZ
12.5 Hz (80 ms)
Definition: Icm426xxDefs.h:775
ICM426XX_GYRO_CONFIG0_ODR_500_HZ
@ ICM426XX_GYRO_CONFIG0_ODR_500_HZ
500 Hz (2 ms)
Definition: Icm426xxDefs.h:774
ICM426XX_GYRO_CONFIG0_ODR_200_HZ
@ ICM426XX_GYRO_CONFIG0_ODR_200_HZ
200 Hz (5 ms)
Definition: Icm426xxDefs.h:779
ICM426XX_GYRO_CONFIG0_ODR_8_KHZ
@ ICM426XX_GYRO_CONFIG0_ODR_8_KHZ
8 KHz (125 us)
Definition: Icm426xxDefs.h:783
ICM426XX_GYRO_CONFIG0_ODR_4_KHZ
@ ICM426XX_GYRO_CONFIG0_ODR_4_KHZ
4 KHz (250 us)
Definition: Icm426xxDefs.h:782
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_t
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_t
OIS1 accelerometer FSR selection.
Definition: Icm426xxDefs.h:1583
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_4g
@ ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_4g
4g
Definition: Icm426xxDefs.h:1586
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_8g
@ ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_8g
8g
Definition: Icm426xxDefs.h:1587
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_16g
@ ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_16g
16g
Definition: Icm426xxDefs.h:1588
ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_2g
@ ICM426XX_OIS1_CONFIG2_ACCEL_FS_SEL_2g
2g
Definition: Icm426xxDefs.h:1585
ICM426XX_ACCEL_CONFIG0_FS_SEL_t
ICM426XX_ACCEL_CONFIG0_FS_SEL_t
Accelerometer FSR selection.
Definition: Icm426xxDefs.h:800
ICM426XX_ACCEL_CONFIG0_FS_SEL_16g
@ ICM426XX_ACCEL_CONFIG0_FS_SEL_16g
16g
Definition: Icm426xxDefs.h:812
ICM426XX_ACCEL_CONFIG0_FS_SEL_2g
@ ICM426XX_ACCEL_CONFIG0_FS_SEL_2g
2g
Definition: Icm426xxDefs.h:809
ICM426XX_ACCEL_CONFIG0_FS_SEL_8g
@ ICM426XX_ACCEL_CONFIG0_FS_SEL_8g
8g
Definition: Icm426xxDefs.h:811
ICM426XX_ACCEL_CONFIG0_FS_SEL_4g
@ ICM426XX_ACCEL_CONFIG0_FS_SEL_4g
4g
Definition: Icm426xxDefs.h:810
BIT_APEX_DATA4_TAP_NUM_POS
#define BIT_APEX_DATA4_TAP_NUM_POS
TAP status flags: non-zero value - tap detected bit0 - positive or negative edge bit1 and 2 - axis de...
Definition: Icm426xxDefs.h:489
ICM426XX_OIS2_CONFIG1_DEC_t
ICM426XX_OIS2_CONFIG1_DEC_t
OIS2 rate selection (base clock fixed by OTP divided by decimator value)
Definition: Icm426xxDefs.h:1621
ICM426XX_OIS2_CONFIG1_DEC_4
@ ICM426XX_OIS2_CONFIG1_DEC_4
OTP_OIS_clock / 4.
Definition: Icm426xxDefs.h:1624
ICM426XX_OIS2_CONFIG1_DEC_16
@ ICM426XX_OIS2_CONFIG1_DEC_16
OTP_OIS_clock / 16.
Definition: Icm426xxDefs.h:1626
ICM426XX_OIS2_CONFIG1_DEC_8
@ ICM426XX_OIS2_CONFIG1_DEC_8
OTP_OIS_clock / 8.
Definition: Icm426xxDefs.h:1625
ICM426XX_OIS2_CONFIG1_DEC_2
@ ICM426XX_OIS2_CONFIG1_DEC_2
OTP_OIS_clock / 2.
Definition: Icm426xxDefs.h:1623
ICM426XX_OIS2_CONFIG1_DEC_32
@ ICM426XX_OIS2_CONFIG1_DEC_32
OTP_OIS_clock / 32.
Definition: Icm426xxDefs.h:1627
ICM426XX_OIS2_CONFIG1_DEC_1
@ ICM426XX_OIS2_CONFIG1_DEC_1
OTP_OIS_clock / 1.
Definition: Icm426xxDefs.h:1622
ICM426XX_GYRO_CONFIG0_FS_SEL_t
ICM426XX_GYRO_CONFIG0_FS_SEL_t
Gyroscope FSR selection.
Definition: Icm426xxDefs.h:744
ICM426XX_GYRO_CONFIG0_FS_SEL_2000dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_2000dps
2000dps
Definition: Icm426xxDefs.h:762
ICM426XX_GYRO_CONFIG0_FS_SEL_125dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_125dps
125dps
Definition: Icm426xxDefs.h:758
ICM426XX_GYRO_CONFIG0_FS_SEL_500dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_500dps
500dps
Definition: Icm426xxDefs.h:760
ICM426XX_GYRO_CONFIG0_FS_SEL_16dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_16dps
16dps
Definition: Icm426xxDefs.h:755
ICM426XX_GYRO_CONFIG0_FS_SEL_62dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_62dps
62dps
Definition: Icm426xxDefs.h:757
ICM426XX_GYRO_CONFIG0_FS_SEL_250dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_250dps
250dps
Definition: Icm426xxDefs.h:759
ICM426XX_GYRO_CONFIG0_FS_SEL_1000dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_1000dps
1000dps
Definition: Icm426xxDefs.h:761
ICM426XX_GYRO_CONFIG0_FS_SEL_31dps
@ ICM426XX_GYRO_CONFIG0_FS_SEL_31dps
31dps
Definition: Icm426xxDefs.h:756
ICM426XX_APEX_CONFIG0_DMP_ODR_t
ICM426XX_APEX_CONFIG0_DMP_ODR_t
DMP ODR selection.
Definition: Icm426xxDefs.h:1062
ICM426XX_APEX_CONFIG0_DMP_ODR_50Hz
@ ICM426XX_APEX_CONFIG0_DMP_ODR_50Hz
50Hz (20ms)
Definition: Icm426xxDefs.h:1064
ICM426XX_APEX_CONFIG0_DMP_ODR_25Hz
@ ICM426XX_APEX_CONFIG0_DMP_ODR_25Hz
25Hz (40ms)
Definition: Icm426xxDefs.h:1063
ICM426XX_APEX_CONFIG0_DMP_ODR_500Hz
@ ICM426XX_APEX_CONFIG0_DMP_ODR_500Hz
500Hz (40ms)
Definition: Icm426xxDefs.h:1066
ICM426XX_APEX_CONFIG0_DMP_ODR_100Hz
@ ICM426XX_APEX_CONFIG0_DMP_ODR_100Hz
100Hz (10ms)
Definition: Icm426xxDefs.h:1065
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_t
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_t
OIS2 gyroscope FSR selection.
Definition: Icm426xxDefs.h:1662
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_1000dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_1000dps
1000 dps
Definition: Icm426xxDefs.h:1669
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_31dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_31dps
31.25 dps
Definition: Icm426xxDefs.h:1664
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_500dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_500dps
500 dps
Definition: Icm426xxDefs.h:1668
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_16dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_16dps
15.625 dps
Definition: Icm426xxDefs.h:1663
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_250dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_250dps
250 dps
Definition: Icm426xxDefs.h:1667
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_2000dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_2000dps
2000 dps
Definition: Icm426xxDefs.h:1670
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_62dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_62dps
62.5 dps
Definition: Icm426xxDefs.h:1665
ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_125dps
@ ICM426XX_OIS2_CONFIG2_GYRO_FS_SEL_125dps
125 dps
Definition: Icm426xxDefs.h:1666
ICM426XX_ACCEL_CONFIG0_ODR_t
ICM426XX_ACCEL_CONFIG0_ODR_t
Accelerometer ODR selection.
Definition: Icm426xxDefs.h:823
ICM426XX_ACCEL_CONFIG0_ODR_1_KHZ
@ ICM426XX_ACCEL_CONFIG0_ODR_1_KHZ
1 KHz (1 ms)
Definition: Icm426xxDefs.h:833
ICM426XX_ACCEL_CONFIG0_ODR_2_KHZ
@ ICM426XX_ACCEL_CONFIG0_ODR_2_KHZ
2 KHz (500 us)
Definition: Icm426xxDefs.h:834
ICM426XX_ACCEL_CONFIG0_ODR_8_KHZ
@ ICM426XX_ACCEL_CONFIG0_ODR_8_KHZ
8 KHz (125 us)
Definition: Icm426xxDefs.h:836
ICM426XX_ACCEL_CONFIG0_ODR_1_5625_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_1_5625_HZ
1.5625 Hz (640 ms)
Definition: Icm426xxDefs.h:825
ICM426XX_ACCEL_CONFIG0_ODR_50_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_50_HZ
50 Hz (20 ms)
Definition: Icm426xxDefs.h:830
ICM426XX_ACCEL_CONFIG0_ODR_12_5_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_12_5_HZ
12.5 Hz (80 ms)
Definition: Icm426xxDefs.h:828
ICM426XX_ACCEL_CONFIG0_ODR_200_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_200_HZ
200 Hz (5 ms)
Definition: Icm426xxDefs.h:832
ICM426XX_ACCEL_CONFIG0_ODR_6_25_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_6_25_HZ
6.25 Hz (160 ms)
Definition: Icm426xxDefs.h:827
ICM426XX_ACCEL_CONFIG0_ODR_32_KHZ
@ ICM426XX_ACCEL_CONFIG0_ODR_32_KHZ
32 KHz (31.25 us)
Definition: Icm426xxDefs.h:838
ICM426XX_ACCEL_CONFIG0_ODR_500_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_500_HZ
500 Hz (2 ms)
Definition: Icm426xxDefs.h:824
ICM426XX_ACCEL_CONFIG0_ODR_25_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_25_HZ
25 Hz (40 ms)
Definition: Icm426xxDefs.h:829
ICM426XX_ACCEL_CONFIG0_ODR_100_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_100_HZ
100 Hz (10 ms)
Definition: Icm426xxDefs.h:831
ICM426XX_ACCEL_CONFIG0_ODR_3_125_HZ
@ ICM426XX_ACCEL_CONFIG0_ODR_3_125_HZ
3.125 Hz (320 ms)
Definition: Icm426xxDefs.h:826
ICM426XX_ACCEL_CONFIG0_ODR_4_KHZ
@ ICM426XX_ACCEL_CONFIG0_ODR_4_KHZ
4 KHz (250 us)
Definition: Icm426xxDefs.h:835
ICM426XX_ACCEL_CONFIG0_ODR_16_KHZ
@ ICM426XX_ACCEL_CONFIG0_ODR_16_KHZ
16 KHz (62.5 us)
Definition: Icm426xxDefs.h:837
fifo_header_t
Describe the content of the FIFO header.
Definition: Icm426xxDefs.h:287