/**
 * \file
 *
 * \brief SAMV71 Xplained Ultra board configuration
 *
 * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
 *
 * \asf_license_start
 *
 * \page License
 *
 * Subject to your compliance with these terms, you may use Microchip
 * software and any derivatives exclusively with Microchip products.
 * It is your responsibility to comply with third party license terms applicable
 * to your use of third party software (including open source software) that
 * may accompany Microchip software.
 *
 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
 * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
 * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
 * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
 * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
 * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
 * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
 * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
 * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
 * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
 *
 * \asf_license_stop
 */
/*
 * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
 */

#ifndef CONF_BOARD_H
#define CONF_BOARD_H

/* Enable ICache and DCache */
#define CONF_BOARD_ENABLE_CACHE_AT_INIT

#define CONF_BOARD_USART_RXD
#define CONF_BOARD_USART_TXD
#define CONF_BOARD_USART_SCK
#define CONF_BOARD_USART_CTS
#define CONF_BOARD_USART_RTS

/** Enable Com Port. */
#define CONF_BOARD_UART_CONSOLE

/** UART MACRO definition */
#define CONF_BOARD_UART_FLAMENCO

/** PCK definition */
#define CONF_BOARD_PCK

/** SPI MACRO definition */
#define CONF_BOARD_SPI

/** SPI slave select MACRO definition */
#define CONF_BOARD_SPI_NPCS0

/** Spi Hw ID . */
#define SPI_ID          ID_SPI0

/** SPI base address for SPI master mode*/
#define SPI_MASTER_BASE      SPI0

/** RESET pin for Flamenco */
#define FLA_RESET_GPIO            (PIO_PD11_IDX)
#define FLA_RESET_FLAGS           (0)
#define FLA_RESET_ACTIVE_LEVEL    (IOPORT_PIN_LEVEL_LOW)
#define FLA_RESET_INACTIVE_LEVEL  (IOPORT_PIN_LEVEL_HIGH)

/*External Interrupt setup for PA19*/
#define PIN_EXT_INTERRUPT	{PIO_PA19, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT | PIO_IT_RISE_EDGE}
#define PIN_EXT_INTERRUPT_MASK	PIO_PA19
#define PIN_EXT_INTERRUPT_PIO	PIOA
#define PIN_EXT_INTERRUPT_ID	ID_PIOA
#define PIN_EXT_INTERRUPT_TYPE	PIO_INPUT
#define PIN_EXT_INTERRUPT_ATTR	(PIO_DEFAULT | PIO_IT_RISE_EDGE)
#define PIN_EXT_INTERRUPT_IRQn	PIOA_IRQn

/** UART4 pins definitions, PD18,PD19. */
#define UART4_RXD_GPIO   PIO_PD18_IDX
#define UART4_RXD_FLAGS  IOPORT_MODE_MUX_C
#define UART4_TXD_GPIO   PIO_PD19_IDX
#define UART4_TXD_FLAGS  IOPORT_MODE_MUX_C

/** Programmable Clock ID for the example by default */
#ifndef GCLK_ID
#define GCLK_ID         PMC_PCK_0
#endif
/** Programmable Clock Pin for the example by default */
#ifndef GCLK_PIN
#define GCLK_PIN        PIN_PCK0
#endif
/** Programmable Clock Pin Mux for the example by default */
#ifndef GCLK_PIN_MUX
#define GCLK_PIN_MUX    PIN_PCK0_MUX
#endif

#endif /* CONF_BOARD_H */
